CN113131905A - Schmitt trigger circuit - Google Patents
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- CN113131905A CN113131905A CN201911392816.2A CN201911392816A CN113131905A CN 113131905 A CN113131905 A CN 113131905A CN 201911392816 A CN201911392816 A CN 201911392816A CN 113131905 A CN113131905 A CN 113131905A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
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Abstract
The application discloses Schmitt trigger circuit, including comparator circuit, inverter circuit, buffer and feedback circuit, comparator circuit is used for comparing input signal and threshold voltage, in order to generate first signal, inverter circuit is used for producing the second signal according to this first signal, the buffer is used for shaping the second signal in order to obtain output signal, feedback circuit is used for adjusting first signal according to output signal feedback, wherein, feedback circuit pulls down first signal to ground when input signal is greater than positive threshold voltage, and pull up first signal to mains voltage when input signal is less than negative-going threshold voltage, there is not the low resistance current channel of mains voltage to ground in the circuit, the during operation does not have extra quiescent current loss, applicable in low-power consumption device.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a Schmitt trigger circuit.
Background
A schmitt trigger is a special gate that has two threshold voltages, a positive threshold voltage and a negative threshold voltage. An input voltage, whose output state is inverted during a process in which an input signal rises from a low level (e.g., ground) to a high level (e.g., power supply voltage VCC), is referred to as a forward threshold voltage; an input voltage that causes its output state to flip during the process of the input signal falling from a high level (e.g., supply voltage VCC) to a low level (e.g., ground reference) is referred to as a negative threshold voltage.
Fig. 1 shows a circuit schematic of a schmitt trigger circuit according to the prior art. As shown in FIG. 1, the Schmitt trigger circuit 100 includes transistors Mp1-Mp3, transistors Mn1-Mn3, and a buffer BUF 1. The transistor Mp1, the transistor Mp2, the transistor Mn2 and the transistor Mn1 are sequentially connected in series between the power supply voltage VCC and the ground, and control terminals of the transistor Mp1, the transistor Mp2, the transistor Mn2 and the transistor Mn1 are connected to each other and all receive the input signal Vin. The control terminal of the transistor Mp3 is connected to the node B between the transistor Mp2 and the transistor Mn2, the first terminal of the transistor Mp3 is connected to the intermediate node between the transistor Mp1 and the transistor Mp2, and the second terminal of the transistor Mp3 is connected to ground. The control terminal of the transistor Mn3 is connected to the node B between the transistor Mp2 and the transistor Mn2, the first terminal of the transistor Mn3 is connected to the supply voltage VCC, and the second terminal of the transistor Mn3 is connected to the intermediate node of the transistors Mn1 and Mn 2. Buffer BUF1 has an input terminal coupled to node B and an output terminal for providing output signal Vout.
Fig. 2 shows a graph of the change in quiescent current of a prior art schmitt trigger circuit. In fig. 2, the horizontal axis represents the input signal Vin, and the vertical axis represents the quiescent current I of the schmitt trigger circuitCC，VILIndicating the negative threshold voltage, V, of the Schmitt trigger circuitIHRepresenting the positive threshold voltage of the schmitt trigger circuit. As shown in FIG. 2, when the input signal Vin is slightly larger than the forward threshold voltage VIHThe sum input signal Vin is slightly less than the negative threshold voltage VILStatic current I of time-delay circuitCCAre both large because when the input signal Vin is slightly larger than the forward threshold voltage VIHWhen node B is low, transistor Mp1 and transistor Mp3 are turned on, a low-resistance current path exists from the supply voltage VCC to ground, and when the input signal Vin is slightly less than the negative threshold voltage VILWhen node B is high, transistor Mn1 and transistor Mn3 are conductive, and a low-resistance current path exists in the circuit from the supply voltage VCC to ground, which results in a quiescent current I for the circuitCCIs relatively large. Normally, when the input signal Vin is at the positive threshold voltage VIHAnd a negative threshold voltage VILQuiescent current I of circuit at nearby timeCCCan reach about dozens of uA, and the Schmitt trigger circuit in the prior art cannot be suitable for low-power-consumption devices.
Disclosure of Invention
In view of the above, the present invention provides a schmitt trigger circuit suitable for low power devices.
According to an embodiment of the present invention, there is provided a schmitt trigger circuit including: a comparison circuit for comparing an input signal with a threshold voltage to generate a first signal; an inverter circuit for generating a second signal from the first signal; a buffer for shaping said second signal to obtain an output signal; and a feedback circuit for feedback conditioning the first signal based on the output signal, wherein the feedback circuit is configured to pull the first signal down to ground when the input signal is greater than a positive threshold voltage and pull the first signal up to a supply voltage when the input signal is less than a negative threshold voltage.
Preferably, the schmitt trigger circuit further comprises a bias circuit for providing a bias current to the comparison circuit.
Preferably, the bias circuit includes: a first transistor having a first terminal connected to a power supply voltage, a control terminal connected to a second terminal thereof, and a second terminal; a current source having a first terminal connected to the second terminal of the first transistor and a second terminal connected to ground, wherein the bias current flows through the first transistor.
Preferably, the comparison circuit includes: a second transistor having a first terminal connected to the power supply voltage, a control terminal connected to the control terminal of the first transistor, and a second terminal; a third transistor having a first terminal connected to the second terminal of the second transistor, a control terminal for receiving the input signal, and a second terminal connected to the feedback circuit, wherein a first node between the second transistor and the third transistor is for providing the first signal.
Preferably, the feedback circuit includes: a resistor having a first terminal connected to the second terminal of the third transistor and a second terminal connected to ground; a fourth transistor having a first terminal connected to the second terminal of the third transistor, a control terminal for receiving the output signal, and a second terminal connected to ground.
Preferably, the inverter circuit includes: fifth to eighth transistors connected in series in sequence between the power supply voltage and ground, control terminals of the fifth to eighth transistors being connected to the first node, a second node between the sixth transistor and the seventh transistor being configured to provide the second signal; a ninth transistor having a first terminal connected to an intermediate node of the fifth transistor and the sixth transistor, a control terminal connected to the second node, and a second terminal connected to ground; a tenth transistor having a first terminal connected to the power supply voltage, a control terminal connected to the second node, and a second terminal connected to an intermediate node of the seventh transistor and the eighth transistor.
Preferably, an input of the buffer is connected to the second node to receive the second signal, and an output is used to provide the output signal.
Preferably, the first transistor and the second transistor are P-type MOSFETs, and the third transistor and the fourth transistor are N-type MOSFETs.
Preferably, the fifth transistor, the sixth transistor, and the ninth transistor are P-type MOSFETs, and the seventh transistor, the eighth transistor, and the tenth transistor are N-type MOSFETs.
The Schmitt trigger circuit comprises a comparison circuit, an inverter circuit, a buffer and a feedback circuit, wherein the comparison circuit is used for comparing an input signal with a threshold voltage to generate a first signal, the inverter circuit is used for generating a second signal according to the first signal, the buffer is used for shaping the second signal to obtain an output signal, and the feedback circuit is used for regulating the first signal according to the output signal in a feedback mode.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a circuit schematic of a schmitt trigger circuit according to the prior art;
FIG. 2 shows a graph of the change in quiescent current of a prior art Schmitt trigger circuit;
FIG. 3 shows a circuit schematic of a Schmitt trigger circuit in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram showing changes in a first signal during operation of a Schmitt trigger circuit in accordance with an embodiment of the present invention;
fig. 5 shows graphs of the change in quiescent current for a schmitt trigger circuit of an embodiment of the present invention and a schmitt trigger circuit of the prior art, respectively.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
In this application, the MOSFET comprises a first terminal, a second terminal and a control terminal, and in the on-state of the MOSFET a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the P-type MOSFET are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the N-type MOSFET are respectively a drain electrode, a source electrode and a grid electrode.
Fig. 3 shows a circuit schematic of a schmitt trigger circuit according to an embodiment of the present invention. As shown in fig. 3, the schmitt trigger circuit 200 includes a bias circuit 210, a comparator circuit 220, an inverter circuit 230, a buffer BUF1, and a feedback circuit 240.
The bias circuit 210 is used to provide a bias current I1 to the comparison circuit 220. The comparison circuit 220 is used for comparing the input signal Vin with a threshold voltage to generate a first signal VA. The inverter circuit 230 is used for generating the second signal VB according to the first signal VA. The buffer BUF1 is used to shape the second signal VB to obtain the output signal Vout. The feedback circuit 240 is used for feedback-adjusting the first signal VA according to the output signal Vout. Wherein, the feedback circuit 240 is used for detecting whether the input signal Vin is greater than the forward threshold voltage VIHPull down the first signal VA to ground and when the input signal Vin is less than the negative threshold voltage VILThe first signal VA is pulled up to the supply voltage VCC.
Wherein the forward threshold voltage VIHThe voltage corresponding to the input signal Vin, which is inverted in output state, is obtained in the process that the input signal Vin rises from a low level (for example, ground) to a high level (for example, the power supply voltage VCC); negative threshold voltage VILThe voltage corresponding to the input signal Vin, whose output state is inverted, is generated in the process of the input signal Vin decreasing from a high level (e.g., the power supply voltage VCC) to a low level (e.g., the ground).
Further, the bias circuit 210 includes a transistor Mp1 and a current source 211 sequentially connected between the power supply voltage VCC and the ground, and a control terminal and a second terminal of the transistor Mp1 are connected to each other. The current source 211 is used to provide a bias current I1, and when the transistor Mp1 is turned on, the bias current I1 flows from the first terminal to the second terminal of the transistor Mp 1.
The comparison circuit 220 includes a transistor Mp2 and a transistor Mn 1. The transistor Mp2 has a first terminal connected to the power supply voltage VCC, a control terminal connected to the transistor Mp1, and the transistor Mp2 and the transistor Mp1 form a current mirror. The transistor Mn1 has a first terminal connected to the second terminal of the transistor Mp2, a control terminal for receiving the input signal Vin, and a second terminal connected to the feedback circuit 240. The node a between the transistor Mp2 and the transistor Mn1 is used to provide the first signal VA.
The inverter circuit 230 includes transistors Mp3-Mp5 and transistors Mn2-Mn 4. The transistor Mp3, the transistor Mp4, the transistor Mn3 and the transistor Mn2 are sequentially connected in series between the power supply voltage VCC and the ground, and control terminals of the transistor Mp3, the transistor Mp4, the transistor Mn3 and the transistor Mn2 are connected to each other and are all connected to the node a to receive the first signal VA. The control terminal of the transistor Mp5 is connected to the node B between the transistor Mp4 and the transistor Mn3, the first terminal of the transistor Mp5 is connected to the intermediate node between the transistor Mp3 and the transistor Mp4, and the second terminal of the transistor Mp5 is connected to ground. The control terminal of the transistor Mn4 is connected to the node B between the transistor Mp4 and the transistor Mn3, the first terminal of the transistor Mn4 is connected to the supply voltage VCC, and the second terminal is connected to the intermediate node between the transistor Mn3 and the transistor Mn 2.
Feedback circuit 240 includes resistor R1 and transistor Mn 5. The resistor R1 has a first terminal connected to the second terminal of the transistor Mn1, and a second terminal connected to ground. The first terminal of the transistor Mn5 is connected to the second terminal of the transistor Mn1, the second terminal is connected to ground, and the control terminal is configured to receive the output signal Vout.
In the above embodiment, the transistors Mn1-Mn5 are selected from N-type MOSFETs, and the transistors Mp1-Mp5 are selected from P-type MOSFETs.
Fig. 4 is a schematic diagram showing changes of the first signal during the operation of the schmitt trigger circuit according to the embodiment of the present invention, and the operation principle of the schmitt trigger according to the embodiment of the present invention will be described in detail with reference to fig. 3 and 4.
When the input signal Vin changes from 0 to the power supply voltage VCC, the transistor Mn1 is turned off and the node a is turned off when the voltage of the input signal Vin is lowThe transistor Mp2 is pulled high to approximately equal the supply voltage VCC, and when the output signal Vout is low, the transistor Mn5 is turned off. As the voltage of the input signal Vin gradually increases, the transistor Mn1 gradually turns on, and the potential of the node C is I1 × R1. When the equivalent impedance of the transistor Mn1 and the resistor R1 is smaller than the impedance of the transistor Mp2, the node A is pulled low, and the Schmitt trigger circuit can be enabled to be in a state that the input signal Vin is equal to the forward threshold voltage V by designing the size relationship between the transistors Mn1-Mn5 and the transistors Mp3-Mp5IHThe output signal Vout is inverted from low level to high level. Then, the transistor Mn5 is turned on, and the transistor Mn5 pulls the node C to ground, and the impedance of the transistor Mn1 is much smaller than that of the transistor Mp2, so the node a is also pulled to ground, i.e. the first signal VA is pulled to ground, as shown by curve 1 in fig. 4.
When the input signal Vin changes from the power voltage VCC to 0, when the voltage of the input signal Vin is high, the transistor Mn1 and the transistor Mn5 are turned on, the node a is pulled low to ground by the transistor Mn1, and the output signal Vout is at a high level. With the gradual reduction of the voltage of the input signal Vin, the transistor Mn1 is gradually turned off, the impedance of the transistor Mn1 is gradually increased, the node A is pulled high when the impedance of the transistor Mn1 is larger than that of the transistor Mp2, and by designing the size relationship between the transistors Mn1-Mn5 and the transistors Mp3-Mp5, the Schmitt trigger circuit can be enabled when the input signal Vin is equal to the negative threshold voltage VILThe inversion occurs when the output signal Vout is inverted from a high level to a low level. Then the transistor Mn5 is turned off, and the equivalent impedance from the node a to the ground becomes the sum of the impedance of the resistor R1 and the impedance of the transistor Mn1, so that the node a is pulled up to the power supply voltage VCC again by the transistor Mp2, i.e., the first signal VA is pulled up to the power supply voltage VCC quickly, as shown by the curve 2 in fig. 4.
Fig. 5 shows graphs of the change in quiescent current for a schmitt trigger circuit of an embodiment of the present invention and a schmitt trigger circuit of the prior art, respectively. In fig. 5, the horizontal axis represents the input signal Vin, and the vertical axis represents the quiescent current I of the schmitt trigger circuitCC，VILIndicating the negative threshold voltage, V, of the Schmitt trigger circuitIHTo express SchmidtThe positive threshold voltage of the trigger circuit, curve 3 represents the quiescent current variation curve of the schmitt trigger circuit of the prior art, and curve 4 represents the quiescent current variation curve of the schmitt trigger circuit of the embodiment of the present invention. As described above, the hysteresis voltage of the schmitt trigger circuit 200 according to the embodiment of the present invention is:
VIH-VIL＝I1×R1
since the first signal VA is at the positive threshold voltage V at the input signal VinIHAnd a negative threshold voltage VILIs large, e.g. when the input signal Vin is slightly larger than the forward threshold voltage VIHWhen the first signal VA is pulled down to ground; when the input signal Vin is slightly less than the negative threshold voltage VILIn the embodiment of the invention, the low-resistance current path from the power supply voltage VCC to the ground does not exist in the Schmitt trigger circuit, and the quiescent current I during operationCCMuch smaller than the schmitt trigger circuit of the prior art, as shown in fig. 5.
In summary, the schmitt trigger circuit according to the embodiment of the present invention includes a comparison circuit, an inverter circuit, a buffer and a feedback circuit, the comparison circuit is configured to compare an input signal with a threshold voltage to generate a first signal, the inverter circuit is configured to generate a second signal according to the first signal, the buffer is configured to shape the second signal to obtain an output signal, and the feedback circuit is configured to adjust the first signal according to an output signal, wherein the feedback circuit pulls the first signal down to ground when the input signal is greater than a positive threshold voltage, and pulls the first signal up to a power supply voltage when the input signal is less than a negative threshold voltage.
It should be noted that although the device is described herein as being an N-channel or P-channel device, or an N-type or P-type doped region, one of ordinary skill in the art will appreciate that complementary devices may be implemented in accordance with the present invention. It will be understood by those skilled in the art that conductivity type refers to the mechanism by which conduction occurs, for example by conduction through holes or electrons, and thus does not relate to the doping concentration but to the doping type, for example P-type or N-type. It will be understood by those of ordinary skill in the art that the words "during", "when" and "when … …" as used herein in relation to the operation of a circuit are not strict terms referring to actions occurring immediately upon initiation of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reactive action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A schmitt trigger circuit, comprising:
a comparison circuit for comparing an input signal with a threshold voltage to generate a first signal;
an inverter circuit for generating a second signal from the first signal;
a buffer for shaping said second signal to obtain an output signal; and
a feedback circuit for feedback-adjusting the first signal in accordance with the output signal,
the feedback circuit is used for pulling the first signal to the ground when the input signal is larger than a positive threshold voltage, and pulling the first signal to a power supply voltage when the input signal is smaller than a negative threshold voltage.
2. The schmitt trigger circuit of claim 1, further comprising a bias circuit for providing a bias current to the comparison circuit.
3. The schmitt trigger circuit of claim 2, wherein the bias circuit comprises:
a first transistor having a first terminal connected to a power supply voltage, a control terminal connected to a second terminal thereof, and a second terminal;
a current source having a first terminal connected to the second terminal of the first transistor and a second terminal connected to ground,
wherein the bias current flows through the first transistor.
4. The Schmitt trigger circuit of claim 3, wherein the comparison circuit comprises:
a second transistor having a first terminal connected to the power supply voltage, a control terminal connected to the control terminal of the first transistor, and a second terminal;
a third transistor having a first terminal connected to the second terminal of the second transistor, a control terminal for receiving the input signal, and a second terminal connected to the feedback circuit,
wherein a first node between the second transistor and the third transistor is to provide the first signal.
5. The Schmitt trigger circuit of claim 4, wherein the feedback circuit comprises:
a resistor having a first terminal connected to the second terminal of the third transistor and a second terminal connected to ground;
a fourth transistor having a first terminal connected to the second terminal of the third transistor, a control terminal for receiving the output signal, and a second terminal connected to ground.
6. The Schmitt trigger circuit of claim 4, wherein the inverter circuit comprises:
fifth to eighth transistors connected in series in sequence between the power supply voltage and ground, control terminals of the fifth to eighth transistors being connected to the first node, a second node between the sixth transistor and the seventh transistor being configured to provide the second signal;
a ninth transistor having a first terminal connected to an intermediate node of the fifth transistor and the sixth transistor, a control terminal connected to the second node, and a second terminal connected to ground;
a tenth transistor having a first terminal connected to the power supply voltage, a control terminal connected to the second node, and a second terminal connected to an intermediate node of the seventh transistor and the eighth transistor.
7. A Schmitt trigger circuit as recited in claim 6, wherein the buffer has an input coupled to the second node for receiving the second signal and an output for providing the output signal.
8. The Schmitt trigger circuit of claim 5, wherein the first transistor and the second transistor are P-type MOSFETs and the third transistor and the fourth transistor are N-type MOSFETs.
9. The Schmitt trigger circuit of claim 6, wherein the fifth transistor, the sixth transistor and the ninth transistor are P-type MOSFETs, and the seventh transistor, the eighth transistor and the tenth transistor are N-type MOSFETs.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911392816.2A CN113131905B (en) | 2019-12-30 | 2019-12-30 | Schmitt trigger circuit |
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| CN201911392816.2A CN113131905B (en) | 2019-12-30 | 2019-12-30 | Schmitt trigger circuit |
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Cited By (1)
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| CN117856767A (en) * | 2024-03-07 | 2024-04-09 | 北京中科银河芯科技有限公司 | Schmitt trigger |
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