CN113130454A - Chip packaging device, electronic module and electronic equipment - Google Patents
Chip packaging device, electronic module and electronic equipment Download PDFInfo
- Publication number
- CN113130454A CN113130454A CN202110389166.7A CN202110389166A CN113130454A CN 113130454 A CN113130454 A CN 113130454A CN 202110389166 A CN202110389166 A CN 202110389166A CN 113130454 A CN113130454 A CN 113130454A
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- chip
- packaging
- plate
- package
- board
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 76
- 239000004033 plastic Substances 0.000 claims abstract description 21
- 238000004891 communication Methods 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 239000003292 glue Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 2
- 230000010354 integration Effects 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- -1 gold tin copper aluminum Chemical compound 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention belongs to the technical field of semiconductor packaging, and discloses a chip packaging device, an electronic module and electronic equipment, wherein the chip packaging device comprises a packaging assembly, a first device and a second device, the packaging assembly comprises a packaging plate, a plastic packaging body and a chip, the chip is packaged on the packaging plate by the plastic packaging body, the first device is positioned on the same side of the chip and is in communication connection with the chip, the first device is packaged on the packaging plate by the plastic packaging body, the second device is fixed on one side of the packaging plate, which is far away from the chip, and is in communication connection with the chip; the electronic module comprises the chip packaging device, the third device is located outside the packaging plate, one end of the second lead is in communication connection with the chip through the packaging plate, and the other end of the second lead is in communication connection with the third device. One side of the packaging plate packages the first device and the chip in an SIP mode, and the other side of the packaging plate is provided with the second device, so that a PCB is omitted, and the miniaturization and high integration of chip packaging are realized.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging device, an electronic module and electronic equipment.
Background
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips through a scribing process, then the cut chips are pasted on a corresponding island of a substrate (or a lead frame) through glue, and then a bonding pad of the chip is connected to a corresponding pin of the substrate through a superfine metal (gold tin copper aluminum) wire or conductive resin to form a required circuit; the individual chips are then encapsulated and protected by a plastic housing.
With the increasing demand for miniaturization and integration of chip packages, In the prior art, SIP (System In a Package) integrates multiple functional wafers, including functional wafers such as processors and memories, into one Package according to factors such as application scenarios and the number of layers of Package substrates, so that a packaging scheme for realizing a basic complete function gradually becomes a new choice, but still cannot meet the demand for miniaturization and high integration of chip packages.
In view of the above situation, it is desirable to design a chip package apparatus, an electronic module and an electronic device to solve the above problems.
Disclosure of Invention
One object of the present invention is: a second device is fixed to a side of a package Board away from a chip, so that a Printed Circuit Board (PCB) can be omitted, and miniaturization and high integration of a chip package can be realized.
Another object of the invention is: the third device is directly connected to the packaging plate through the second lead, and high integration of the electronic module is further achieved.
Another object of the invention is: an electronic device is provided, which comprises the electronic module.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a chip packaging apparatus is disclosed, including:
the packaging assembly comprises a packaging plate, a plastic packaging body and a chip, wherein the chip is packaged on the packaging plate by the plastic packaging body;
the first device is positioned on the same side of the chip, the first device is in communication connection with the chip, and the plastic package body packages the first device on the package plate;
and the second device is fixed on one side of the packaging plate, which is far away from the chip, and is in communication connection with the chip.
As a preferable scheme, the package assembly further comprises solder mask layers, and the solder mask layers are attached to two sides of the package plate.
As a preferable scheme, a window is formed in the solder resist layer, and the chip, the first device, and the second device are fixed in the window.
Preferably, the first device is configured as a passive device.
Preferably, the second component is configured as a passive component and/or as an active component.
Preferably, the second device is fixed on the package plate by a snap, an adhesive glue or a screw.
As a preferable scheme, a first via hole is formed in the package board, a conductive medium is plated on a side wall of the first via hole, and the second device is in communication connection with the chip through the conductive medium.
As a preferred scheme, a second via hole is formed in the package board, a first conducting wire penetrates through the second via hole, one end of the first conducting wire is in communication connection with the chip, and the other end of the first conducting wire is in communication connection with the second device.
On the other hand, the electronic module comprises a third device, a second lead and the chip packaging device, wherein the third device is located outside the packaging plate, one end of the second lead is in communication connection with the chip through the packaging plate, and the other end of the second lead is in communication connection with the third device.
On the other hand, the electronic equipment comprises the electronic module.
The invention has the beneficial effects that: the chip packaging device comprises a plastic packaging body, a first device, a second device, a first connecting piece, a second connecting piece and a chip packaging board, wherein the plastic packaging body of the chip packaging device is used for packaging the first device and the chip on one side of the packaging board; the electronic module comprises the chip packaging device, wherein the third device is located outside the packaging plate, and the second lead connects the third device to the packaging plate of the chip packaging device, so that high integration of the electronic module is further realized.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
Fig. 1 is an exploded view of a chip packaging apparatus according to an embodiment;
FIG. 2 is a schematic diagram of a second device side of the chip packaging apparatus;
fig. 3 is a schematic structural diagram of a first device side of the chip packaging apparatus (with the plastic package body removed);
fig. 4 is a schematic structural diagram of an electronic module according to an embodiment.
In fig. 1 to 4:
100. a chip packaging device;
1. a package assembly; 11. a package board; 12. molding the body; 13. a chip; 14. a solder resist layer; 141. a window;
2. a first device;
3. a second device;
200. a third device;
300. a second conductive line.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless expressly stated or limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
As shown in fig. 1 to fig. 3, the present embodiment provides a chip packaging apparatus 100, which includes a packaging assembly 1, a first device 2, and a second device 3, wherein the packaging assembly 1 includes a packaging plate 11, a plastic package body 12, and a chip 13, and the plastic package body 12 packages the chip 13 on the packaging plate 11; the first device 2 is positioned on the same side of the chip 13, the first device 2 is in communication connection with the chip 13, and the plastic package body 12 packages the first device 2 on the package plate 11; the second device 3 is fixed on the side of the package plate 11 away from the chip 13, and the second device 3 is in communication connection with the chip 13. The plastic package body 12 may be configured as an epoxy molding compound, a silicon rubber, or a polyimide, the plastic package body 12 in this embodiment is an epoxy molding compound, the package plate 11 may be configured as a package substrate or a package frame, the package plate 11 in this embodiment is a package substrate, the first device 2 and the chip 13 are both packaged by the plastic package body 12 on one side of the package substrate, and the second device 3 is fixed on the other side of the package substrate (i.e., one side of the package substrate away from the first device 2 and the chip 13). It can be understood that the plastic package body 12 encapsulates the first device 2 and the chip 13 on one side of the package substrate in an SIP manner, the second device 3 is fixed on the other side of the package substrate, and the first device 2 and the second device 3 are in communication connection with the chip 13, so that a PCB structure is omitted, and further the miniaturization and integration degree of the chip package apparatus 100 is improved.
In the present embodiment, the first device 2 is configured as a passive device, and exemplarily, the first device 2 is configured as a resistor, a capacitor, an inductor, or a converter; the second device 3 is configured as a passive device and/or an active device, for example, the second device 3 is configured as a diode, a triode, or an arithmetic unit, the second device 3 in this embodiment is a device with a large heat productivity, and the device with the large heat productivity is fixed outside the plastic package body 12 and is far away from the chip 13, so that the influence of the second device 3 on the operation of the chip 13 is avoided, and meanwhile, the heat dissipation of the second device 3 is facilitated.
As a preferred embodiment, the package assembly 1 further includes solder resists 14, the solder resists 14 are attached to both sides of the package board 11, and when the chip 13, the first device 2, or the second device 3 are connected by solder communication, the solder resists 14 can prevent the tin water from splashing to other positions of the package board 11. Specifically, the window 141 is formed in the solder mask layer 14, the chip 13, the first device 2 and the second device 3 are fixed in the window 141 of the solder mask layer 14, the window opening process of the solder mask layer 14 is a conventional means in the field, detailed description is omitted for a specific working principle, the second device 3 of the embodiment is fixed on the window 141 of the solder mask layer 14 through a buckle, adhesive glue or a screw, the structure is simple, and tin water can be prevented from splashing to other positions of the package board 11 during soldering, and reliability is improved.
In this embodiment, the package board 11 is provided with a first via hole, a conductive medium is plated on a sidewall of the first via hole, and the second device 3 is in communication connection with the chip 13 through the conductive medium. The conductive medium may be copper or other metal, and the conductive medium penetrates through the first via hole to communicatively connect the second device 3 and the chip 13 on both sides of the package board 11, which is compact.
In other embodiments of the present invention, the package board 11 is provided with a second via hole, the second via hole is provided with a first conductive wire, one end of the first conductive wire is communicatively connected to the chip 13, and the other end of the first conductive wire is communicatively connected to the second device 3. It can be understood that the first conductive line penetrates the second via hole to communicatively connect the second device 3 and the chip 13 on both sides of the package board 11, and the process is simple.
As shown in fig. 4, the present embodiment further provides an electronic module, which includes a third device 200, a second conductive trace 300 and the chip packaging apparatus 100, where the third device 200 is located outside the packaging board 11, one end of the second conductive trace 300 is communicatively connected to the chip 13 through the packaging board 11, and the other end is communicatively connected to the third device 200. Specifically, the area of any surface of the third device 200 is larger than the surface area 1/2 of the package board 11, for example, the third device 200 may be configured as a switch or a connector, and the third device 200 is directly connected to the package board 11 through the second wire 300, and then is in communication connection with the chip 13 through the package board 11, so that the integration degree of the electronic module is further improved.
The embodiment also provides electronic equipment, including foretell electronic module, electronic module's the degree of integrating is high, and then has realized electronic equipment's miniaturization.
In the description herein, it is to be understood that the terms "upper," "lower," "left," "right," and the like are based on the orientation or positional relationship shown in the drawings for convenience in description and simplicity of operation, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
In addition, the foregoing is only the preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A chip packaging apparatus, comprising:
the packaging assembly (1) comprises a packaging plate (11), a plastic package body (12) and a chip (13), wherein the chip (13) is packaged on the packaging plate (11) through the plastic package body (12);
the first device (2), the first device (2) is located on the same side of the chip (13), the first device (2) is in communication connection with the chip (13), and the plastic package body (12) packages the first device (2) on the package board (11);
the second device (3), the second device (3) is fixed on one side of the packaging plate (11) far away from the chip (13), and the second device (3) is in communication connection with the chip (13).
2. The chip packaging arrangement according to claim 1, characterized in that the package assembly (1) further comprises a solder resist layer (14), the solder resist layer (14) being applied on both sides of the package board (11).
3. The chip packaging arrangement according to claim 2, characterized in that a window (141) is opened in the solder resist layer (14), and the chip (13), the first device (2) and the second device (3) are fixed in the window (141).
4. Chip packaging arrangement according to claim 3, characterized in that said second component (3) is fixed to said packaging plate (11) by means of snaps, adhesive glue or screws.
5. Chip packaging arrangement according to any one of claims 1-4, characterized in that the first device (2) is provided as a passive device.
6. Chip packaging arrangement according to any one of claims 1-4, characterized in that the second device (3) is provided as a passive device and/or as an active device.
7. The chip packaging apparatus according to claim 1, wherein the packaging board (11) has a first via hole formed therein, a sidewall of the first via hole is plated with a conductive medium, and the second device (3) is communicatively connected to the chip (13) through the conductive medium.
8. The chip packaging apparatus according to claim 1, wherein a second via hole is opened in the packaging board (11), a first conductive wire is disposed through the second via hole, one end of the first conductive wire is communicatively connected to the chip (13), and the other end of the first conductive wire is communicatively connected to the second device (3).
9. An electronic module, characterized in that it comprises a third device (200), a second conductor (300) and a chip packaging arrangement (100) according to any one of claims 1 to 8, the third device (200) being located outside the packaging board (11), one end of the second conductor (300) being communicatively connected to the chip (13) via the packaging board (11) and the other end being communicatively connected to the third device (200).
10. An electronic device, characterized in that it comprises an electronic module according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110389166.7A CN113130454B (en) | 2021-04-12 | 2021-04-12 | Chip packaging device, electronic module and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110389166.7A CN113130454B (en) | 2021-04-12 | 2021-04-12 | Chip packaging device, electronic module and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113130454A true CN113130454A (en) | 2021-07-16 |
| CN113130454B CN113130454B (en) | 2024-07-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110389166.7A Active CN113130454B (en) | 2021-04-12 | 2021-04-12 | Chip packaging device, electronic module and electronic equipment |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102576702A (en) * | 2009-12-10 | 2012-07-11 | 国家半导体公司 | Module package with embedded substrate and leadframe |
| CN105374784A (en) * | 2014-08-19 | 2016-03-02 | 英特尔公司 | Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication |
| CN105552065A (en) * | 2016-02-01 | 2016-05-04 | 中国电子科技集团公司第三十八研究所 | System-level package structure of T/R assembly control module and package method of system-level package structure |
| CN110767615A (en) * | 2019-10-14 | 2020-02-07 | 华天科技（西安）有限公司 | SSD storage chip packaging structure and manufacturing method |
| CN211879369U (en) * | 2020-05-25 | 2020-11-06 | 深圳市中兴微电子技术有限公司 | Chip packaging structure and electronic equipment |
| CN112018101A (en) * | 2019-05-28 | 2020-12-01 | 联发科技股份有限公司 | Semiconductor package |
-
2021
- 2021-04-12 CN CN202110389166.7A patent/CN113130454B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102576702A (en) * | 2009-12-10 | 2012-07-11 | 国家半导体公司 | Module package with embedded substrate and leadframe |
| CN105374784A (en) * | 2014-08-19 | 2016-03-02 | 英特尔公司 | Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication |
| CN105552065A (en) * | 2016-02-01 | 2016-05-04 | 中国电子科技集团公司第三十八研究所 | System-level package structure of T/R assembly control module and package method of system-level package structure |
| CN112018101A (en) * | 2019-05-28 | 2020-12-01 | 联发科技股份有限公司 | Semiconductor package |
| CN110767615A (en) * | 2019-10-14 | 2020-02-07 | 华天科技（西安）有限公司 | SSD storage chip packaging structure and manufacturing method |
| CN211879369U (en) * | 2020-05-25 | 2020-11-06 | 深圳市中兴微电子技术有限公司 | Chip packaging structure and electronic equipment |
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| CN113130454B (en) | 2024-07-05 |
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