CN113130380A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113130380A CN113130380A CN201911393123.5A CN201911393123A CN113130380A CN 113130380 A CN113130380 A CN 113130380A CN 201911393123 A CN201911393123 A CN 201911393123A CN 113130380 A CN113130380 A CN 113130380A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention provides a semiconductor structure and a forming method thereof, wherein the forming method comprises the following steps: after the second dielectric layer is patterned, a shielding layer is formed on the surface of the second conductive layer; after the shielding layer is formed, etching the first dielectric layer at the bottom of the second contact hole until the first conductive layer is exposed, and forming a third contact hole in the second dielectric layer; forming a first plug in the third contact hole by taking the shielding layer as a mask; after the first plug is formed, removing the shielding layer; and after removing the shielding layer, forming a second plug in the second contact hole and forming a third plug in the first contact hole. The method can form the second plug and the third plug with high quality, and improves the conductivity of the second plug and the third plug.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor chips are developed to a higher integration level in order to achieve faster operation speed, larger data storage capacity, and more functions. The structure of the semiconductor chip becomes more and more complex, and the connection relationship of the interconnection structure becomes more complex.
In a metal interconnection structure, different metal layers of the same layer are often connected with metal layers of different depths, which increases the difficulty of the semiconductor structure forming process.
The electrical performance of the metal interconnection structure formed by the prior art is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a working method thereof, which can improve the electrical property of a metal interconnection structure.
The technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate comprising: a first conductive layer; a first dielectric layer covering the first conductive layer; the second conducting layer is positioned in the first dielectric layer, and the top surface of the second conducting layer is exposed out of the first dielectric layer; the second dielectric layer is positioned on the second conductive layer and the first dielectric layer; patterning the second dielectric layer, forming a first contact hole and a second contact hole in the second dielectric layer, and exposing the second conductive layer at the bottom of the first contact hole; after the second dielectric layer is patterned, forming a shielding layer on the surface of the second conductive layer, wherein the shielding layer is made of a dielectric material; after the shielding layer is formed, etching the first dielectric layer at the bottom of the second contact hole until the first conductive layer is exposed, and forming a third contact hole in the first dielectric layer; forming a first plug in the third contact hole; after the first plug is formed, removing the shielding layer; and after removing the shielding layer, forming a second plug in the second contact hole and forming a third plug in the first contact hole.
Optionally, the step of forming the shielding layer on the surface of the second conductive layer includes: and carrying out first dielectric treatment on partial material on the surface of the second conductive layer to form the shielding layer.
Optionally, the first dielectric treatment process includes an oxidation process, an ashing process, or a nitridation process.
Optionally, after removing the shielding layer, forming a first groove in the second conductive layer; the third plug is also located in the first recess.
Optionally, the step of forming a shielding layer on the surface of the second conductive layer includes: depositing a metal layer on the surface of the second conductive layer by taking the second conductive layer as a seed layer; and carrying out second dielectric treatment on the metal layer to form the shielding layer.
Optionally, the metal layer is a transition metal of a first transition system or a second transition system.
Optionally, the step of depositing a metal layer on the surface of the second conductive layer includes: introducing precursor molecules to the surface of the second conductive layer, wherein the precursor molecules comprise transition metal centers of a second transition system and a third transition system which are complexed with three heteroleptic ligands; and thermally dissolving the ligand of the precursor to form the metal layer.
Optionally, the process of forming the metal layer includes an atomic layer deposition process or a chemical vapor deposition process.
Optionally, after removing the shielding layer and before forming the second plug, the method further includes: etching the second conducting layer to form a second groove in the second conducting layer; the second plug is also located in the second recess.
Optionally, the shielding layer is made of zirconium oxide, hafnium nitride, tungsten oxide, aluminum oxide, ruthenium oxide, or titanium oxide.
Optionally, the thickness of the shielding layer is 5 to 10 angstroms.
Optionally, the second conductive layer is made of ruthenium, tungsten, or copper.
Optionally, the process of removing the shielding layer includes a wet etching process.
Optionally, the etching gas for removing the shielding layer includes chlorine, oxygen, and argon.
Optionally, the process of forming the first plug in the third contact hole includes: a bottom-up metal growth process; the process of forming the third and second plugs includes: a bottom-up metal growth process.
Optionally, the first dielectric layer is made of silicon oxide, silicon nitride or silicon oxynitride; the shielding layer is made of metal oxide or metal nitride.
Optionally, the first plug is flush with a surface of the second conductive layer.
Optionally, the method further includes: and carrying out planarization treatment on the second plug and the third plug.
The technical scheme of the invention also provides a semiconductor structure formed according to the method
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the technical scheme of the invention, before the first plug is formed, a shielding layer is formed on the surface of the second conductive layer. In the process of forming the first plug, the shielding layer can isolate the second conductive layer, so that a first plug material is prevented from being formed on the surface of the second conductive layer, and further the height difference between the surface of the first plug and the surface of the second conductive layer can be reduced, so that the influence of the height difference between the first plug and the second conductive layer on the process of forming the third plug and the second plug can be reduced, the high-quality second plug and the high-quality third plug can be formed, the conductive performance of the second plug and the third plug can be improved, for example, the hollow holes in the second plug and the third plug can be reduced, and the capacitance and the resistance can be reduced.
Further, after the shielding layer is removed, a first groove is formed in the second conductive layer, and the third plug is also formed in the first groove, so that the second conductive layer can be in contact with the third plug through the side wall and the bottom surface of the first groove, thereby increasing the contact area and reducing the contact resistance.
Drawings
FIGS. 1-6 are schematic structural diagrams illustrating steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 7 to 8 are schematic structural diagrams of steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
There are a number of problems with semiconductor formation methods, such as: when the heights of different plugs in the metal interconnection structure are different, the electrical performance of the formed interconnection structure is poor.
The technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the following steps: after the second dielectric layer is patterned, a shielding layer is formed on the surface of the second conductive layer; after the shielding layer is formed, etching the first dielectric layer at the bottom of the second contact hole until the first conductive layer is exposed, and forming a third contact hole in the second dielectric layer; forming a first plug in the third contact hole by taking the shielding layer as a mask; after the first plug is formed, removing the shielding layer; and after removing the shielding layer, forming a second plug in the second contact hole and forming a third plug in the first contact hole. The method can form the second plug and the third plug with high quality, and improves the conductivity of the second plug and the third plug.
Fig. 1 to 6 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 1, a substrate is provided, the substrate includes a first conductive layer 101; a first dielectric layer 110 overlying the first conductive layer 101; the second conducting layer 111 is positioned in the first dielectric layer, and the top surface of the second conducting layer 111 is exposed out of the first dielectric layer 110; and a second dielectric layer 120 located on the second conductive layer 111 and the first dielectric layer 110.
The substrate further comprises a substrate and a third dielectric layer 100 positioned on the substrate, the first conductive layer 101 is positioned in the third dielectric layer 100, and the top surface of the first conductive layer 101 is exposed out of the third dielectric layer 100.
The first dielectric layer 110 is located on the third dielectric layer 100, and the second dielectric layer 120 is located on the first dielectric layer 110.
The substrate is a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-on-semiconductor or a germanium-on-semiconductor.
The first dielectric layer 110 is made of silicon oxide, silicon nitride or silicon oxynitride; the second dielectric layer 120 is made of silicon oxide, silicon nitride or silicon oxynitride; the third dielectric layer 100 is made of silicon oxide, silicon nitride or silicon oxynitride.
In this embodiment, the first conductive layer 101 and the second conductive layer 111 are made of the same material. In other embodiments, the materials of the first conductive layer 101 and the second conductive layer 111 may not be the same.
In this embodiment, the material of the first conductive layer 101 is a metal, such as ruthenium. In other embodiments, the material of the first conductive layer is copper or tungsten.
In this embodiment, the material of the second conductive layer 111 is a metal, such as ruthenium. In other embodiments, the material of the first conductive layer is copper or tungsten.
In this embodiment, the substrate further includes: a first mask layer 112 located between the first dielectric layer 110 and the second dielectric layer 120, wherein the first mask layer 112 has a first opening and a second opening; the first opening is aligned with the first conductive layer 101 and the second opening exposes the second conductive layer 111.
The material of the first mask layer 112 is different from the materials of the first dielectric layer 110 and the second dielectric layer 120.
Specifically, in this embodiment, the material of the first mask layer 112 is silicon nitride or silicon oxynitride.
The substrate further comprises a capping layer 121 on the second dielectric layer 120; a second initial mask layer 124 on the capping layer 121.
The cover layer 121 is used to cover a conductive layer (not shown) in the second dielectric layer 120. In other embodiments, the substrate may not have the cover layer.
The material of the covering layer 121 is silicon nitride, silicon oxide or silicon oxynitride.
Specifically, the second initial mask layer 124 has a third opening and a fourth opening therein, and the third opening is aligned with the first conductive layer 101; the fourth opening is aligned with the second conductive layer 111.
The material of the second initial masking layer 124 is different from the material of the second dielectric layer 120.
The second initial mask layer 124 is made of silicon nitride or silicon oxynitride.
With reference to fig. 1, the second dielectric layer 120 is patterned, a first contact hole 140 and a second contact hole 130 are formed in the second dielectric layer 120, and the bottom of the first contact hole 140 exposes the second conductive layer 111.
The first contact hole 140 is used for subsequently accommodating a third plug 142, so as to electrically connect the second conductive layer 111 with an external circuit; the second contact hole 130 is used to subsequently receive a second plug 132.
In this embodiment, the second dielectric layer 120 further has the second initial mask layer 124 thereon, and the patterning step includes: forming a patterned first photoresist layer 123 on the second dielectric layer 120; and etching the second dielectric layer 120 by using the first photoresist layer 123 and the second initial mask layer 124 as masks to form the first contact hole 140 and the second contact hole 130. In other embodiments, the second dielectric layer is not provided with the second initial mask layer, and the second dielectric layer is etched by using the first photoresist layer as a mask.
The process for etching the second dielectric layer 120 includes anisotropic dry etching.
Referring to fig. 2, a shielding layer 141 is formed on the surface of the second conductive layer 111, and the shielding layer 141 is made of a dielectric material.
The shielding layer 141 is used for isolating the second conductive layer 111 in a subsequent process of forming the first plug, so as to avoid forming a material of the first plug 131 on the surface of the second conductive layer 111, and further reduce a height difference between the surface of the first plug 131 and the surface of the second conductive layer 111, so as to reduce an influence of the height difference between the first plug 131 and the second conductive layer 111 on a process of forming the third plug 142 and the second plug 132, and to form the second plug 132 and the third plug 142 with high quality, and to improve conductivity of the second plug 132 and the third plug 142, for example, to reduce voids in the second plug 132 and the third plug, so as to reduce capacitance and resistance.
In this embodiment, the step of forming the shielding layer 141 includes: and performing first dielectric treatment on a partial material on the surface of the second conductive layer to form the shielding layer 141.
The first dielectric treatment is used to form a dielectric material by partially dielectric the surface of the second conductive layer 111.
In this embodiment, the step of forming the shielding layer 141 includes: the surface material of the second conductive layer 111 is subjected to a first dielectric treatment to form a shielding layer 141, and then the shielding layer 141 is located in the second conductive layer 111.
Specifically, in this embodiment, the first dielectric treatment process includes: an oxidation process, a nitridation process, or an ashing process. Correspondingly, when the second conductive layer 111 is made of ruthenium, the shielding layer 141 is made of ruthenium oxide; when the second conductive layer 111 is made of copper, the shielding layer 141 is made of copper oxide; when the second conductive layer 111 is made of tungsten, the shielding layer 141 is made of tungsten oxide.
If the thickness of the shielding layer 141 is too large, the thickness of the second conductive layer 111 is easily reduced, which affects the electrical performance of the second conductive layer 111; if the thickness of the shielding layer 141 is too small, it is not easy to sufficiently isolate the second conductive layer 111, and it is easy to form the first plug 131 material on the surface of the second conductive layer 111 subsequently. Specifically, the thickness of the shielding layer 141 is 5 to 10 angstroms.
In this embodiment, the first dielectric layer is treated by an oxidation process, and correspondingly, the shielding layer 141 is made of a metal oxide.
In this embodiment, the oxidation process includes an atomic oxidation process. Specifically, the oxidizing gas of the oxidation process is atomic oxygen; the oxidation temperature is 500K-600K.
In other embodiments, the first dielectric treatment process is a nitridation process, and the material of the shielding layer is a metal nitride. For example: when the second conductive layer is made of ruthenium, the shielding layer is made of ruthenium nitride; when the second conducting layer is made of copper, the shielding layer is made of copper nitride; when the second conductive layer is made of tungsten, the shielding layer is made of tungsten nitride.
Referring to fig. 3, after the shielding layer 141 is formed, the first dielectric layer 110 at the bottom of the second contact hole 130 is etched until the first conductive layer 101 is exposed, and a third contact hole 150 is formed in the first dielectric layer 110.
The third contact hole 150 is used for receiving the first plug 131 to electrically connect the first conductive layer 101 with an external circuit.
After the forming of the shielding layer 141, forming a first connection groove 151 and a second connection groove 152 in the second dielectric layer 120, wherein the first connection groove 151 is communicated with the first contact hole 140, and the second connection groove 152 is communicated with the second contact hole 130.
In this embodiment, before etching the first dielectric layer 110 at the bottom of the second contact hole 130 to expose the first conductive layer 101, the method further includes: forming a patterned second photoresist layer on the second initial mask layer 124 (as shown in fig. 2), where the second photoresist layer exposes the third opening, the fourth opening, a portion of the second initial mask layer 124 around the third opening, and a portion of the second initial mask layer 124 around the fourth opening; and etching the second initial mask layer 124 by using the second photoresist layer as a mask to form a second mask layer 122.
The step of forming the third contact hole 150, the first connection groove 151, and the second connection groove 152 includes: and etching the first dielectric layer 110 and the second dielectric layer 120 by using the second mask layer 122 as a mask until the first conductive layer 101 is exposed, forming a third contact hole 150 in the first dielectric layer 110 at the bottom of the second contact hole 130, and forming a first connecting groove 151 and a second connecting groove 152 in the second dielectric layer 120.
It should be noted that, in other embodiments, the first connection groove and the second connection groove may not be formed. The step of forming the third contact hole includes: and etching the first dielectric layer at the bottom of the second contact hole by taking the second initial mask layer 124 as a mask until the first conductive layer is exposed, thereby forming a third contact hole.
In this embodiment, the process of etching the first dielectric layer 110 and the second dielectric layer 120 includes an anisotropic dry etching process.
Referring to fig. 4, a first plug 131 is formed in the third contact hole 150.
The first plug 131 is used to electrically connect the first conductive layer 101 with a subsequent second plug.
The step of forming the first plug 131 includes: a first plug 131 is formed in the third contact hole 150 using the first conductive layer 101 as a seed layer.
The process of forming the first plug 131 includes a bottom-up metal growth process. The metal growth process from bottom to top can form the first plug material on the metal surface without forming the metal material on the dielectric material surface. Therefore, the first plug material is not formed on the shielding layer 141.
In this embodiment, the material of the first plug 131 is tungsten, copper or ruthenium.
In this embodiment, the first plug 131 is flush with the surface of the second conductive layer 111. In other embodiments, the first plug surface is higher or lower than the second conductive layer surface.
Referring to fig. 5, after the first plug 131 is formed, the shielding layer 141 is removed (as shown in fig. 4).
In this embodiment, the process of removing the shielding layer 141 includes a wet etching process. Specifically, the etching gas for removing the shielding layer comprises chlorine, oxygen and argon.
In other embodiments, the process of removing the masking layer comprises a dry etching process.
It should be noted that, in this embodiment, the shielding layer 141 is located in the second conductive layer 111, and after the shielding layer 141 is removed, the first groove 160 is formed in the second conductive layer 111.
The first groove 160 is subsequently used for accommodating a third plug, and the second conductive layer 111 can contact with the third plug through the side wall and the bottom surface of the first groove 160, so that the contact area between the second conductive layer 111 and the third plug can be increased, and the contact resistance can be further reduced.
Referring to fig. 6, after removing the shielding layer 141, a second plug 132 is formed in the second contact hole 130, and a third plug 142 is formed in the first contact hole 140.
The second plug 132 is used for electrically connecting the first plug 131 with an external circuit; the third plug 142 is used to electrically connect the second conductive layer 111 to an external circuit.
The process of forming the second and third plugs 132 and 142 includes a bottom-up metal growth process.
The second plug 132 and the third plug 142 are made of the same material. And the second plug 132 is the same material as the first plug 131.
The material of the second plug 132 and the third plug 142 is tungsten, ruthenium or copper.
In this embodiment, the second conductive layer 111 has a first groove 160 therein, and the step of forming the third plug 142 further includes: a third plug 142 is formed in the first groove 160.
In this embodiment, the second plug 132 is further located in the second connecting groove to form a second connecting layer; the third plugs 142 are also located in the first connection grooves 151, forming a first connection layer.
In this embodiment, specifically, after forming the third plug in the first contact hole and forming the second plug in the second contact hole, the step of forming the second plug 132 and the third plug 142 further includes: forming a first connection layer in the first connection groove 151 (shown in fig. 5); a second connection layer is formed in the second connection groove 152 (shown in fig. 5). In other embodiments, the step of forming the first connection layer and the second connection layer may not be included.
The first and second connection layers and the second and third plugs 132 and 142 are formed through the same process.
After forming the second and third plugs 132 and 142, the forming method further includes: the second plug 132 and the third plug 142 are planarized.
The planarization process is used to remove the second plug 132 material and the third plug material on the second dielectric layer.
Specifically, in this embodiment, the first connection layer and the second connection layer are subjected to planarization processing.
The planarization treatment process comprises a chemical mechanical polishing process.
Fig. 7 and 8 are schematic structural views of steps in another embodiment of a method for forming a semiconductor structure of the present invention.
The same parts of this embodiment as the previous embodiment are not described herein again, but the differences include:
referring to fig. 7, a shielding layer 241 is formed on the surface of the second conductive layer 111.
In this embodiment, the process of forming the shielding layer 241 includes: and depositing a shielding layer 241 on the surface of the second conductive layer 111.
In this embodiment, the shielding layer 241 is located on the second conductive layer 111.
The step of depositing a shielding layer 241 on the surface of the second conductive layer 111 includes: depositing a metal layer on the surface of the second conductive layer 111 by taking the second conductive layer 111 as a seed layer; and performing second dielectric treatment on the metal layer to form the shielding layer 241.
In this embodiment, the metal layer is made of a second transition metal and a third transition metal, and specifically, the metal layer is made of Zr, Hf, tungsten, or ruthenium. In other embodiments, the metal layer may also be Ti or aluminum.
The step of forming the metal layer includes: introducing precursor molecules to the surface of the second conductive layer 111, wherein the precursor molecules comprise transition metal centers of a second transition system and a third transition system which are complexed with three heteroleptic ligands; and thermally dissolving the ligand of the precursor to form the metal layer.
The process of forming the metal layer includes an atomic deposition process or a chemical vapor deposition process.
In this embodiment, the metal layer forming method forms the metal layer material only on the metal surface, and the metal layer is not formed on the dielectric material surface. Therefore, in the embodiment, no metal layer is formed at the bottom of the first contact hole.
In this embodiment, the shielding layer 241 is made of: ZrO (ZrO)2HfN, or tungsten oxide. In other embodiments, the material of the shielding layer may be Al2O3Or TiO2。
The temperature for dissolving the hot blood is 50-600 ℃.
The second dielectric treatment process comprises an oxidation process, a nitridation process or an ashing process.
If the thickness of the shielding layer 241 is too large, the subsequent removal of the shielding layer 241 is not facilitated; if the thickness of the shielding layer 241 is too small, it is not easy to sufficiently isolate the second conductive layer 111, and it is easy to form the first plug 131 material on the surface of the second conductive layer 111 subsequently. Specifically, the thickness of the shielding layer 241 is 5 to 10 angstroms.
Referring to fig. 8, after the first plug 131 is formed, the shielding layer 241 is removed.
In this embodiment, after the shielding layer 241 is removed, the second conductive layer 111 does not have a groove. In this embodiment, the third plug 142 material is only located in the first contact hole 140.
In other embodiments, after removing the shielding layer, the method further includes: and etching the second conducting layer to form a second groove in the second conducting layer. The step of forming the third plug further comprises: forming a second plug in the second recess.
Embodiments of the present invention further provide a semiconductor structure formed by the method for forming the semiconductor structure shown in fig. 1 to 6 or fig. 7 to 8.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising: a first conductive layer; a first dielectric layer covering the first conductive layer; the second conducting layer is positioned in the first dielectric layer, and the top surface of the second conducting layer is exposed out of the first dielectric layer; the second dielectric layer is positioned on the second conductive layer and the first dielectric layer;
patterning the second dielectric layer, forming a first contact hole and a second contact hole in the second dielectric layer, and exposing the second conductive layer at the bottom of the first contact hole;
after the second dielectric layer is patterned, forming a shielding layer on the surface of the second conductive layer, wherein the shielding layer is made of a dielectric material;
after the shielding layer is formed, etching the first dielectric layer at the bottom of the second contact hole until the first conductive layer is exposed, and forming a third contact hole in the first dielectric layer;
forming a first plug in the third contact hole;
after the first plug is formed, removing the shielding layer;
and after removing the shielding layer, forming a second plug in the second contact hole and forming a third plug in the first contact hole.
2. The method as claimed in claim 1, wherein the step of forming the shielding layer on the surface of the second conductive layer comprises: and carrying out first dielectric treatment on partial material on the surface of the second conductive layer to form the shielding layer.
3. The method of claim 2, wherein the first dielectric treatment process comprises an oxidation process, an ashing process, or a nitridation process.
4. The method according to claim 2, wherein after removing the masking layer, a first groove is formed in the second conductive layer; the third plug is also located in the first recess.
5. The method as claimed in claim 1, wherein the step of forming a shielding layer on the surface of the second conductive layer comprises: depositing a metal layer on the surface of the second conductive layer by taking the second conductive layer as a seed layer; and carrying out second dielectric treatment on the metal layer to form the shielding layer.
6. The method as claimed in claim 5, wherein the metal layer is a transition metal of a first transition system or a second transition system.
7. The method as claimed in claim 6, wherein the step of depositing the metal layer on the surface of the second conductive layer comprises: introducing precursor molecules to the surface of the second conductive layer, wherein the precursor molecules comprise transition metal centers of a second transition system and a third transition system which are complexed with three heteroleptic ligands; and thermally dissolving the ligand of the precursor to form the metal layer.
8. The method of claim 5, wherein the process of forming the metal layer comprises an atomic layer deposition process or a chemical vapor deposition process.
9. The method as claimed in claim 5, wherein after removing the masking layer and before forming the second plug, further comprising: etching the second conducting layer to form a second groove in the second conducting layer; the second plug is also located in the second recess.
10. The method as claimed in claim 1, wherein the shielding layer is made of zirconium oxide, hafnium nitride, tungsten oxide, aluminum oxide, ruthenium oxide, or titanium oxide.
11. The method of claim 1, wherein the masking layer has a thickness of 5 to 10 angstroms.
12. The method according to claim 1, wherein a material of the second conductive layer is ruthenium, tungsten, or copper.
13. The method of claim 1, wherein the process of removing the masking layer comprises a wet etching process.
14. The method of claim 13, wherein the etching gas to remove the masking layer comprises chlorine, oxygen, and argon.
15. The method as claimed in claim 1, wherein the step of forming the first plug in the third contact hole comprises: a bottom-up metal growth process; the process of forming the third and second plugs includes: a bottom-up metal growth process.
16. The method as claimed in claim 1, wherein the shielding layer is made of metal oxide or metal nitride; the first dielectric layer is made of silicon oxide, silicon nitride or silicon oxynitride.
17. The method of claim 1, wherein the first plug is flush with a surface of the second conductive layer.
18. The method of forming a semiconductor structure of claim 1, further comprising: and carrying out planarization treatment on the second plug and the third plug.
19. A semiconductor structure formed according to the method of any one of claims 1 to 18.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020093097A1 (en) * | 2001-01-17 | 2002-07-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US20040129967A1 (en) * | 2003-01-06 | 2004-07-08 | Si-Youn Kim | Bottom electrode of capacitor of semiconductor device and method of forming the same |
| KR20090052068A (en) * | 2007-11-20 | 2009-05-25 | 주식회사 하이닉스반도체 | Method of forming contact plug in semiconductor device |
| JP2014183116A (en) * | 2013-03-18 | 2014-09-29 | Asahi Kasei Electronics Co Ltd | Semiconductor device manufacturing method and semiconductor device |
| US10157774B1 (en) * | 2017-07-25 | 2018-12-18 | Globalfoundries Inc. | Contact scheme for landing on different contact area levels |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020093097A1 (en) * | 2001-01-17 | 2002-07-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US20040129967A1 (en) * | 2003-01-06 | 2004-07-08 | Si-Youn Kim | Bottom electrode of capacitor of semiconductor device and method of forming the same |
| KR20090052068A (en) * | 2007-11-20 | 2009-05-25 | 주식회사 하이닉스반도체 | Method of forming contact plug in semiconductor device |
| JP2014183116A (en) * | 2013-03-18 | 2014-09-29 | Asahi Kasei Electronics Co Ltd | Semiconductor device manufacturing method and semiconductor device |
| US10157774B1 (en) * | 2017-07-25 | 2018-12-18 | Globalfoundries Inc. | Contact scheme for landing on different contact area levels |
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