CN113128155B - System and method for establishing simulation model of field effect transistor - Google Patents
System and method for establishing simulation model of field effect transistor Download PDFInfo
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Abstract
Disclosed are a system and a method for establishing a simulation model of a field effect transistor, the simulation model of the field effect transistor including: the field effect transistor model comprises four connecting ends of a grid electrode, a source electrode, a drain electrode and a body electrode of the field effect transistor; a first diode model including a first diode connected between a body electrode and a drain electrode of the field effect transistor model; and the first diode model and the second diode model represent the leakage characteristic and the capacitance-voltage characteristic of the field effect transistor through breakdown voltage parameters and temperature parameters. The simulation model of the field effect transistor represents the leakage characteristic and the capacitance-voltage characteristic of the field effect transistor through the breakdown voltage parameter and the temperature parameter, so that the model can better reflect the device characteristic, the problem of convergence is solved, and the simulation accuracy is ensured.
Description
Technical Field
The invention relates to the technical field of device simulation, in particular to a system and a method for establishing a simulation model of a field effect transistor.
Background
Junction Field-Effect transistors (JFETs) are active devices having an amplifying function, are widely used in circuit design, and are also used to manufacture various semiconductor devices. In order to accelerate the manufacturing cycle and avoid resource waste, modeling and simulating are generally carried out on a circuit or a semiconductor device before the circuit or the semiconductor device is put into production, and simulation is carried out on an established device model by adopting an SPICE simulation tool and the like to obtain different fitting curves, so that whether the device can normally work or not and whether each parameter has good characteristics or not can be quickly analyzed.
In the SPICE model of the conventional JFET, a parasitic diode is arranged between a grid electrode and a source electrode, and when the voltage between the grid electrode and the source electrode is larger, the grid current is overlarge, so that the problem of convergence in SPICE simulation is caused, and the parameter characteristics of the model cannot be accurately analyzed. Although the convergence problem is reduced by the series resistance of the grid electrode, the change characteristic of model current/capacitance along with voltage is influenced, and the accuracy of the JFET model is seriously influenced. Therefore, the simulation accuracy of the current JFET model is not high.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a system and a method for building a simulation model of a field effect transistor including a JFET, which can solve the problem of SPICE simulation convergence and ensure the simulation accuracy of model parameter characteristics.
According to a first aspect of the present invention, there is provided a system for creating a simulation model of a field effect transistor, including:
the field effect transistor model comprises four connecting ends of a grid electrode, a source electrode, a drain electrode and a body electrode of the field effect transistor, and the grid current of a diode built in the field effect transistor is zero;
a first diode model comprising a first diode connected between a body electrode and a drain electrode of the field effect transistor model;
a second diode model comprising a second diode connected between a body electrode and a source electrode of the field effect transistor model,
the first diode model and the second diode model characterize leakage characteristics and capacitance-voltage characteristics of the field effect transistor by a breakdown voltage parameter and a temperature parameter.
Optionally, the breakdown voltage parameter is obtained according to breakdown voltages of the first diode and the second diode, respectively, and the temperature parameter is obtained according to leakage currents of the simulation model of the field effect transistor at a plurality of different simulation temperatures.
Optionally, the field effect transistor model characterizes leakage characteristics and capacitance-voltage characteristics of the field effect transistor through a current-voltage parameter, a capacitance-voltage parameter and high and low temperature parameters.
Optionally, in the simulation model of the field effect transistor, the first diode and the second diode are located outside the field effect transistor.
Optionally, the simulation model of the field effect transistor is stored in the form of a sub-circuit.
According to a second aspect of the present invention, there is provided a method for creating a simulation model of a field effect transistor, comprising:
acquiring a current-voltage parameter, a capacitance-voltage parameter and a high-low temperature parameter according to the established test data of the field effect transistor model;
setting gate current parameters corresponding to a built-in diode in the field effect transistor model to zero, wherein the current-voltage parameters comprise the gate current parameters;
constructing a first diode model and a second diode model outside the field effect transistor model to form a combined model;
respectively acquiring breakdown voltage parameters, tunneling current parameters and temperature parameters of the first diode model and the second diode model;
and adding the current-voltage parameter, the capacitance-voltage parameter, the high and low temperature parameters, the breakdown voltage parameter, the tunneling current parameter and the temperature parameter into the combined model to obtain a simulation model of the field effect transistor.
Optionally, the respectively obtaining the breakdown voltage parameter, the tunneling current parameter, and the temperature parameter of the first diode model and the second diode model includes:
acquiring respective breakdown voltage parameters according to the breakdown voltages of the first diode and the second diode in the first diode model and the second diode model respectively;
respectively acquiring corresponding tunneling current parameters according to leakage currents of the first diode and the second diode at normal temperature;
and respectively obtaining corresponding temperature parameters according to the leakage currents of the first diode and the second diode at high temperature and low temperature.
Optionally, the tunneling current parameters include a diode bottom tunneling saturation current parameter and a diode sidewall tunneling saturation current parameter.
Optionally, the normal temperature is 25 ℃, the high temperature is 150 ℃, and the low temperature is-40 ℃.
Optionally, the leakage current at the normal temperature is obtained by zeroing a gate voltage in the field effect transistor model at 25 ℃ and testing a drain current.
The invention provides a system and a method for establishing a simulation model of a field effect transistor, which are characterized in that on the basis of an original JFET model, adding a first diode between a body electrode and a drain electrode of the JFET, adding a second diode between the body electrode and a source electrode, constructing a first diode model and a second diode model, sequentially extracting various parameters of the JFET model, the first diode model and the second diode model based on test data, setting source current of a diode of the JFET model to zero, the capacitor voltage characteristic and the leakage characteristic are represented by all parameters together, so that the problem of convergence caused by the built-in diode of the JFET is avoided, meanwhile, the newly established system for establishing the simulation model of the field effect transistor can better reflect the physical structure of the device, and parameter extraction is carried out based on the model architecture, so that the simulation accuracy of model parameters can be ensured, and good model characteristics can be obtained.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a simple structure diagram of a JFET model of gate series resistance;
fig. 2a and 2b show a current-voltage characteristic diagram and a capacitance-voltage characteristic diagram, respectively, of the JFET model according to fig. 1;
FIG. 3 is a simplified schematic diagram of a semiconductor model according to an embodiment of the present invention;
FIG. 4 shows a block diagram of a semiconductor model according to an embodiment of the invention;
FIG. 5 shows a flow chart of a method of building a semiconductor model according to an embodiment of the invention;
fig. 6a and 6b show a current-voltage characteristic graph and a capacitance-voltage characteristic graph, respectively, of a semiconductor model according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 shows a simple structure diagram of a JFET model of gate series resistance; fig. 2a and 2b show a current-voltage characteristic diagram and a capacitance-voltage characteristic diagram, respectively, of the JFET model according to fig. 1.
As shown in fig. 1, the JFET model structure of the prior art includes a JFET having a source S, a drain D, a gate G and a body B. In the SPICE model of the JFET, a built-in parasitic diode D0 is arranged between a grid electrode and a source electrode, when the voltage between the grid electrode and the source electrode is large, the grid current is excessive, and therefore the SPICE simulation has convergence problems, such as poor convergence or incapability of convergence. To solve this problem, a resistor rg is connected in series with the gate G, which, although it can solve the convergence problem, affects the model current/capacitance versus voltage characteristic (IV/CV).
Fig. 2a represents the IV characteristic diagram, with the ordinate Ids representing the drain current, the abscissa vgs representing the gate voltage, the dotted line representing the normal JFET simulation result (i.e. the simulation result without the resistor rg), and the solid line representing the simulation result after the gate series resistor rg. Fig. 2b represents a CV characteristic diagram, wherein the ordinate cgg represents the gate capacitance, the abscissa vgs represents the gate voltage, the dotted line represents the simulation result of a normal JFET (i.e., the simulation result without the resistor rg), and the solid line represents the simulation result after the gate series resistor rg. As can be seen from fig. 2a and 2b, the simulation result after the resistors are connected in series deviates from the original characteristic curve, thereby seriously affecting the accuracy of the JFET model.
To this end, the present application proposes a new semiconductor model that can achieve good current-voltage and capacitance-voltage characteristics while solving the convergence problem. As described in detail below in conjunction with fig. 3-6 b.
FIG. 3 is a simplified schematic diagram of a semiconductor model according to an embodiment of the present invention; FIG. 4 shows a block diagram of a semiconductor model according to an embodiment of the invention.
As shown in fig. 3, the equivalent circuit of the semiconductor model includes a Junction Field Effect Transistor (JFET) and two diodes, the JFET model 110 is established based on the JFET, the first diode model is established based on the first diode dio1, and the second diode model is established based on the second diode dio 2. In the JFET model 110, node G represents the gate, node D represents the drain, node S represents the source, and node B represents the bulk electrode. First diode dio1 is an external diode connected between the body electrode and the drain, second diode dio2 is an external diode connected between the body electrode and the source, and the anode of first diode dio1 is connected to the body electrode, and the anode of second diode dio2 is also connected to the body electrode. The equivalent circuit of the JFET model is illustrated in fig. 3 by taking an N-type JFET as an example, and it is conceivable that the model of the P-type JFET is similar (the connection of the positive and negative electrodes of the two diodes of the P-type JFET model is opposite to the N-type).
In the semiconductor model of the embodiment, a parasitic diode dio1 is added between the body and the drain, and a parasitic diode dio2 is added between the body and the source on the basis of the original JFET model, so that a new model is constructed. Based on the test data of the JFET model, the parameters of the JFET model are extracted, then the is parameter in the JFET model parameters is set to be 0(is represents the gate saturation junction current and is also called as the gate current parameter in the following process), and the leakage current of the JFET is fitted through the first diode dio1 and the second diode dio2, so that various parameters of the semiconductor model are obtained.
As shown in fig. 4, the semiconductor model 400 includes: a field effect transistor model 401, a first diode model 402 and a second diode model 403. The field effect transistor model 401 comprises four connecting ends of a grid electrode, a source electrode, a drain electrode and a body electrode of the field effect transistor, and the grid current of a diode built in the field effect transistor is zero; first diode model 402 includes a first diode dio1 connected between the body electrode and the drain of the field effect transistor model; the second diode model 402 includes a second diode dio2 connected between the body electrode and the source of the field effect transistor model, with both the first diode dio1 and the second diode dio2 located external to the field effect transistor.
In this embodiment, the field effect transistor model 401 represents the leakage characteristics and the capacitance-voltage characteristics of the field effect transistor through a current-voltage parameter (IV), a capacitance-voltage parameter (CV), and high and low temperature parameters. The first diode model 402 and the second diode model 403 characterize the leakage characteristic and the capacitance-voltage characteristic of the field effect transistor by the breakdown voltage parameter (vb) and the temperature parameter (xti). The breakdown voltage parameter (vb) is obtained from the breakdown voltages of the first diode dio1 and the second diode dio2, respectively, and the temperature parameter (xti) is obtained from the leakage current at a plurality of different simulation temperatures of the semiconductor model 400. The semiconductor model 400 is stored in a sub-circuit form, i.e. a field effect transistor model 401, a first diode model 402 and a second diode model 403 are combined into a sub-circuit form.
The semiconductor model architectures shown in fig. 3-4 can better reflect the physical structure of the device, and parameter extraction is performed based on the model architectures, so that the problem of convergence in SPICE simulation can be solved, and the accuracy of the IV/CV characteristics of the model can be ensured.
FIG. 5 shows a flow chart of a method of building a semiconductor model according to an embodiment of the invention;
as shown in fig. 5, a method for establishing a semiconductor model is provided, in which parasitic diodes are respectively externally connected to two ends D, S of a JFET, and model parameters of the JFET and two diodes dio1/dio2 are sequentially extracted, so as to complete modeling of the semiconductor model, and the method specifically includes the following steps:
in step S101, a current-voltage parameter, a capacitance-voltage parameter, and a high-low temperature parameter are obtained according to the established test data of the field effect transistor model.
The field effect transistor model 401 is built from only JFETs and then the parameters of the JFET model are extracted according to a conventional procedure. The extracted JFET model parameters include a current-voltage parameter (IV characteristic parameter): vto, alpha, beta, lambda, gamds, is, k1, ucrit (vto denotes the JFET threshold voltage, alpha denotes the saturation factor, beta denotes the transconductance coefficient, lambda denotes the channel length modulation coefficient, gamds denotes the drain voltage causing the threshold voltage lowering effect, k1 denotes the effect of the bulk voltage on the threshold voltage, ucrit denotes the threshold electric field for mobility lowering); capacitance-voltage parameter (CV characteristic parameter): gcap, crat, pb, cvto (gcap denotes gate capacitance at zero bias, crat denotes gate capacitance scaling factor, pb denotes gate junction potential, cvto denotes threshold voltage of capacitance model); high and low temperature parameters: tcv, beta ce. (tcv denotes threshold voltage temperature coefficient and beta denotes beta temperature coefficient).
In step S102, a gate current parameter corresponding to a built-in diode in the field effect transistor model is set to zero, and the current-voltage parameter includes the gate current parameter.
And setting the parameter is in the JFET model to be 0, namely turning off a diode built in the JFET, thereby avoiding the problem of convergence caused by overlarge gate current.
In step S103, a first diode model and a second diode model are built outside the field effect transistor model to form a combined model.
Modifying a JFET model structure, and respectively adding a first diode dio1 and a second diode dio2 at two ends of a source electrode and a drain electrode of the JFET model, so that a first diode model 402 and a second diode model 403 are built outside a field effect transistor model 401 to form a combined model, and the combined model is stored in a sub-circuit mode.
In step S104, a breakdown voltage parameter, a tunneling current parameter, and a temperature parameter of the first diode model and the second diode model are obtained, respectively.
The method comprises the following steps: acquiring respective breakdown voltage parameters vb according to the breakdown voltages of the first diode dio1 and the second diode dio 2; respectively obtaining tunneling current parameters corresponding to the first diode dio1 and the second diode dio2 according to leakage currents at normal temperature, wherein the tunneling current parameters comprise a diode bottom tunneling saturation current parameter jtun and a diode side wall tunneling saturation current parameter jtunnw; the respective corresponding temperature parameters are obtained according to the leakage currents of the first diode dio1 and the second diode dio2 at high temperature and low temperature, respectively.
In this step, based on the characteristics of the actual device, the reverse breakdown voltage is respectively tested for the first diode dio1 and the second diode dio2 to obtain two vb parameters, and the first diode model 402 and the second diode model 403 are respectively corrected. Since the breakdown voltage of the diode across the source and drain of a JFET may not be the same in an actual device, actual test data needs to be incorporated.
When the tunneling current parameters corresponding to the first diode dio1 and the second diode dio2 are respectively obtained according to the leakage currents at the normal temperature, the tunneling current parameters can be obtained by setting the gate voltage to zero, grounding the drain and testing the drain current in the field effect transistor model at 25 ℃. The normal temperature is represented by 25 ℃, and parameters jtun and jtensw of the two diode models are respectively adjusted based on the leakage current of the JFET at 25 ℃.
And (3) representing high temperature by 150 ℃ and low temperature by-40 ℃, respectively testing the JFET at two temperatures to obtain leakage current, and extracting the temperature parameters xti of the two diode models.
In step S105, the current-voltage parameter, the capacitance-voltage parameter, the high-low temperature parameter, the breakdown voltage parameter, the tunneling current parameter, and the temperature parameter are all added to the combined model to obtain a semiconductor model.
And adding the parameters obtained in the steps into the combined model to obtain a final semiconductor model 400, and simulating and measuring various characteristics of the model.
Referring to fig. 4 and 5, the semiconductor model 400 of the present embodiment first extracts parameters of a field effect transistor model 401(JFET model) based on measured IV/CV data of the JFET model; and then, setting the is parameter of the JFET model parameter to be 0, and avoiding the problem of non-convergence caused by a built-in diode between the model source electrode and the model grid electrode. Then adding external diodes dio1 and dio2 in the JFET model; correspondingly updating the parameters vb of the first diode model 402 and the second diode model 403 according to the test data of the breakdown voltage between the drain and the source of the two diodes respectively; then, fitting the leakage current of the JFET at 25 ℃ by adjusting the parameters jtun/jtensw of the first diode model 402 and the second diode model 403 (jtun represents the tunneling saturation current at the bottom of the diode, and jtensw represents the tunneling saturation current at the side wall of the diode); the leakage currents of the JFETs at high and low temperatures, respectively, are fitted by adjusting xti parameters of the first diode model 402 and the second diode model 403. Thus, various parameters of the semiconductor model are obtained, and the parameters are added into the combined model to obtain the complete semiconductor model. Therefore, the simulation characteristics of all parameters are ensured to be good, and the problem of convergence is solved.
FIGS. 6a and 6b show a current-voltage characteristic graph and a capacitance-voltage characteristic graph, respectively, of a semiconductor model according to an embodiment of the present invention
Fig. 6a represents the IV characteristic (Ids _ vgs), with the ordinate Ids representing the drain current, the abscissa vgs representing the gate voltage, the dashed line representing the simulation result for the JFET model only (Ids _ JFET), and the solid line representing the simulation result for the semiconductor model of the embodiment of the invention (Ids _ JFET + dio). Fig. 6b represents a CV (cgg _ vgs) characteristic diagram, with the ordinate cgg representing the gate capacitance, the abscissa vgs representing the gate voltage, the dashed line representing the simulation result of the JFET model alone (ids _ JFET), and the solid line representing the simulation result of the semiconductor model of the embodiment of the invention (ids _ JFET + dio). As can be seen from fig. 6a and 6b, the simulation result of the improved semiconductor model of the present embodiment is consistent with the simulation result of the JFET model, so that the IV/CV square vibration characteristics can be ensured to be good, and the simulation result is accurate.
In summary, the semiconductor model and the model establishing method thereof provided by the invention are based on the original JFET model, the first diode is added between the body electrode and the drain electrode of the JFET, the second diode is added between the body electrode and the source electrode, the first diode model and the second diode model are constructed, then based on the test data, the parameters of the JFET model, the first diode model and the second diode model are sequentially extracted, the source current of the diode of the JFET model is set to zero, the capacitance voltage characteristic and the leakage characteristic are represented by the parameters together, so that the convergence problem caused by the built-in diode of the JFET is avoided, meanwhile, the newly established semiconductor model can better reflect the physical structure of the device, the parameter extraction is carried out based on the model architecture, the simulation accuracy of the model parameters can be ensured, and good current-voltage characteristic and capacitance-voltage characteristic are obtained, can simultaneously take account of the convergence and the model characteristic, and has good model stability.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A system for modeling a simulation model of a field effect transistor, comprising:
the field effect transistor model comprises four connecting ends of a grid electrode, a source electrode, a drain electrode and a body electrode of the field effect transistor, wherein the grid electrode current of a diode built in the field effect transistor is zero, and the field effect transistor model is used for acquiring a current-voltage parameter, a capacitance-voltage parameter and a high-low temperature parameter according to the built test data of the field effect transistor model;
a first diode model comprising a first diode connected between a body electrode and a drain electrode of the field effect transistor model;
a second diode model comprising a second diode connected between a body electrode and a source electrode of the field effect transistor model,
the combined model formed by the first diode model and the second diode model is used for acquiring a breakdown voltage parameter, a tunneling current parameter and a temperature parameter of the combined model, and obtaining a simulation model of the field effect transistor according to the current-voltage parameter, the capacitance-voltage parameter, the high-low temperature parameter, the breakdown voltage parameter, the tunneling current parameter and the temperature parameter,
wherein the field effect transistor model represents the leakage characteristic and the capacitance-voltage characteristic of the field effect transistor model through the current-voltage parameter, the capacitance-voltage parameter and the high-low temperature parameter,
and the first diode model and the second diode model represent the leakage characteristic and the capacitance-voltage characteristic of the simulation model through the breakdown voltage parameter, the tunneling current parameter and the temperature parameter.
2. The system for creating a simulation model of a field-effect transistor according to claim 1, wherein the breakdown voltage parameter is obtained from breakdown voltages of the first diode and the second diode, respectively, the tunneling current parameter is obtained from leakage currents of the first diode and the second diode at normal temperature, respectively, and the temperature parameter is obtained from leakage currents of the simulation model of the field-effect transistor at high temperatures and low temperatures.
3. The system for creating a simulation model of a field effect transistor of claim 2, wherein the tunneling current parameters comprise a diode bottom tunneling saturation current parameter and a diode sidewall tunneling saturation current parameter.
4. The system for creating a simulation model of a field effect transistor according to claim 2, wherein the normal temperature is 25 ℃, the high temperature is 150 ℃, and the low temperature is-40 ℃.
5. The system for building a simulation model of a field effect transistor according to claim 1, wherein the simulation model of the field effect transistor is stored in a sub-circuit form.
6. A method for establishing a simulation model of a field effect transistor comprises the following steps:
acquiring a current-voltage parameter, a capacitance-voltage parameter and a high-low temperature parameter according to the established test data of the field effect transistor model;
setting gate current parameters corresponding to a built-in diode in the field effect transistor model to zero, wherein the current-voltage parameters comprise the gate current parameters;
constructing a first diode model and a second diode model outside the field effect transistor model to form a combined model;
respectively acquiring breakdown voltage parameters, tunneling current parameters and temperature parameters of the first diode model and the second diode model;
adding the current-voltage parameter, the capacitance-voltage parameter, the high and low temperature parameters, the breakdown voltage parameter, the tunneling current parameter and the temperature parameter into the combined model to obtain a simulation model of the field effect transistor,
wherein the field effect transistor model represents the leakage characteristic and the capacitance-voltage characteristic of the field effect transistor model through the current-voltage parameter, the capacitance-voltage parameter and the high-low temperature parameter,
and the first diode model and the second diode model represent the leakage characteristic and the capacitance-voltage characteristic of the simulation model through the breakdown voltage parameter, the tunneling current parameter and the temperature parameter.
7. The method of building a simulation model of a field effect transistor according to claim 6, wherein obtaining a breakdown voltage parameter, a tunneling current parameter, and a temperature parameter of the first diode model and the second diode model, respectively, comprises:
acquiring respective breakdown voltage parameters according to the breakdown voltages of the first diode and the second diode in the first diode model and the second diode model respectively;
respectively acquiring corresponding tunneling current parameters according to leakage currents of the first diode and the second diode at normal temperature;
and respectively obtaining corresponding temperature parameters according to the leakage currents of the first diode and the second diode at high temperature and low temperature.
8. The method of claim 7, wherein the tunneling current parameters comprise a diode bottom tunneling saturation current parameter and a diode sidewall tunneling saturation current parameter.
9. The method for creating a simulation model of a field effect transistor according to claim 7, wherein the normal temperature is 25 ℃, the high temperature is 150 ℃, and the low temperature is-40 ℃.
10. The method for creating a simulation model of a field effect transistor according to claim 9, wherein the leakage current at normal temperature is obtained by testing a drain current by zeroing a gate voltage in the field effect transistor model at 25 ℃.
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