CN113128141B - Median filtering system based on error-free random calculation - Google Patents
Median filtering system based on error-free random calculation Download PDFInfo
- Publication number
- CN113128141B CN113128141B CN202110416068.8A CN202110416068A CN113128141B CN 113128141 B CN113128141 B CN 113128141B CN 202110416068 A CN202110416068 A CN 202110416068A CN 113128141 B CN113128141 B CN 113128141B
- Authority
- CN
- China
- Prior art keywords
- random
- comparator
- output
- sequence
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Abstract
The invention discloses a median filtering system based on error-free random calculation, which is applied to the field of digital image processing optimization design and aims at solving the problem of larger resource consumption in the prior art, and the median filtering system comprises: the device comprises a forward conversion module, a random comparator and a backward conversion module; the forward conversion module comprises a concentrated sequence generation unit and a uniform sequence generation unit, wherein the concentrated sequence generation unit and the uniform sequence generation unit are used for respectively converting binary signals into a uniformly distributed sequence and a concentrated distributed sequence; the output end of the concentrated sequence generating unit is connected with the input end of the random comparator, the output end of the uniform sequence generating unit is connected with the selecting end of the random comparator, and the output end of the random comparator is connected with the backward conversion module; the backward conversion module converts the random sequence output by the random comparator into a binary numerical value; the median filter can be well applied to the fields of digital image median filtering noise reduction and the like.
Description
Technical Field
The invention belongs to the field of digital image processing optimization design, and particularly relates to a technology for realizing a median filtering system.
Background
The current integrated circuit has the requirements of high operation performance, small integrated area, low power consumption and the like. With the continuous development of science and technology, the size of the transistor is continuously reduced, and more transistors can be integrated in a unit area. However, as Dennard's scaling law fails, the field of computing has met with unprecedented challenges. According to Moore's law, the leakage current increases with the decrease in the size of the transistor, and the power consumption of the integrated circuit increases, but the performance is not improved, and the reliability of the complex and precise chip becomes the most concerned issue for designers at the present stage, which promotes the development of new computing technology.
In the design of a random calculation digital circuit, a common forward conversion unit uses a Linear Feedback Shift Register (LFSR) to generate a random number source, different initial values of the Linear Feedback Shift Register (LFSR) are set, and output sequences of forward conversion are different, so that not only can a pseudo-random bit stream be generated, but also autocorrelation of the bit stream sequence can be well reduced, but each path of the random circuit needs an independent initial random number to drive, and thus, the circuit area and the resource occupation of the forward conversion unit are greatly increased.
Disclosure of Invention
In order to solve the technical problem, the invention provides a median filtering system based on error-free random calculation.
The technical scheme adopted by the invention is as follows: an error-free stochastic computation-based median filtering system, comprising: the device comprises a forward conversion module, a random comparator module and a backward conversion module;
the forward conversion module comprises a concentrated sequence generation unit and a uniform sequence generation unit, wherein the concentrated sequence generation unit and the uniform sequence generation unit are used for respectively converting binary signals into a concentrated distribution sequence and a uniform distribution sequence;
the output end of the concentrated sequence generating unit is connected with the input end of the random comparator, the output end of the uniform sequence generating unit is connected with the selecting end of the random comparator, and the output end of the random comparator is connected with the backward conversion module; the backward conversion module converts the random sequence output by the random comparator into a binary value.
The counter also comprises a clock period module, and the clock period module and the forward conversion module share one adding counter.
The generation process of the centralized distribution sequence comprises the following steps: comparing the weighted binary number with the up-counter value of the current clock period, and if the weighted binary number is larger than the up-counter value of the current clock period, outputting a bit stream of '1'; otherwise, the output bit stream is '0', and since the current clock cycle is equal to the last clock cycle plus 1, the centrally distributed sequence with '1' at the head of the sequence and '0' at the tail of the sequence can be output.
The generation process of the uniform sequence generation unit comprises the following steps: and performing phase-AND on the binary bar code of the value of the added counter in the current clock period and the value of the added counter in the previous clock period to obtain each bit output, performing phase-AND on each bit output in the binary weighting number respectively, and connecting the obtained outputs with an OR gate respectively to finally obtain a uniformly distributed sequence of the weighted binary number.
Comprising three binary signals.
The random comparator module is a structure formed by cascading three random comparators, correspondingly, the three random comparators are sequentially recorded as a first random comparator, a second random comparator and a third random comparator, three concentrated sequences of three binary signals after passing through the forward conversion module are used as the input of the first random comparator, the larger output of the other concentrated sequence and the larger output of the first random comparator are used as the input of the second random comparator, the smaller output of the first random comparator and the smaller output of the second random comparator are used as the input of the third random comparator, the larger output of the second random comparator is used as the maximum sequence output of the random comparator module, the larger output of the third random comparator is used as the median sequence output of the random comparator module, and the smaller output of the third random comparator is used as the minimum sequence output of the random comparator module; the evenly distributed sequence is used as the input of the selection end of three random comparators.
The single random comparator includes: the device comprises a first random comparison module, a stanh module, a second random comparison module and a third random comparison module; two input ends of the three random comparison modules are used as two input ends of the random comparator, the input of the two input ends of the random comparator is in opposite phase, and a selection end of the first random comparison module is used as a selection end of the random comparator; the output end of the first random comparison module is connected with the input end of the stanh module, and the output end of the stanh module is respectively connected with the respective selection ends of the second random comparison module and the third random comparison module; the output of the second random comparison module is used as the larger output end of the random comparator, and the output of the third random comparison module is used as the smaller output end of the random comparator.
The stanh module is specifically a stanh function based on a finite state machine, and specifically:
the conversion principle of the state transition diagram is as follows: n states, respectively S 0 、S 1 、…、S n-1 X is used as the initial input value of the state machine, and Y is output only with the current state S i In relation to this, 0 < i < N-1, and if 0 < i ≦ N/2-1, the output value Y =0; otherwise the output value Y =1.
The invention has the beneficial effects that: the random calculation is a representation form of approximate or inaccurate calculation, the invention can realize the error-free output result of the random comparator, the structure comprises a forward conversion module, a random comparator and a backward conversion module, the random comparator can be cascaded, the forward conversion module, the random comparator and the backward conversion module are sequentially connected by circuits, an input binary signal generates a uniform distribution sequence and a concentrated distribution sequence through a probability sequence generator, the concentrated distribution sequence is used as the input end of the random comparator, the uniform distribution sequence is used as the selection end of the random comparator, the output end of the random comparator is connected with the backward conversion module, the conversion from the random sequence to the traditional binary value is completed, and the invention can be well applied to the fields of digital image median filtering, noise reduction and the like; the median filtering system based on error-free random calculation of the invention has the following advantages:
1. the improved stochastic comparator model achieves stochastic computation results without intrinsic errors by fixing the probability distribution based on an up-counter conversion unit to reduce cross-correlation.
2. The clock period module and the forward conversion module can share one adding counter, so that the resource consumption is reduced.
3. The random calculation can be well applied to the fields of median filtering, noise reduction and the like.
Drawings
FIG. 1 is a block diagram of a median filtering system in accordance with the present invention;
fig. 2 is a schematic diagram of a 3 x 3 sliding window of median filtering in the present invention;
FIG. 3 is a schematic diagram of a centralized sequence generation unit according to the present invention;
FIG. 4 is a schematic diagram of a uniform sequence generation unit in the present invention;
FIG. 5 is a diagram of a finite state machine based transition in the present invention;
FIG. 6 is a diagram showing an internal structure of a random comparator according to the present invention;
FIG. 7 is a diagram of a cascade of random comparators in accordance with the present invention;
FIG. 8 is a graph of the results of an experiment applied to median filtering of an image according to the present invention;
fig. 8 (a) is an original image, fig. 8 (b) is a median filtering result implemented by a conventional method, and fig. 8 (c) is a median filtering result implemented based on random calculation.
Detailed Description
In order to facilitate the understanding of the technical contents of the present invention by those skilled in the art, the present invention will be further explained with reference to the accompanying drawings.
As shown in fig. 1, an error-free random computation-based median filtering system of the present invention includes: the device comprises a forward conversion module, a random comparator and a backward conversion module; the forward conversion module comprises a concentrated sequence generation unit and a uniform sequence generation unit, and is used for respectively converting binary signals into a concentrated distribution sequence and a uniform distribution sequence; the random comparator is used for outputting a maximum concentrated distribution sequence and a minimum concentrated distribution sequence; the backward conversion module is used for converting the output random sequence back to a binary value.
The forward conversion unit in this embodiment uses a Linear Feedback Shift Register (LFSR) to generate a random number source, sets different initial values of the Linear Feedback Shift Register (LFSR), and has different output sequences of forward conversion, thereby not only generating a pseudo-random bit stream, but also well reducing autocorrelation of the bit stream sequence.
As shown in fig. 2, the median filtering 3 × 3 sliding window output value schematic diagram, when implemented using software, compares the pixel values of each column (row) first, and sorts them according to the maximum value, the middle value and the minimum value; then comparing the column (row) with the maximum value to take the minimum value, comparing the column (row) with the intermediate value to take the intermediate value, and comparing the column (row) with the minimum value to take the maximum value; finally, comparing the three values in the previous step, taking a middle value, which is the required statistical median in the window, as the output of the window, the specific example comparing process shown in fig. 2 is as follows:
and 3, finally comparing the three values, and taking a middle value, wherein the middle value is the statistical median med {50, 37, 24} in the required window, namely the output value of the 37-bit window.
As shown in fig. 3, a centralized distribution sequence generation unit that generates a binary weighted number X [ n-1:0] is compared with the up-counter value cnt of the current clock period, so that the forward conversion unit based on the up-counter is used, the cross correlation among sequences can be reduced through the distribution of fixed probability, not only can the circuit multiplexing be realized, but also the resource consumption can be reduced. And the adding counter in the forward conversion unit can also be shared with the adding counter in the clock period module, so that the operating efficiency of the circuit is further improved. Wherein the up-counter can be shared by all forward converters, and if X > cnt, the output bitstream is "1"; if X is less than or equal to cnt, the output bit stream is '0', and since cnt = cnt +1 in each clock cycle, a centralized distribution sequence with '1' at the head of the sequence and the rest bits being '0' at the tail of the sequence, such as the number to be converted 5, can be output, and the centralized distribution sequence 11111000 of 8-bit generated by the centralized conversion unit.
X [ n-1:0 represents the binary sequence to be converted, and X represents the binary weighted number of n bits.
As shown in fig. 4, the uniformly distributed sequence generation unit, in which the up-counter is shared by all forward converters, the up-counter value cnt of the current clock cycle is anded with the binary inverse of the up-counter value of the previous clock cycle, and its function is to act as a rising edge detector, and the resulting output per bit is respectively compared with the binary weight X [ n-1: and (0) and the outputs are respectively connected with an OR gate, and then the weighted binary number X [ n-1:0] in a uniformly distributed sequence.
X in FIG. 4 0 、…、X i 、…、X n-1 Respectively represent X [ n-1:0]N bits.
As shown in fig. 5, the finite state machine based state transition diagram is composed of a set of N states arranged in a linear fashion (saturating counter). Typically, N =2 is chosen K Where K is a positive integer, the transition from the first state to the last state must be accomplished by successive transitions of all intermediate states. Wherein, the conversion principle of the state transition diagram is that N states are S respectively 0 、S 1 、…、S i 、…、S N-1 X is used as the initial input value of the state machine, and Y is output only with the current state S i If the value is more than 0 and less than or equal to N/2-1, the output value Y =0; otherwise, the output value Y =1, thereby constructing a stanh function based on a finite state machine, and on the basis of the existing model, the invention not only realizes an error-free calculation result, but also reduces the original state number to only four states to realize functions, thereby greatly reducing the circuit area and the resource occupation.
As shown in fig. 6, the internal structure of the random comparator, wherein a and B are the input ends of the random comparator and are the concentrated distribution sequences, R is the selection end of the data selector and is the uniform distribution sequence, the generated random bit stream difference is sent to the stanh module, as can be known from the configuration of the stanh module,
further obtain P of 0. Ltoreq. P X When less than 0.5, P Y ＝0；P X When =0.5, P Y ＝1/2；0.5＜P X When the ratio is less than or equal to 1, P Y And =1. So if A > B, then P X > 0.5,s =1,stanh module tends to remain on the high side, the rightmost datator selects a; if A < B, then P X < 0.5,s =0,stanh module tends to remain on the low state side, and the rightmost data selector selects B, thereby outputting the maximum and minimum concentrated distribution sequences, respectively. Where S denotes the output of the stanh module.
P Y Representing the probability of 1 for each bit in the output bitstream；P X Represents the probability of each bit 1 in the input bitstream;
is expressed in an input probability P X The current state is the probability of i; n represents the total number of states.
As shown in fig. 7, the random comparator cascade diagram is formed by cascading the above mentioned random comparators, and the operation principle thereof is briefly described as follows: binary signals a, B and C are respectively converted into random bit streams through a forward conversion unit to obtain three sequences A, B and C; firstly, comparing the sizes of the two sequences B and C, storing a larger sequence into MAX1, and storing a smaller sequence into MIN1; then comparing the size of the MAX1 and A sequences, storing the larger sequence into MAX and the smaller sequence into MIN2; and finally, comparing the sizes of the two sequences of the MINi and the MIN2, storing the larger sequence into the MID, and storing the smaller sequence into the MIN, thereby respectively outputting the maximum sequence MAX, the median sequence MID and the minimum sequence MIN.
As shown in fig. 8, the cascaded random comparator can be applied to the field of digital image processing such as median filtering, and the whole process is implemented by using a random bit stream, in a tested IEEE gallery, the pixel value of each pixel point is represented by a gray value represented by an 8-bit weighted binary, where fig. 8 (a) is an original image, fig. 8 (b) is a median filtering result implemented by a conventional method, and fig. 8 (c) is a median filtering result implemented based on random computation, and it can be found that the median filter based on random computation of the present invention has no inherent probability value error compared with the median filter under the weighted binary system.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (4)
1. An error-free stochastic computation-based median filtering system, comprising: the device comprises a forward conversion module, a random comparator module and a backward conversion module;
the forward conversion module comprises a concentrated sequence generation unit and a uniform sequence generation unit, wherein the concentrated sequence generation unit and the uniform sequence generation unit are used for respectively converting binary signals into a uniformly distributed sequence and a concentrated distributed sequence;
the generation process of the centralized distribution sequence comprises the following steps: comparing the weighted binary number with the up-counter value of the current clock period, and if the weighted binary number is larger than the up-counter value of the current clock period, outputting a bit stream of '1'; otherwise, the output bit stream is '0', because the current clock period is equal to the last clock period and is added with 1, the output '1' is completely at the head of the sequence, and the rest bits are '0' and are distributed in the concentration of the tail of the sequence;
the generation process of the uniform sequence generation unit comprises the following steps: taking the phase of the binary inverse of the value of the counter added in the current clock period and the value of the counter added in the previous clock period, taking the phase of each obtained bit output with each bit phase in the binary weighting number, and connecting the obtained outputs with an OR gate respectively to finally obtain a uniform distribution sequence of the weighted binary number;
the output end of the concentrated sequence generating unit is connected with the input end of the random comparator, the output end of the uniform sequence generating unit is connected with the selection end of the random comparator, and the output end of the random comparator is connected with the backward conversion module; the backward conversion module converts the random sequence output by the random comparator into a binary numerical value;
the counter also comprises a clock period module, and the clock period module and the forward conversion module share one adding counter.
2. The error-free random computation-based median filtering system according to claim 1, wherein the random comparator module is a cascade structure of three random comparators, the three random comparators are sequentially identified as a first random comparator, a second random comparator and a third random comparator, each random comparator comprises two inputs, by comparing the two inputs, the larger one of the two inputs is used as the larger output of the random comparator, the smaller one of the two inputs is used as the smaller output of the random comparator, the random comparator correspondingly comprises three binary signals, and three concentrated sequences of the three binary signals after passing through a forward conversion module are formed, wherein the two concentrated sequences are used as the inputs of the first random comparator, the larger output of the other concentrated sequence and the first random comparator are used as the inputs of the second random comparator, the smaller output of the first random comparator and the smaller output of the second random comparator are used as the inputs of the third random comparator, the larger output of the second random comparator is used as the maximum sequence output of the random comparator module, the smaller output of the third random comparator is used as the minimum output of the random comparator module; the evenly distributed sequence is used as the input of the selection end of three random comparators.
3. The error-free stochastic computation based median filtering system according to claim 2, wherein the single stochastic comparator comprises: the device comprises a first random comparison module, a stanh module, a second random comparison module and a third random comparison module; two input ends of the three random comparison modules are used as two input ends of the random comparator, the input of the two input ends of the random comparator is in opposite phase, and a selection end of the first random comparison module is used as a selection end of the random comparator; the output end of the first random comparison module is connected with the input end of the stanh module, and the output end of the stanh module is respectively connected with the respective selection ends of the second random comparison module and the third random comparison module; the output of the second random comparison module is used as the larger output end of the random comparator, and the output of the third random comparison module is used as the smaller output end of the random comparator.
4. The median filtering system based on error-free stochastic computation of claim 3, wherein the stanh module is specifically a finite state machine-based stanh function, specifically:
the transition principle of the state transition diagram is as follows: n states, respectively S 0 、S 1 、、、S N-1 X is used as the initial input value of the state machine, and Y is output only with the current state S i About 0<i<N-1, if 0<if i is less than or equal to N/2-1, the output value Y =0; otherwise the output value Y =1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110416068.8A CN113128141B (en) | 2021-04-19 | 2021-04-19 | Median filtering system based on error-free random calculation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110416068.8A CN113128141B (en) | 2021-04-19 | 2021-04-19 | Median filtering system based on error-free random calculation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113128141A CN113128141A (en) | 2021-07-16 |
| CN113128141B true CN113128141B (en) | 2023-03-24 |
Family
ID=76777377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110416068.8A Active CN113128141B (en) | 2021-04-19 | 2021-04-19 | Median filtering system based on error-free random calculation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113128141B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117314730B (en) * | 2023-11-28 | 2024-03-15 | 进迭时空(杭州)科技有限公司 | Median filtering computing device and method for accelerating digital image processing |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104782116A (en) * | 2012-09-18 | 2015-07-15 | 菲力尔系统公司 | Row and column noise reduction in thermal images |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060099123A (en) * | 2005-03-10 | 2006-09-19 | 엘지전자 주식회사 | Solt noise elimination method in case of tilt adjustment using tracking error and adjustment error improvement method |
| CN102740340B (en) * | 2012-07-19 | 2014-08-20 | 中南大学 | Data gathering method oriented to same configuration nodes in network cluster of wireless sensor |
| CN108446606A (en) * | 2018-03-01 | 2018-08-24 | 苏州纳智天地智能科技有限公司 | A kind of face critical point detection method based on acceleration binary features extraction |
| CN110620566B (en) * | 2019-09-25 | 2021-07-02 | 电子科技大学 | FIR filtering system based on combination of random calculation and remainder system |
| CN110677138B (en) * | 2019-09-25 | 2021-06-15 | 电子科技大学 | FIR filter based on error-free probability calculation |
-
2021
- 2021-04-19 CN CN202110416068.8A patent/CN113128141B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104782116A (en) * | 2012-09-18 | 2015-07-15 | 菲力尔系统公司 | Row and column noise reduction in thermal images |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113128141A (en) | 2021-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109143832B (en) | High-precision multichannel time-to-digital converter | |
| US8462028B2 (en) | Parallel to serial conversion apparatus and method of converting parallel data having different widths | |
| CN111404550B (en) | Analog-to-digital converter and clock generation circuit thereof | |
| CN113128141B (en) | Median filtering system based on error-free random calculation | |
| CN114968179A (en) | True random number generating circuit based on clock jitter and metastable state | |
| TW200915173A (en) | Data bus inversion detection mechanism | |
| CN112698811A (en) | Neural network random number generator sharing circuit, sharing method and processor chip | |
| CN115001507A (en) | Parallel-serial conversion circuit | |
| CN110336536B (en) | Circuit and device for true random number generator | |
| US5644253A (en) | Multiple-valued logic circuit | |
| CN213934855U (en) | Neural network random number generator sharing circuit based on random computation | |
| Nair et al. | Design of multistage counters using linear feedback shift register | |
| CN110705196B (en) | Error-free adder based on random calculation | |
| US11475288B2 (en) | Sorting networks using unary processing | |
| Lin et al. | A review of deterministic approaches to stochastic computing | |
| CN113157247B (en) | Reconfigurable integer-floating point multiplier | |
| US20050012523A1 (en) | Half-rate clock logic block and method for forming same | |
| CN114925640A (en) | Multi-stage MPRM logic circuit power consumption optimization method | |
| Chen et al. | 19.7 A scalable pipelined time-domain DTW engine for time-series classification using multibit time flip-flops with 140Giga-cell-updates/s throughput | |
| US10778240B1 (en) | Device and method for digital to analog conversion | |
| CN114374809A (en) | Analog-to-digital conversion circuit of infrared focal plane reading circuit | |
| Sneha et al. | A modified partially parallel polar encoder architecture | |
| CN110890895A (en) | Method for performing polar decoding by means of representation transformation and associated polar decoder | |
| CN220273668U (en) | Circuit for converting parallel signal into serial signal | |
| US20020163359A1 (en) | Data transformation for the reduction of power and noise in CMOS structures |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |