CN113128114B - 一种半导体器件的ssta模型优化方法 - Google Patents
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- CN113128114B CN113128114B CN202110411630.8A CN202110411630A CN113128114B CN 113128114 B CN113128114 B CN 113128114B CN 202110411630 A CN202110411630 A CN 202110411630A CN 113128114 B CN113128114 B CN 113128114B
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CN105247787A (zh) * | 2013-10-03 | 2016-01-13 | 华为技术有限公司 | 可重新配置的多路径注频锁相振荡器 |
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JP2008298621A (ja) * | 2007-05-31 | 2008-12-11 | Toshiba Corp | 半導体集積回路の統計的タイミング解析装置及びそれを用いた解析方法 |
US10839129B2 (en) * | 2019-02-13 | 2020-11-17 | International Business Machines Corporation | Characterization of spatial correlation in integrated circuit development |
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CN105247787A (zh) * | 2013-10-03 | 2016-01-13 | 华为技术有限公司 | 可重新配置的多路径注频锁相振荡器 |
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Effective date of registration: 20220915 Address after: 510000 building a, No. 136, Kaiyuan Avenue, Huangpu Development Zone, Guangzhou, Guangdong Applicant after: Guangdong Dawan District integrated circuit and System Application Research Institute Applicant after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510535 building a, 136 Kaiyuan Avenue, Guangzhou Development Zone, Guangdong Province Applicant before: Guangdong Dawan District integrated circuit and System Application Research Institute Applicant before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
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