CN113126738A

CN113126738A - Power consumption management method and memory module

Info

Publication number: CN113126738A
Application number: CN201911412237.XA
Authority: CN
Inventors: 黄景伦; 马鸿标; 高杉敦
Original assignee: Epp Storage Technology Hangzhou Co ltd
Current assignee: Epp Storage Technology Hangzhou Co ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2021-07-16

Abstract

The invention provides a power consumption management method and a memory module. The method for managing power consumption is applied to a memory module comprising a plurality of memory devices, wherein the memory devices share a bus for communication commands, addresses and data, and comprises enabling a part of the memory devices to no longer hold data and to maintain other memory devices to hold data and entering a hybrid power-saving mode, so that the part of the memory devices in the memory devices no longer hold data and to maintain other memory devices to hold data. Therefore, the power consumption management method and the memory module can set the power consumption of the plurality of memory devices in the memory module respectively, thereby reducing the overall power consumption of the memory module.

Description

Power consumption management method and memory module

Technical Field

The invention belongs to the technical field of memory devices, and particularly relates to a power consumption management method and a memory module.

Background

As the speed development and application of processors become more and more extensive, the requirements for memory speed, memory space size, power consumption, etc. become more and more stringent. Memory modules having multiple memory devices are often designed to multiply the size of the memory space, but at the same time, the overall power consumption of the memory module is also multiplied accordingly. In the Memory device industry, many techniques are applied to try to reduce power consumption, and in recent years, such as a Pseudo Static Random Access Memory (PSRAM) application circuit in a standby mode (standby mode) consumes minimum power to self-refresh (self-refresh) data of Memory cells (Memory cells) in the background, but in a Memory module having a plurality of Memory devices, the above method still needs to consume power for maintaining refreshing all the Memory devices, and it is difficult to achieve a desirable result in terms of the overall power consumption control effect of the Memory module.

Therefore, it is necessary to provide a power consumption management method and a memory module to solve the above technical problems in the prior art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power consumption management method and a memory module, so as to solve the problem that it is difficult to set the power consumption of each of a plurality of memory devices in the memory module, thereby reducing the overall power consumption of the memory module.

In order to achieve the above and other related objects, the present invention provides a power consumption management method applied to a memory module including a plurality of memory devices sharing a bus for communicating commands, addresses and data, the power consumption management method including enabling a portion of the memory devices to no longer hold data and to maintain other memory devices to hold data, and entering a hybrid power saving mode, such that the portion of the memory devices to no longer hold data and to maintain other memory devices to hold data.

As an alternative to the present invention, the step of enabling a portion of the memory devices to no longer retain data and maintaining another portion of the memory devices to retain data may comprise: writing a set of power setting codes to a mode register in the memory device; and when entering the hybrid power saving mode, determining which of the memory devices are enabled to no longer hold data according to the set of power setting codes.

As an alternative of the present invention, the set of power setting codes is a PASR (Partial Array Self-Refresh) mode setting code, the memory device provides a virtual memory space, and a Refresh (Refresh) setting of the virtual memory space according to the set of power setting codes written in advance determines which of the memory devices are enabled to no longer hold data when entering the hybrid power saving mode.

As an alternative of the present invention, each bit of the set of power setting codes corresponds to a specific memory device of the memory devices, and when receiving the set of power setting codes entering the hybrid power saving mode, whether to enable the specific memory device to no longer hold data is determined according to the value of each bit of the set of power setting codes which is pre-written.

As an alternative of the present invention, the set of power setting codes and the half sleep mode setting codes are written into the mode register of the memory devices to enter a hybrid power saving mode, and it is determined which of the memory devices are enabled to no longer hold data according to the set of power setting codes.

As an alternative to the present invention, the step of enabling a portion of the memory devices to no longer retain data and maintaining another portion of the memory devices to retain data may comprise: enabling a portion of the memory devices to no longer retain data through a fuse (fuse) in the portion of the memory devices.

The invention also provides a memory module comprising a plurality of memory devices sharing a bus for communicating commands, addresses and data and providing a virtual memory space, wherein the memory devices are respectively provided with a command decoder and a plurality of mode registers, and the memory devices are configured to enable a part of the memory devices to no longer hold data and maintain other memory devices to hold data and enter a hybrid power-saving mode, so that the part of the memory devices do not hold data and maintain other memory devices to hold data.

As an alternative of the present invention, the mode register includes a mode register space for storing a set of power setting codes written to determine which of the memory devices are enabled to no longer hold data according to the set of power setting codes when entering the hybrid power saving mode.

As an alternative of the invention, the memory devices are each provided with a fuse, so that changing an electrical characteristic of the fuse enables the portion of the memory device to no longer retain data.

As an alternative of the invention, the portion of the memory device that no longer holds data corresponds to at least two memory blocks that are not contiguous in the virtual memory space.

As described above, according to the power consumption management method and the memory module of the present invention, a part of the memory devices in the memory module can no longer hold data and maintain the other memory devices to hold data, and the power consumption of the plurality of memory devices in the memory module can be set respectively, thereby reducing the overall power consumption of the memory module.

Drawings

FIG. 1 is a functional block diagram of a memory module according to an embodiment of the present invention.

FIG. 2 illustrates a mode register table (mode register table) of a mode register according to an exemplary embodiment of the present invention.

FIG. 3 is a clock diagram of the bus for communicating commands, addresses and data to the memory module according to one embodiment of the present invention.

FIG. 4 is a timing diagram illustrating an exemplary memory module entering a hybrid power saving mode according to the invention.

FIG. 5 is a diagram illustrating a mode register table of a mode register according to another embodiment of the present invention.

FIG. 6 shows a schematic diagram of a command decoder of a memory device as an example of the present invention.

FIG. 7 is a schematic diagram of a command decoder of a memory device according to another example of the present invention.

FIG. 8 is a diagram illustrating a mode register table of a mode register according to another embodiment of the present invention.

Fig. 9 is a diagram illustrating an exemplary PASR mode setting code list according to the present invention.

Fig. 10 is a diagram illustrating a PASR mode setting code list according to another embodiment of the present invention.

FIG. 11 is a block diagram of a memory module according to another embodiment of the present invention.

FIG. 12 is a flowchart illustrating an operation of the memory module according to an exemplary embodiment of the present invention.

Description of the element reference numerals

1. 2 storage module

11. 12, 13, 14 memory device

111. 121, 131, 141 instruction decoder

112. 122, 132, 142 mode register

S100, S110, S120, S130, S140

Detailed Description

The power consumption management method and the memory module according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Please refer to fig. 1 to 4 and fig. 12. Fig. 1 is a functional block diagram of an exemplary memory module according to the present invention, fig. 2 is a mode register table (mode register table) of a mode register according to an exemplary embodiment of the present invention, fig. 3 is a clock diagram of a bus for communicating commands, addresses and data of the memory module according to an exemplary embodiment of the present invention, fig. 4 is a clock diagram of the memory module according to an exemplary embodiment of the present invention entering a hybrid power saving mode, and fig. 12 is an operation flowchart of the memory module according to an exemplary embodiment of the present invention. As shown in fig. 1, a memory module 1 to which the power consumption management method of fig. 12 is applied includes a plurality of

memory devices

11, 12 mounted on a substrate. The memory module 1 enables a part of the

memory devices

11, 12, such as: the memory device 11 no longer holds data and maintains other memory devices, such as: the memory device 12 holds data. Here, two

memory devices

11, 12 are illustrated as being packaged in a single package, however, the

memory devices

11, 12 may be arranged by other packaging techniques, such as: wafer level chip scale packaging (wafer level chip scale packaging). Each

memory device

11, 12 includes an

instruction decoder

111, 121 and a plurality of

mode registers

112, 122. The

memory devices

11, 12 are exemplified by memory chips, such as but not limited to PSRAM memory chips, but can also be other types of memory chips, such as: FLASH, DDR, GDDR. The

memory devices

11, 12 communicate the same commands, addresses and data to each other over a bus that shares the substrate, with the commands, addresses and data communicated over the bus including, in this example, signals/CE, CLK, DQSM, VDD, VSS, DQ [7:0], and so on. Referring to fig. 3, the clock diagram is shown, which is an example of an OPI interface (OPI interface), and other embodiments may be compatible with other interfaces or include other types of signals, but is not limited thereto. The

memory devices

11 and 12 respectively have a memory space, wherein each memory cell (memory cell) is associated with an address, and a virtual memory space is provided for the outside world as a whole, and in this case, the size of the virtual memory space is ideally the sum of the memory spaces of the

memory devices

11 and 12. The most significant bit (most significant bit) value of the address is used as the device identification code of the

memory device

11, 12, for example, the most significant bit of the address is 1 to represent the memory device 11 corresponding to the upper half of the virtual memory space, and the most significant bit of the address is 0 to represent the memory device 12 corresponding to the lower half of the virtual memory space.

In the initial state, in step S100, the memory module 1 performs a normal operation. The

command decoders

111, 121 decode signals to cause the

memory devices

11, 12 to perform corresponding operations, such as: write data, read data, mode register commands, etc., and need not be limited thereto. The mode registers 112, 122 include a mode register space. One of the

mode registers

112, 122 is defined herein as the mode register table of FIG. 2, where x can represent any number, and the available mode register instructions generate the corresponding function of the mode register table by writing or reading the

mode registers

112, 122 according to MA [7:0] and MR [7:0 ].

In step S110, the memory module 1 merges the data to be refreshed into the

partial memory devices

11 and 12, such as: a portion of a memory device, for example: memory device 11, a portion of the memory space of a single memory device 11, or a combination of the above.

Next, in step S120, a portion of the

memory devices

11, 12 may be enabled to no longer retain data. In this example, a portion of

memory devices

11, 12 are enabled by writing a set of power setting codes to a mode register in

memory devices

11, 12, such as: suppose that eight bits of power setting code MRx [7:0] are written to the mode register MRx, x being an integer such as: MR12, where bits of the power setting code MRx [7:0] correspond to a particular memory device 11/12, a maximum of eight memory device modes can be set, such as: the first bit corresponds to memory device 11 and the second bit corresponds to memory device 12.

Next, in step S130, the hybrid power saving mode is entered. Referring to the mode register table of FIG. 2 and the clock diagram of FIG. 4, the SLP mode setting codes are written to the mode registers 112, 122 of the

memory devices

11, 12 corresponding to MR6 according to MA [7:0] and MR [7:0] to enter the hybrid power saving mode after the mode register command. The half sleep power down mode setting code is illustrated here as the four high bits of mode register MR6[7:0], the four low bits of mode register MR6[3:0] being reserved bits. In this example, the half sleep mode setting code can be, but is not limited to, binary 1111. In the hybrid power saving mode, which of the

memory devices

11, 12 is no longer holding data is determined according to the set of power setting codes written in step S120. For example, a bit of the power setting code of 0 indicates that the

corresponding memory device

11, 12 enters a half sleep mode (HS mode), and a bit of the power setting code of 1 indicates that the

corresponding memory device

11, 12 enters a power down mode (DPD mode). Taking power setting code 10000000 as an example, it represents that memory device 11 enters power-down mode and memory device 12 enters half sleep power-down mode. The

memory devices

11, 12 consume minimal power to retain data in the semi-sleep power-saving mode, which may be as low as 23 μ A for 64MB PSRAM. Data is no longer held in the power down mode and therefore the power consumption will be lower, perhaps as low as 5 μ A for 64MB PSRAM. Therefore, it is possible to flexibly set whether or not the

individual memory devices

11 and 12 consume the power holding data in the hybrid power saving mode, thereby reducing the power consumption of the entire memory module.

Then, in step S140, the hybrid power saving mode is exited according to the requirement. In this example, similar to the clock diagram shown in FIG. 4, after a short low of the CE signal, the mixed power saving mode is left after waiting for the same 200 μ s to 500 μ s, and the normal operation is returned.

Since the power setting code of the present embodiment is written with the half sleep power saving mode setting code and enters the half sleep power saving mode at the same time, the execution speed is fast.

Referring to the mode register table of FIG. 5, in another embodiment, unlike the previous embodiment, the step S120 and the step S130 are combined to enable a part of the memory devices to no longer hold data and enter the hybrid power saving mode to enable a part of the memory devices to no longer hold data and maintain the other memory devices to hold data. Other common parts are not described in detail herein. Referring to the clock diagram of FIG. 4, in the combination of steps S120 and S130, the power setting code and the half sleep mode setting code are written to the mode register of the memory device corresponding to MR6 according to MA [7:0] and MR [7:0] after the mode register command to enter the hybrid power saving mode. The half sleep power saving mode setting code is illustrated here as the four high bits of the mode register MR6[7:0] followed by the four low bit power setting code. In this example, the half sleep mode setting code can be, but is not limited to, binary 1111. The individual bits of the set of power setting codes may correspond to a particular memory device, such as: the first of the four lower bits corresponds to the first memory device and the second bit corresponds to the second memory device. And, in the hybrid power-saving mode, it is determined which of the memory devices are no longer to hold data according to the set of power setting codes. For example, a bit of the power setting code of 0 indicates that the corresponding memory device enters the half sleep power saving mode, and a bit of the power setting code of 1 indicates that the corresponding memory device enters the power down mode. Taking the power setting code 1000 as an example, it represents that the first memory device enters a power-down mode and the second to four memory devices enter a semi-sleep power-saving mode.

Please refer to fig. 6, which shows a schematic diagram of the command decoder 113 of the memory device according to an example of the present invention. The command decoder 113 may enable a portion of the memory devices to no longer hold data in conjunction with the step S120. The command decoder 113 is not limited to be provided in each of the

memory devices

11, 12 by way of example, and the command decoder 113 includes two data multiplexers, one of which selects a bit of the output power setting code according to the device identification code die _ id and the other of which selects either the half sleep power saving mode enter command HS _ command _ final or the power down mode enter command DPD _ command _ final according to the bit output thereby.

Referring to FIG. 7, a schematic diagram of a command decoder of a memory device according to another embodiment of the present invention is shown. The command decoder may enable a portion of the memory devices to no longer hold data in conjunction with the step S120. A fuse is respectively arranged in the memory devices, and an electrical characteristic of the fuse is changed by a laser process or a programming process so that the corresponding memory device can not retain data any more.

Through the embodiments, whether each memory device no longer holds data can be flexibly set, so that the partial memory devices which do not hold data correspond to at least two discontinuous memory blocks in the virtual memory space.

Please refer to fig. 1, fig. 8, fig. 9 and fig. 12. FIG. 8 is a diagram illustrating a mode register table of another exemplary mode register of the present invention, and FIG. 9 is a diagram illustrating a PASR mode setting code list of an exemplary mode register of the present invention. The present embodiment exemplifies a case where the PASR mode setting code is used as the power setting code. The power consumption management method of the present embodiment is similar to that of FIG. 12, however, step S120 enables a portion of the memory devices to no longer retain data by writing a set of power setting codes to a

mode register

112, 122 of the

memory device

11, 12, such as: assume that the three-bit PASR mode setting code shown in fig. 9 is written as the power setting code to the mode registers 112, 122 of the corresponding MR 4. According to FIG. 9, different PASR mode setting codes correspond to a specific refresh setting for the virtual memory space, such as: the PASR mode setting code of 001 would correspond to refreshing the lower half of the virtual memory space, i.e., corresponding to the memory device 12 of fig. 1. Therefore, at step S130, for convenience of illustration, the mode register instructions according to the previous example write the half sleep mode setting codes to the mode registers 112, 122 of the

memory devices

11, 12 corresponding to MR6 to enter the hybrid power saving mode according to MA [7:0] and MR [7:0 ]. At this time, as shown in the right two columns of fig. 9, whether to make the corresponding

specific memory device

11, 12 no longer hold data is determined according to the different values of the previously written power setting codes.

Please refer to fig. 10, fig. 11 and fig. 12. Fig. 10 is a diagram illustrating a PASR mode setting code list according to another embodiment of the present invention, and fig. 11 is a functional block diagram of a memory module according to another embodiment of the present invention. The present embodiment exemplifies a case where the PASR mode setting code is used as the power setting code. As shown in fig. 10, the memory module 2 of the present embodiment includes four

memory devices

11, 12, 13, and 14, each of the

memory devices

11, 12, 13, and 14 includes a

command decoder

111, 121, 131, and 141 and a plurality of mode registers 112, 122, 132, and 142. Similar to FIG. 1, the

memory devices

11, 12, 13, 14 share the same commands, addresses and data with each other over a bus of the substrate, which include signals/CE, CLK, DQSM, VDD, VSS, DQ [7:0] in this example. The

storage devices

11, 12, 13, 14 each have a storage space, wherein each storage unit is associated with an address, and the whole provides a virtual storage space to the outside, and for this example, the size of the virtual storage space is ideally the sum of the storage spaces of the

storage devices

11, 12, 13, 14. The most significant bit value of the address is used as the device identification code of the

memory devices

11, 12, 13, 14, for example, the most significant bit of the address is 1 to represent the

memory devices

11, 12 corresponding to the upper half of the virtual memory space, and the most significant bit of the address is 0 to represent the

memory devices

13, 14 corresponding to the lower half of the virtual memory space. The power consumption management method of the present embodiment is similar to that of FIG. 10, however, enabling a portion of the memory devices to no longer retain data at step S120 is accomplished by writing a set of power setting codes to a

mode register

112, 122, 132, 142 of the

memory devices

11, 12, 13, 14, such as: assume that the three-bit PASR mode setting code shown in fig. 10 is written as a power setting code to the mode registers 112, 122, 132, 142 of the corresponding MR 4. According to FIG. 10, different PASR mode setting codes correspond to a specific refresh setting for the virtual memory space, such as: the PASR mode setting code of 001 would correspond to refreshing the lower half of the virtual memory space, i.e., to the

memory devices

13, 14 of fig. 1. Therefore, at step S130, for convenience of illustration, the mode register instructions according to the previous example write the half sleep mode setting codes to the mode registers 112, 122, 132, 142 of the

memory devices

11, 12, 13, 14 corresponding to MR6 according to MA [7:0] and MR [7:0] to enter the hybrid power saving mode. At this time, as shown in the right four columns of fig. 10, it is determined whether the corresponding

specific memory device

11, 12, 13, 14 is enabled to no longer hold data according to the different values of the previously written power setting codes.

The foregoing describes a number of different embodiments in accordance with the present invention, in which the various features may be implemented in single or in various combinations. Therefore, the present invention is disclosed as illustrative embodiments which illustrate the principles of the present invention and should not be construed as limiting the invention to the disclosed embodiments. Furthermore, the foregoing description and the accompanying drawings are only illustrative of the present invention and are not intended to limit the present invention. Variations or combinations of other devices are possible without departing from the spirit and scope of the invention.

Claims

1. A method for managing power consumption of a memory module including a plurality of memory devices sharing a bus for communicating commands, addresses and data, the method comprising: the power consumption management method comprises the following steps:

enabling a part of the memory devices to no longer hold data and maintaining other memory devices to hold data; and

and entering a hybrid power-saving mode, so that the part of the memory devices does not retain data and other memory devices retain data.

2. The power consumption management method of claim 1, wherein: the step of enabling a portion of the memory devices to no longer retain data and maintaining another portion of the memory devices to retain data includes:

writing a set of power setting codes to a mode register in the memory devices; and

when entering the hybrid power saving mode, it is determined which of the memory devices are enabled to no longer hold data according to the set of power setting codes.

3. The power consumption management method of claim 2, wherein:

the set of power setting codes is a PASR mode setting code;

the storage devices provide a virtual storage space; and

and determining which of the memory devices are enabled to no longer hold data when entering a hybrid power saving mode according to the refresh setting of the written set of power setting codes to the virtual memory space.

4. The power consumption management method of claim 2, wherein:

each bit of the set of power setting codes corresponds to a particular one of the memory devices; and

when entering the hybrid power saving mode, whether the specific memory device is enabled to no longer hold data is determined according to the value of each bit of the written group of power setting codes.

5. The power consumption management method of claim 2, wherein:

writing the set of power setting codes and the half sleep mode setting codes into the mode register of the memory devices to enter a hybrid power saving mode, and determining which of the memory devices are enabled to no longer hold data according to the set of power setting codes.

6. The power consumption management method of claim 1, wherein: the step of enabling a portion of the memory devices to no longer retain data and maintaining another portion of the memory devices to retain data includes:

enabling a portion of the memory devices to no longer retain data through a fuse in the portion of the memory devices.

7. A kind of storage module, its characterized in that: the method comprises the following steps:

the memory devices share a bus for communicating commands, addresses and data and provide a virtual memory space, and are respectively provided with a command decoder and a plurality of mode registers, wherein the memory devices are configured to enable a part of the memory devices to no longer hold data and to maintain other memory devices to hold data and to enter a hybrid power-saving mode, so that a part of the memory devices to no longer hold data and to maintain other memory devices to hold data.

8. The memory module of claim 7, wherein:

the mode registers include a mode register space for storing a set of power setting codes written to determine which of the memory devices are enabled to no longer hold data according to the set of power setting codes when entering the hybrid power saving mode.

9. The memory module of claim 7, wherein: the memory devices are each provided with a fuse to change an electrical characteristic of the fuse to enable the portion of the memory devices to no longer retain data.

10. The memory module of claim 7, wherein: the portion of the memory device that no longer holds data corresponds to at least two non-contiguous blocks of the virtual memory space.