JPS6222293A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enlarge a writing address set up time during writing by detecting the change of a reading/writing external control (R/W) signal and making a writing circuit non-active for a fixed time. CONSTITUTION:When a chip is selected by a chip select control signal inverse CS and a signal R/W is changed from a reading to a writing, this is detected and a transition circuit and a clock generator circuit 3 output a prohibit clock phiWE. This clock phiWE becomes a prohibit control signal and a writing circuit 1 is not activated for a fixed time through a writing control circuit 4. Accordingly, the set up time of a writing address by a signal inversion CS, R/W becomes the same and the set up time becomes a fully spare time and an erroneous writing or the like is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a write circuit for a semiconductor memory device, and more particularly to a write circuit for a random access type static memory.

[Summary of the invention]

The present invention utilizes a read/write external control signal (hereinafter Rμ
In a random access type semiconductor memory device, in which information is read and written to a static memory cell by a change in the read/write external control signal, that is, the semiconductor memory device changes from a read state to a write state. When the clock is activated, a change in this external signal is detected and an internal control signal is generated as a clock, and while this internal control signal is active, the write circuit is inactive, and the external signal is not activated during that period. By inhibiting the writing of input data to the memory cell and retaining the information of the memory cell in the read state cycle, it is possible to secure an address setup time to be described later from the R door signal.

[Prior art]

Random access method ■Read/write memory (R
AM), one of the AC electrical customizations for the write cycle is the address set-up time iAB from the Rβ signal as shown in Figure 3, that is, the write cycle twc.
The timing for setting the ψ signal to the write state in response to a change in the address signal is defined therein. This tA
Usually, at worst, fi is in a state where the ψ signal is written at the same time as the address signal changes (write at wLw level, 'III'
The ψ signal is actually put into the write state before the address signal changes.

Figure 4 shows a conventional write circuit, where 1 is a write circuit, 2 is a chip control circuit using CS and R/W signals, 3 is a convex transition detection circuit, 4 is a write control circuit, and 5 is a column selection gate. , 6 is a memory cell, and 7 is a load circuit. In order to obtain the timing as shown in Fig. 3, by delaying the internal write signal wzl even when the external Ri signal is in the write state as shown in Fig. 4, the input data is not propagated to the memory cell and the write start timing is adjusted. is delayed.

[Problems and Objects to be Solved by the Invention] The internal write signal WE shown above is delayed by the rise of the chip select control signal, that is, by the change of the semiconductor memory device from the standby state to the operating state, and is removed from the write circuit. The start time of writing to memory cells is delayed. This causes a difference between the set-up time from the R/W signal and the set-up time from the surface signal, and the set-up time from the R/W signal changes when the ψ signal changes to the write state at the same time as the address signal changes. There was a problem in that there was insufficient margin for the standard value.

The present invention solves this problem, and its purpose is to control ψ,
It is an object of the present invention to provide a semiconductor memory device in which the address set-up time from an OB signal can be made to be approximately the same, and can have a margin with respect to the value of the above-mentioned standard.

[Means for solving problems]

The semiconductor memory device of the present invention has static memory cells arranged in a matrix, and when writing and reading information to and from these memory cells, the read and write circuits can be controlled to an operating state by a ψ signal. In a semiconductor memory device equipped with a circuit, a transition detection circuit detects a change in an R/W@ number from a read state to a write state, a control circuit receives a detection signal of the detection circuit and generates an internal control signal; A special feature is that the write circuit is inactivated for a certain period of time by a control signal from this control circuit.

[Effect]

By adopting the above circuit configuration, the present invention operates the transition detection circuit when the Rβ signal shifts from the read state to the write state, in the same way as when the crystal signal shifts from the standby state to the operating state. Write external data to memory cells with the period write circuit inactive? By delaying the start of Q, sufficient time can be secured for setup from the C8 and ψ signals.

〔Example〕

The μ sewage invention will be described in detail based on examples.

Figure 1 is a circuit diagram showing an embodiment of the present invention. 1 is a write circuit, to which an external write-in terminal Djs is connected as an input, a pair of data lines, D1&: as an output, 5
It is connected to the pair of bit lines BL and BL through the column selection gate of , and a crystal is connected to the first stage circuit to inhibit writing in the standby state. 2
is a chip control circuit using as, R7W signals, and R
The operation of the chip is controlled by the input state of the /W signal. 3 is a transition detection circuit for the OB and ψ signals and a clock generation circuit, which detects when as moves from a standby state to an operating state and when the ψ signal moves from a read state to a write state, and generates a clock. It is a circuit. 4 is a write control plane path, to which the clock output φWE of the clock generation circuit 3 is connected as an input, and the internal write control signal WE is connected to the final stage circuit of the write circuit 1. 6 is 1 in the memory cell array
It is a memory cell, and the word line WL and the above BL,
BI is connected. Reference numeral 7 designates a load circuit connected to the power supply voltage VDD and each of the pair of bit lines BL, rr.

The entire operation of the circuit of the above actual tJO7A example will be explained. FIG. 2 shows the operating waveforms of the circuit shown in FIG.

When the semiconductor memory device is in operation, the Rμ signal is changed from the read state to the write state, that is, from 'H level to "
- When the write control circuit is moved to the label, the write control circuit becomes operational through the chip control circuit. Then, the internal write signal wm becomes activated (IH level). However, at the same time, the transition detection circuit 3 operates, and the clock signal generation circuit operates to generate the clock signal φwz2. During this period when the a-link signal φwz is being generated, the write control circuit 4 is inactivated and wg is at the ILI level.

As a result, the information input from the external data input terminal Din does not appear on the data line D for a certain period of time, and the start time of writing into the memory cell is delayed.
After φwz is cut off and 7K becomes 1H', information is propagated to the DD and writing to the memory cell is started. By delaying the start time of writing to a memory cell by tC1l, the R/w signal can be changed from the read state to the write state sufficiently quickly in response to the input of the address signal.
Data can be written to the specified address without writing errors.

A similar circuit operation occurs when the CB changes from a standby state to a write operation state.

[Invention Q effect]

As described above, according to the present invention, the address set-up time from the cs and Ft/W signals is set to the same value to meet the standard, that is, the i and R/W signals are brought into the write state at the same time as the external address signal changes. Semiconductor storage device with sufficient margin for ? can be provided.

[Brief explanation of drawings]

FIG. 1 is a bottom circuit diagram of the present invention.゛Figure 2 is a timing diagram of the oath operation in Figure 1. FIG. 3 is a timing diagram of the conventional compliment operation. FIG. 4 is a conventional writing circuit diagram. 1...Write circuit 2...Chip control circuit 3...Transition detection circuit and clock generation circuit 4...Write control circuit 5...Fist column selection gate 6-#-Memory self...Load circuit or higher

Claims (1)

[Claims] A semiconductor memory device comprising static memory cells arranged in a matrix and a circuit that can control reading and writing using a read/write external control signal to write and read information to and from the memory cells. a transition detection circuit that detects a change in the read/write external control signal from a read state to a write state; a control circuit that receives a detection signal from the detection circuit and generates an internal control signal; A semiconductor memory device characterized in that the write circuit is inactivated for a certain period of time in response to a control signal.