CN101494090A

CN101494090A - Memory access control method

Info

Publication number: CN101494090A
Application number: CNA2008100046940A
Authority: CN
Inventors: 宁树梁; 刘维理
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2008-01-21
Filing date: 2008-01-21
Publication date: 2009-07-29
Anticipated expiration: 2028-01-21
Also published as: CN101494090B

Abstract

The invention provides a memory control method. A read write command is decoded to generate a mode memory setup signal; when the mode memory setup signal is enabled, a flip-latch outputs a memory vault selection signal; afterwards, the memory vault selection signal is decoded to generate a register selection signal. The register selection signal can select a register so as to write an address signal into the selected register. And the value of a certain register can be used for determining whether an error checking function is enabled. Therefore, the next-generation memory framework which supports the CRC function can be compatible with the original memory framework.

Description

Memory access control method

Technical field

The invention relates to a kind of memory access control method, and particularly relevant for a kind of determine whether carry out Cyclical Redundancy Check (cyclic redundancy check, memory access control method CRC).

Background technology

In communication system or computer system, (cyclic redundancy check CRC) improves the bug check ability can to utilize Cyclical Redundancy Check.After data transmission or data storing, CRC can be used for checking whether make a mistake in data transmission procedure.In data transmission procedure, receiving/send out both sides all needs to carry out the CRC computing, by a certain side's comparison CRC operation result that both sides calculated, can learn whether received data are wrong then.

Along with the transfer speed of data of computer system is more and more faster, existing memory architecture can't ensure the data transmission accuracy of storer.Therefore, in follow-on memory architecture, can use the crc error audit function, to guarantee the correct of data transmission in storage access.But the legacy memory framework also can't be supported the crc error audit function, makes and supports the memory architecture of future generation of crc error audit function can't upwards be compatible to existing memory architecture.

Just, if in same computer system, use the memory architecture of future generation of supporting the crc error audit function and the existing memory architecture that can't support the crc error audit function simultaneously, must close the CRC function of memory architecture of future generation, otherwise System Operation has problem.

On the other hand,, preferably can start the CRC function, to increase system effectiveness if in same computer system, all use the memory architecture of future generation that to support the crc error audit function.

Summary of the invention

The present invention is a kind of memory access control method, and the storer that contains the CRC function in order to solution can't upwards be compatible to the problem of old memory transfer framework.

One of example of the present invention provides a kind of memory control methods, comprising: the read write command of decoding is deposited setting signal to produce a pattern; When this pattern was deposited setting signal and is activation, the data base of decoding was selected signal, to produce a register selection signal; According to this register selection signal, from a plurality of registers, select at least one register, and an address signal is written to selecteed this register; And according to the value of selecteed this register, whether to determine activation one error checking function.

Comprehensively the above when the present invention can't support the CRC function at old memory transfer framework, can close the CRC unit, makes storer can upwards be compatible to old memory transfer framework.Or when the memory transfer framework is supported the CRC function, can open the CRC unit, keep due system effectiveness.

Description of drawings

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:

Fig. 1 is the rough schematic view of storer 100.

Fig. 2 is the control calcspar according to storer 100 inside of the embodiment of the invention.

Fig. 3 is instruction demoder 220 sequential synoptic diagram.

The main element symbol description:

100: storer

210: receiving element

220: instruction decoder

230: latch

240,250: demoder

260-0,260-1: group of registers

260-1a: register

The 270:CRC unit

ADD_BUS: address bus

ADD＜0:12 〉: address signal

BS＜0:1 〉: data base is selected signal

: rwo address strobe signals

CMD_BUS: instruction bus

CLK: clock signal

CRC_EN:CRC function enable signal

CRC_V: error checking function operation result

DQ: data bus

MRS: pattern is deposited setting signal

: column address gating signal

SEL, SELp0, SELp1: register selection signal

VSS, VDD: power supply

: write enable signal

CS: chip enable signal

Embodiment

In embodiments of the present invention, disclose a kind of memory control methods and memory architecture, can determine whether to start/close the CRC function of memory architecture of future generation according to circumstances.Preferably, when all memory module in the system all can be supported the CRC function, just start the CRC function, to increase system effectiveness.That is to say,, make mistakes avoiding as long as when having a memory module can not support the CRC function in the system, had better not start the CRC function.

Please refer to Fig. 1, the rough schematic view of its display-memory 100, certainly, storer 100 also has other I/O pins, but is simplified illustration, and other I/O pins do not demonstrate.

As shown in Figure 1, the I/O pin of storer 100 comprises at least: address pin, but the address signal on its receiver address bus ADD_BUS; The instruction pin, it can receive instruction bus CMD_BUS and (comprise

,

And CS) command signal on; Two power pins receive power vd D and VSS respectively; The clock pulse pin receives clock signal CLK; And the data pin, receive data bus DQ.

Storer 100 will determine whether activation error checking function CRC according to received address signal and instruction signal.Under error checking function CRC was not enabled De Qing Indistinct, data bus DQ can output error audit function operation result CRC_V; Under the situation that error checking function CRC is enabled, data bus DQ then can output error audit function operation result CRC_V.

Fig. 2 is the storer 100 internal control calcspars according to the embodiment of the invention, and it can determine whether start the CRC function.At this, with address signal ADD＜0:12〉be 13, and data base is selected signal BS＜0:1〉be 2 and be the example explanation.Certainly, present embodiment is not limited to this.

Receiving element 210 is accepted address signal on clock signal CLK, the address bus ADD_BUS and the command signal on the instruction bus CMD_BUS.Particularly, receiving element 210 will decode address signal ADD＜0:12 by address bus ADD_BUS〉select signal BS＜0:1 with data base 〉.In addition, receiving element 210 can be with the signal decoding arow location gating signal on the instruction bus CMD_BUS

(row address strobe), rwo address strobe signals

(column address strobe), write activation | signal

(write enable) and chip enable signal CS (chip selected).

220 pairs of column address gating signals of instruction decoder

, rwo address strobe signals

, write enable signal WE and chip enable signal CS decodes, to produce a plurality of signals, one of them signal is called pattern and deposits setting signal MRS.This pattern is deposited setting signal MRS and is used to activation latch 230.Please refer to Fig. 3, its display column address gating signal

, rwo address strobe signals

, write enable signal

Deposit the sequential chart of setting signal MRS with pattern.As shown in Figure 3, work as column address gating signal

, rwo address strobe signals

With write enable signal

Be all logic low and chip enable signal CS when being logic high, it is activation that pattern is deposited setting signal MRS.Certainly, present embodiment is not limited to this.

Latch 230 more can receiver address signal ADD＜0:12 〉, data base selects signal BS＜0:1.Such as, when pattern is deposited setting signal MRS and is activation, address signal ADD＜0:12 that latch 230 outputs are latched〉and data base select signal BS＜0:1.

Demoder 240 is selected signal BS＜0:1 with data base〉be decoded into register selection signal SEL＜0:3 〉.

Demoder 250 is with register selection signal SEL＜0:3〉be decoded into register selection signal SELp0, SELp1 ...Those register selection signal SELp0, SELp1 ... can be used for activation group of registers 260-0,260-1 ....

At this, comprise that with group of registers 13 registers are that example is done explanation.Address signal ADD＜0:12〉can be written into the group of registers that is enabled.Such as, when group of registers 260-1 is enabled, address signal ADD＜0:12〉can write 13 interior registers of group of registers 260-1 so far.

Whether in the present embodiment, the output valve of a certain register can be treated as CRC function enable signal CRC_EN, be enabled with control CRC function.This register is such as depositing setting (MRS, mode register setting) register 260-1a for the pattern in the group of registers 260-1.

CRC unit 270 can receive data DQ, and it is carried out the CRC computing, to produce error checking function operation result CRC_V.When this CRC function enable signal CRC_EN is activation, but activation CRC unit 270 produces error checking function operation result CRC_V to make CRC unit 270.Relative, when this CRC function enable signal CRC_EN is anergy, but anergy CRC unit 270 does not produce error checking function operation result CRC_V to make CRC unit 270.Certainly, CRC function enable signal CRC_EN is other I/O circuit in the writable control storage 100 also, can be not wrong with the data output that makes storer 100.

The embodiment of the invention can be applicable to high speed/big data quantity storer (such as, DDR4) in, be compatible to old memory architecture to make it.

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.

Claims

1. memory control methods comprises:

The read write command of decoding is deposited setting signal to produce a pattern;

When this pattern was deposited setting signal and is activation, the data base of decoding was selected signal, to produce a register selection signal;

According to this register selection signal, from a plurality of registers, select at least one register, and an address signal is written to selecteed this register; And

According to the value of selecteed this register, whether to determine activation one error checking function.

2. memory control methods as claimed in claim 1 is characterized in that also comprising:

Decode signal on the address bus is selected signal to produce this address signal and this data base.

3. memory control methods as claimed in claim 1 or 2 is characterized in that also comprising:

Decode signal on the instruction bus is to produce this read write command.

4. memory control methods as claimed in claim 3 is characterized in that, this read write command comprises at least: a column address gating signal, a rwo address strobe signals, a chip enable signal and write enable signal.

5. memory control methods as claimed in claim 4 is characterized in that, when this column address gating signal, this rwo address strobe signals, this chip enable signal and this write enable signal and be all logic high, it was activation that this pattern is deposited setting signal.

6. memory control methods as claimed in claim 1 is characterized in that also comprising:

Latch this address signal and this data base and select signal; And

When this pattern is deposited setting signal and is activation, this address signal that output is latched and this data base selection signal.

7. memory control methods as claimed in claim 5 is characterized in that also comprising:

Latch this address signal and this data base and select signal; And