CN100369016C - A controller for synchronous dynamic random access memory - Google Patents

Abstract

The invention belongs to the technical field of space electronics. Specifically, the invention relates to a controller chip of a synchronous dynamic random access memory, including a chip selection and address latch circuit, and a synchronous dynamic random access memory data bus interface circuit; its characteristics In that, it also includes an instruction decoding and refreshing control unit; the instruction decoding and refreshing control unit generates the control signals required by the synchronous dynamic random access memory array according to the received control CPU instruction; the chip selection and The address latch circuit generates chip select, clock enable and address signals required by the synchronous dynamic random access memory array according to the received instructions of the control CPU. The invention has the advantages of: 1) it is suitable for super-large-capacity storage; 2) it has higher reliability and is more suitable for the space radiation environment; 3) it is simple and flexible to implement.

Description

A controller for synchronous dynamic random access memory

technical field

The invention belongs to the technical field of space electronics, and in particular, the invention relates to a software-controlled synchronous dynamic random access memory controller chip, which is used for synchronous dynamic random access memory array data of a space vehicle CPU interface Store and playback and data retention control.

Background technique

Space vehicles generate a large amount of data during their missions. Due to the time and bandwidth limitations of the aircraft-ground data link, these data usually need to be temporarily stored in a large-capacity memory and played back down when the aircraft passes the station. The storage medium of the large-capacity memory usually adopts a magnetic medium or a solid-state storage medium, wherein the solid-state storage medium mainly includes a synchronous dynamic random access memory (SDRAM) and a flash memory (FLASH memory). SDRAM has the advantages of simple mechanical structure, high reliability, random access to data, and fast data access speed. However, due to the inherent characteristics of synchronous dynamic random access memory itself that requires dynamic refresh to keep data from being lost, there is also a refresh control The shortcomings of complexity and high power consumption require a special controller to control. The existing SDRAM controllers generally have the following types: one is a dedicated SDRAM interface chip, which has a fixed interface and limited access capacity, which cannot meet the requirements of the aircraft for a large memory capacity; the other is a chip with an SDRAM interface. DSP, such as the TMS320C6000 series, has the disadvantage of limited capacity and is not easy to expand; there is also an FPGA-based SDRAM controller designed for various applications, such as the SDRAM controller IP core provided by Xilinx, but these SDRAM controllers have the same In addition to the limited capacity, the state machine is often used as the core of its controller. The single event effect in the space radiation environment may cause the wrong action of the state machine, so that the SDRAM memory chip enters an error state, resulting in data loss.

Contents of the invention

The object of the present invention is to provide a kind of synchronous dynamic random access memory controller (being SDRAM controller) based on software control that is suitable for space vehicle use, this SDRAM controller can store data to solid-state memory array under software control In the storage unit of any specified address, the data in the storage unit of any specified address can be read out, and at the same time, the software can be used to independently control each SDRAM chip to enter the automatic refresh (AUTOREFRESH) mode.

In order to realize the above-mentioned object of the invention, the synchronous dynamic random access memory controller based on software control provided by the present invention comprises a chip selection and address latch circuit, a synchronous dynamic random access memory data bus interface circuit; it is characterized in that it also includes an instruction Decoding and refresh control unit, wherein the instruction decoding and refresh control unit, chip selection and address latch circuit are connected with the control bus and data bus of the CPU for control; The instructions of the CPU generate chip selection, clock enable, and address signals required by the synchronous dynamic random access memory array; the instruction decoding and refresh control unit generates synchronous dynamic random access according to the received instructions of the control CPU The control signal required by the memory array; the synchronous dynamic random access memory data bus interface circuit is connected with the CPU data bus, the data bus of the synchronous dynamic random access memory array and the instruction decoding and refresh control unit, thereby completing the CPU and the synchronous dynamic random access memory Data exchange between access memory arrays and automatic refresh function of synchronous dynamic random access memory.

The control signals generated by the instruction decoding and refresh control unit include RAS, CAS, WE, and DQM signals required for synchronizing the DRAM array.

The instruction decoding and refreshing control unit also produces an address output control signal, which controls the chip selection and address latch circuit to output row address or column address; the instruction decoding and refreshing control unit also produces a data input and output control signal, and the signal Control the data flow direction of the synchronous dynamic random access memory data bus interface circuit.

The instruction decoding and refresh control unit will automatically generate an automatic refresh instruction to periodically refresh the synchronous dynamic random access memory to keep the data storage correct.

The controller can support memory arrays with a maximum capacity of 4096G bits.

The controller circuit is all realized by hardware and written into a chip of FPGA (Field Programmable Gate Array).

Compared with the prior art, the present invention has the advantages that: 1) it is suitable for ultra-large-capacity memory, and the capacity can be infinitely expanded by expanding the "chip select and address latch", which can fully meet the needs of space vehicles for large-capacity memory. capacity requirements. 2) The control method of sending instructions by software and decoding by hardware is more reliable than the automatic state conversion control method of the finite state machine, and is more suitable for the space radiation environment. 3) The implementation is simple and flexible, and can be implemented with a single FPGA according to system requirements and other interface circuits or codec circuits, thereby greatly improving the flexibility of the system and reducing the volume and weight of the whole machine.

Description of drawings

Fig. 1 is the functional block diagram of the SDRAM controller that the present invention provides;

Fig. 2 is a block diagram of instruction decoding and refresh control unit;

Figure 3 is a timing diagram of SDRAM read and write;

The meanings of the symbols in the figure are as follows:

Ra: a row address Ca: a column address BS: block selection Qa: read column a data

Db: data written to column b address

tSS: Input setup time tSH: Input hold time tCCD: Delay between column addresses tRAS: Row activation time

tRC: row cycle time tRP: row precharge time tRCD: row activation to column address delay tCC: clock cycle

tSAC: clock to valid output delay

Fig. 4 is the SDRAM reading and writing waveform diagram obtained by the actual simulation of the present invention.

Detailed ways

In order to further illustrate the purpose and characteristics of the present invention, the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, wherein Fig. 1 is a functional block diagram of the present invention, Fig. 2 is a block diagram of instruction decoding and refresh control unit, and Fig. 3 is SDRAM read and write timing diagram. Fig. 4 is the SDRAM reading and writing wave form diagram (what adopted is software emulation, emulation platform is Modelsim) of the present invention's actual emulation gained. Table 1 is the truth table of external commands and control signals required for SDRAM work.

As shown in Fig. 1, the present invention is made up of chip selection and address latch circuit, instruction decoding and refresh control unit, SDRAM data bus interface circuit three parts, wherein chip selection and address latch circuit, instruction decoding and refresh control unit Both are connected to the control bus and data bus of the control CPU, and the chip select and address latch circuits generate chip select (CS), clock enable (CKE), Bank and address signals required by the SDRAM memory array, and instruction decoding and refreshing The control unit generates the control signals (RAS, CAS, WE, DQM) required by the SDRAM memory array. The SDRAM data bus interface circuit is connected with the CPU data bus, the data bus of the SDRAM memory array, and the command decoding and refresh control unit, thereby completing the data exchange between the CPU and the SDRAM memory array and the automatic refresh function of the SDRAM memory. The controller in this embodiment can support a memory array with a maximum capacity of 4096G bits.

SDRAM completes read, write and refresh operations by relying on the different timing and addresses of its input control signals CLOCK, CKE, CS, RAS, CAS, WE, DQM, and the corresponding addresses and data on the data bus. Referring to Fig. 3, taking reading a data from a certain memory unit as an example, it is necessary to give the row address effective instruction (CKE=HIGH, CSn=LOW, RAS=LOW, CAS=HIGH, WE=HIGH) and the corresponding row address (ADDR , A10/AP) and the block (Bank) address (BA), give the read command (CKE=HIGH, CSn=LOW, RAS=HIGH, CAS=LOW, WE=HIGH) after a certain time interval (several clock cycles) And the corresponding column address (ADDR, A10/AP), when CAS Latency=3, after 3 clock cycles, the data of this address will appear on the data bus (DQ). Similarly, write operations and memory initialization, refresh, pre-charging, etc. require the external SDRAM controller to give corresponding command signals in accordance with the provisions of Table 1.

Order CKEn-1 CKEn CS RAS CAS we DQM BA0,1 A10/AP A11, A9～0 Mode register setting h x L L L L x Opcode Auto Refresh h h L L L h V x line activation h x L L h h x V line address read Auto precharge off h x L h L h x V L column address Auto precharge on h Write Auto precharge off h x L h L L x V L column address Auto precharge on h burst end h x L h h L x x precharge block selection h x L L h L x V L x all blocks x h no-op instruction h x h x x x x x L h h h

Table 1

In Table 1, V=valid X=don’t matter H=logic high level L=logic low level

According to the instructions issued by the computer software, the present invention uses the instruction decoding and refresh control unit to perform instruction decoding, and the output signal end of this unit generates corresponding timing RAS, CAS, WE, DQM signals, and at the same time, the instruction decoding and refresh control unit It also controls the chip select and address latch unit to generate corresponding CKE, CS, BA and address (ADDR) signals, and controls the SDRAM data bus interface unit to write the data on the CPU data bus into the SDRAM memory or transfer the data from the SDRAM memory read from the array onto the CPU data bus. While completing the read and write sequences, the instruction decoding and refresh control unit in Figure 1 will automatically generate an automatic refresh instruction to refresh the SDRAM memory regularly to keep the data stored correctly.

Fig. 2 is an internal functional block diagram of the instruction decoding and refresh control unit. The instruction decoding unit receives the instructions of the CPU control bus and data bus (all instructions are listed in Table 1), and sends the signals Y1, Y2, Y3 and Y4, Y5, and Y6 after decoding the instructions to the WE and DQM signal generating units respectively and RAS and CAS signal generation unit, and also generate refresh start command to start refresh and pre-charge command generation unit to generate refresh (REFRESH) and pre-charge command signal PRG, WE and DQM signal generation unit and RAS and CAS signal generation unit to generate compliance SDRAM memory requires sequential RAS, CAS, WE, DQM signals. At the same time, an address output control signal will be generated to control whether to output a row address or a column address, and a data input and output control signal will be generated to control the data flow.

In this embodiment, the chip select and address latch unit is mainly composed of a 6-64 decoder, two 12-bit latches and a 12-bit two-to-one multiplexer. The 6-64 decoder generates corresponding CS, Bank and CKE signals according to software instructions; two 12-bit latches respectively latch the row address and column address, and these two address signals are sent to the 12-bit two-to-one multi-way selection The multiplexer outputs the row address or column address to the address bus of the SDRAM array under the control of the address output control signal.

The SDRAM data bus interface unit is mainly composed of a 16-bit tri-state gate. The control terminal of the tri-state gate receives the instruction decoding and refreshes the data input and output signals generated by the control unit to control the writing of data on the CPU data bus to the SDRAM memory or read data from the SDRAM memory array to the CPU data bus.

This embodiment can support a memory array with a maximum capacity of 4096G bits. It is worth noting that the capacity of the memory array can be further expanded by expanding the chip selection and address latch circuits in the present invention.

The controller circuits in this embodiment are all implemented by hardware, and finally written into an FPGA (Field Programmable Gate Array) chip.

Claims (6)

1. a controller of synchronous dynamic random access memory, comprising chip select and address latch circuit, synchronous dynamic random access memory data bus interface circuit; It is characterized in that, also comprises instruction decoding and refresh control unit, described The instruction decoding and refresh control unit, chip select and address latch circuit are connected with the control bus and data bus of the control CPU; The chip select and address latch circuit generates chip select, clock enable, and address signals required by the synchronous dynamic random access memory array according to the received control instruction of the CPU; The instruction decoding and refresh control unit generates control signals required for synchronous dynamic random access memory arrays according to the received control instructions of the CPU; The synchronous dynamic random access memory data bus interface circuit is connected with the CPU data bus, the data bus of the synchronous dynamic random access memory array and the instruction decoding and refreshing control unit. 2. by the controller of synchronous dynamic random access memory according to claim 1, it is characterized in that, the control signal that described instruction decoding and refresh control unit produces comprises the required RAS, CAS of synchronous dynamic random access memory array , WE, DQM signals. 3. by the controller of synchronous dynamic random access memory according to claim 1, it is characterized in that, described instruction decoding and refresh control unit also produce address output control signal, and this signal controls chip selection and address latch circuit output The row address or column address; instruction decoding and refresh control unit also generates data input and output control signals, which control the data flow direction of the synchronous dynamic random access memory data bus interface circuit. 4. by the controller of synchronous dynamic random access memory according to claim 3, it is characterized in that, described instruction decoding and refresh control unit can produce automatic refresh instruction automatically, synchronous dynamic random access memory is periodically refreshed, To keep the data stored correctly. 5. The controller of the synchronous dynamic random access memory according to claim 1, wherein the controller can support a memory array with a maximum capacity of 4096 G bits. 6. by the controller of the described synchronous dynamic random access memory of claim 1, it is characterized in that, described controller circuit is all realized with hardware, writes a slice of FPGA chip.

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