CN100369016C

CN100369016C - Controller synchronous dynamic random access storage

Info

Publication number: CN100369016C
Application number: CNB2005100870161A
Authority: CN
Inventors: 陈斌; 刘大海; 沈卫华; 陈晓敏; 孙辉先
Original assignee: National Space Science Center of CAS
Current assignee: National Space Science Center of CAS
Priority date: 2005-07-22
Filing date: 2005-07-22
Publication date: 2008-02-13
Anticipated expiration: 2025-07-22
Also published as: CN1900918A

Abstract

The present invention belongs to the field of space electronic technology, and is especially one controller chip for synchronous DRAM. The controller chip includes a chip selecting and address latching circuit and a synchronous DRAM data bus interface circuit, as well as a command decoding and refreshing control unit. The command decoding and refreshing control unit generates the control signal for the synchronous DRAM based on the received control command from the CPU; and the chip selecting and address latching circuit generates the chip selecting signal, the clock enabling signal and the address signal for the synchronous DRAM based on the received control command from the CPU. The present invention has the advantages of suitability for super bulk memory, high reliability suitable for space application, and being simple and flexible.

Description

A kind of controller of Synchronous Dynamic Random Access Memory

Technical field

The invention belongs to the space electronic technical field, specifically, the present invention relates to a kind of Synchronous Dynamic Random Access Memory controller chip based on software control, this chip is used for data storage and playback and the data retentive control with the Synchronous Dynamic Random Access Memory array of spacecraft cpu i/f.

Background technology

Spacecraft produces mass data in it executes the task process, these data need be kept in descending playback when aircraft misses the stop usually owing to be subjected to aircraft---the time and the bandwidth constraints of ground data link by mass storage.The storage medium of mass storage adopts magnetic medium or solid storage medium usually, wherein mainly contains Synchronous Dynamic Random Access Memory storer (SDRAM) and flash memory (FLASH storer) in the solid storage medium.Advantage such as SDRAM has, and physical construction is simple, reliability is high, but data random access, data access speed are fast, but because the intrinsic characteristic that needs dynamic refresh could keep data not lose of Synchronous Dynamic Random Access Memory itself, also there are refresh control complexity, shortcoming that power consumption is bigger, need special controller to control.Existing sdram controller generally has following several: a kind of is special-purpose sdram interface chip, and the sort controller interface is fixed, and the visit finite capacity can not satisfy the requirement of aircraft for the storer vast capacity; Another kind is the DSP that has sdram interface, TMS320C6000 series for example, and its shortcoming is a finite capacity, is difficult for expansion; Also having a kind of is the sdram controller based on FPGA at various Application Design, the sdram controller IP kernel that provides as Xilinx company, but these sdram controllers are except that same finite capacity, also often adopt the core of state machine as its controller, do not consider that single particle effect under the space radiation environment may cause the malfunction of state machine, thereby make the SDRAM storage chip enter error condition, cause loss of data.

Summary of the invention

The object of the present invention is to provide and a kind ofly be suitable for that spacecraft uses, Synchronous Dynamic Random Access Memory controller (being sdram controller) based on software control, this sdram controller can be under software control with data storage in the storage unit of any assigned address of solid-state memory array, and the data in the storage unit of any assigned address can be read, can utilize simultaneously software to control each SDRAM chip separately and enter automatically and refresh (AUTOREFRESH) pattern.

For achieving the above object, the Synchronous Dynamic Random Access Memory controller based on software control provided by the invention comprises sheet choosing and address latch circuit, Synchronous Dynamic Random Access Memory data bus interface circuit; It is characterized in that, also comprise instruction decode and refresh control unit, wherein instruction decode and refresh control unit, sheet choosing and address latch circuit link to each other with the control bus and the data bus of control with CPU; Described choosing and address latch circuit be according to the control that the receives instruction with CPU, produces that Synchronous Dynamic Random Access Memory array required sheet choosing, clock enable, address signal; Described instruction decode and refresh control unit produce the required control signal of Synchronous Dynamic Random Access Memory array according to the instruction of the control that receives with CPU; The data bus of Synchronous Dynamic Random Access Memory data bus interface circuit and cpu data bus, Synchronous Dynamic Random Access Memory array and instruction decode and refresh control unit link to each other, thereby finish the exchanges data between CPU and Synchronous Dynamic Random Access Memory array and the automatic refresh function of Synchronous Dynamic Random Access Memory.

The control signal that described instruction decode and refresh control unit produce comprises the required RAS of Synchronous Dynamic Random Access Memory array, CAS, WE, DQM signal.

Described instruction decode and refresh control unit also produce address output control signal, this signal controlling sheet choosing and address latch circuit output row address or column address; Instruction decode and refresh control unit also produce the data input/output control signal, the data flow of this signal controlling Synchronous Dynamic Random Access Memory data bus interface circuit.

Described instruction decode and refresh control unit can produce automatic refreshing instruction automatically, and Synchronous Dynamic Random Access Memory is carried out periodic refresh, to keep the correct of data storage.

Described controller can be supported the memory array of capacity maximum to 4096G bits.

Described controller circuitry is all realized with hardware, is write a slice FPGA (field programmable gate array) chip.

Compared with prior art, the invention has the advantages that: 1) be applicable to ultra-high capacity storage, by the expansion to " sheet choosing and address latch ", capacity can infinitely enlarge, and can satisfy the capacity requirement of spacecraft for mass storage fully.2) adopt software to send instructions, the control mode of hardware decoding, the automatic conversion and control mode of the state of the finite state machine of comparing, reliability is higher, more is applicable to space radiation environment.3) realize simple and flexible, can realize with a slice FPGA according to circuit such as system's needs and other interface circuits or coders, thus the dirigibility that improves system greatly, the volume and weight of reduction complete machine.

Description of drawings

Fig. 1 is the theory diagram of sdram controller provided by the invention;

Fig. 2 is instruction decode and refresh control unit block diagram;

Fig. 3 is SDRAM read-write sequence figure;

The meaning of each symbolic representation is as follows among the figure,

Ra:a every trade address Ca:a row column address BS: piece is selected Qa: a column data of reading

Db: the data that write the b column address

TSS: input tSH Time Created: input retention time tCCD: tRAS delays time between column address: the line activating time

TRC: line period time tRP: line precharge time tRCD: line activating arrives column address time delay tCC: the clock period

TSAC: clock is to effectively output time-delay

Fig. 4 is the SDRAM read-write oscillogram of actual emulation gained of the present invention.

Embodiment

For further specifying purpose of the present invention and feature, below in conjunction with drawings and the specific embodiments the present invention is made a detailed description, wherein Fig. 1 is a theory diagram of the present invention, and Fig. 2 is instruction decode and refresh control unit block diagram, and Fig. 3 is SDRAM read-write sequence figure.Fig. 4 is actual emulation gained SDRAM of the present invention read-write oscillogram (employing be software emulation, emulation platform is Modelsim).Table 1 is required external command and control signal truth table for SDRAM works.

As shown in Figure 1, the present invention is made up of sheet choosing and address latch circuit, instruction decode and refresh control unit, SDRAM data bus interface circuit three parts, wherein sheet choosing and address latch circuit, instruction decode and refresh control unit all link to each other with data bus with the control bus of control with CPU, sheet choosing and address latch circuit produce SDRAM memory array required sheet choosing (CS), clock and enable (CKE), Bank and address signal, and instruction decode and refresh control unit produce the required control signal (RAS, CAS, WE, DQM) of SDRAM memory array.The data bus of SDRAM data bus interface circuit and cpu data bus, SDRAM memory array and instruction decode and refresh control unit link to each other, thereby finish the exchanges data between CPU and SDRAM memory array and the automatic refresh function of SDRAM storer.Controller in the present embodiment can be supported the memory array of capacity maximum to 4096G bits.

SDRAM finishes read-write and refreshes that to wait operation be that appropriate address and data on the different sequential of its input control signal of dependence CLOCK, CKE, CS, RAS, CAS, WE, DQM and address, the data bus are finished.Referring to Fig. 3, to read a data instance from certain storage unit, need provide row address effective instruction (CKE=HIGH earlier, CSn=LOW, RAS=LOW, CAS=HIGH, WE=HIGH) and respective row address (ADDR, A10/AP) and piece (Bank) address (BA), certain hour (some clock period) provides read instruction (CKE=HIGH, CSn=LOW, RAS=HIGH afterwards more at interval, CAS=LOW, WE=HIGH) and respective column address (ADDR, A10/AP), when CAS Latency=3, after 3 clock period, the data of this address will appear on the data bus (DQ).Equally, write operation and initialize memory, refresh, precharge etc. all needs outside sdram controller to provide the command adapted thereto signal according to the regulation of table 1.

Order			CKE n-1	CK En	CS	RAS	CAS	WE	DQM	BA0，1	A10/AP	A11，A9～0
Order			CKE n-1	CK En	CS	RAS	CAS	WE	DQM	BA0，1	A10/AP	A11，A9～0	Mode register is provided with			H	X	L	L	L	L	X	Operational code
Automatically refresh			H	H	L	L	L	H	V	X			Mode register is provided with			H	X	L	L	L	L	X	Operational code
Automatically refresh			H	H	L	L	L	H	V	X			Line activating			H	X	L	L	H	H	X	V	Row address
Read	Auto-precharge closes		H	X	L	H	L	H	X	V	L	Column address	Line activating			H	X	L	L	H	H	X	V	Row address
	Auto-precharge closes										L		Auto-precharge is opened		H
	Write	Auto-precharge closes									H		Auto-precharge is opened		H	X	L	H	L	L	X	V	L	Column address
Auto-precharge is opened		Auto-precharge closes		H																			L
Auto-precharge is opened		Burst finishes			H	X	L	H	H	L		X	X
Precharge		Burst finishes			H	X	L	H	H	L	Piece is selected	X	X			H	X	L	L	H	L	X	V	L	X
		All pieces	X	H							Piece is selected												V	L
		All pieces	X	H	No-operation instruction			H	X	H	X	X	X	X	X
L	H	H	H							H	X	X	X

Table 1

In the table 1, the effective X=of V=it doesn't matter H=logic high L=logic low

The instruction that the present invention sends according to computer software, carry out instruction decode by instruction decode and refresh control unit, produce RAS, CAS, WE, the DQM signal of corresponding time sequence at the output signal end of this element, instruction decode simultaneously and refresh control unit also control strip choosing and address latch unit produce corresponding C KE, CS, BA and address (ADDR) signal, and control SDRAM data bus interface unit is written to the data on the cpu data bus in the SDRAM storer or with data and reads on the cpu data bus from the SDRAM memory array.When finishing each sequential of read-write, the instruction decode of Fig. 1 and refresh control unit also can produce automatic refreshing instruction automatically, and the SDRAM storer is carried out periodic refresh, to keep the correct of data storage.

Fig. 2 is the inside theory diagram of instruction decoding and refresh control unit.Instruction decoding unit receives the instruction (all instructions all are listed in the table 1) of cpu control bus and data bus, signal Y1, Y2, Y3 and Y4, Y5, Y6 after the instruction decode are delivered to WE and DQM signal generation unit and RAS and CAS signal generation unit respectively, also can produce simultaneously and refresh enabled instruction and start and to refresh and precharge instruction generation unit produces and refreshes (REFRESH) and precharge command signal PRG, WE and DQM signal generation unit and RAS and CAS signal generation unit produce RAS, CAS, WE, the DQM signal that meets SDRAM memory requirement sequential.Simultaneously, also will produce address output control signal control output row address or column address, and produce the data input/output control signal and flow to control data.

In the present embodiment, sheet choosing and address latch unit mainly are made up of a 6-64 code translator, two 12 latchs and 12 alternative MUX.The 6-64 code translator produces corresponding C S, Bank and CKE signal according to software instruction; Two 12 latchs latch row address and column address respectively, and this two-way address signal is given 12 alternative MUX, and MUX output row address or column address under the control of address output control signal are given the address bus of SDRAM array.

The SDRAM data bus interface unit mainly is made up of one 16 triple gate, the control end of triple gate with receive the data input/output signal that instruction decode and refresh control unit produce, with control the data on the cpu data bus are written in the SDRAM storer or with data and from the SDRAM memory array, read on the cpu data bus.

Present embodiment can be supported the memory array of capacity maximum to 4096G bits, it should be noted that by the expansion to sheet choosing and address latch circuit among the present invention, can further enlarge the capacity of memory array.

Controller circuitry in the present embodiment is all realized with hardware, is write a slice FPGA (field programmable gate array) chip at last.

Claims

1. the controller of a Synchronous Dynamic Random Access Memory comprises sheet choosing and address latch circuit, Synchronous Dynamic Random Access Memory data bus interface circuit; It is characterized in that, also comprise instruction decode and refresh control unit, described instruction decode and refresh control unit, sheet choosing and address latch circuit link to each other with the control bus and the data bus of control with CPU;

Described choosing and address latch circuit be according to the steering order of the CPU that receives, produces that Synchronous Dynamic Random Access Memory array required sheet choosing, clock enable, address signal;

Described instruction decode and refresh control unit produce the required control signal of Synchronous Dynamic Random Access Memory array according to the steering order of the CPU that receives;

The data bus of described Synchronous Dynamic Random Access Memory data bus interface circuit and cpu data bus, Synchronous Dynamic Random Access Memory array and instruction decode and refresh control unit link to each other.

2. press the controller of the described Synchronous Dynamic Random Access Memory of claim 1, it is characterized in that the control signal that described instruction decode and refresh control unit produce comprises the required RAS of Synchronous Dynamic Random Access Memory array, CAS, WE, DQM signal.

3. by the controller of the described Synchronous Dynamic Random Access Memory of claim 1, it is characterized in that described instruction decode and refresh control unit also produce address output control signal, this signal controlling sheet choosing and address latch circuit output row address or column address; Instruction decode and refresh control unit also produce the data input/output control signal, the data flow of this signal controlling Synchronous Dynamic Random Access Memory data bus interface circuit.

4. press the controller of the described Synchronous Dynamic Random Access Memory of claim 3, it is characterized in that, described instruction decode and refresh control unit can produce automatic refreshing instruction automatically, and Synchronous Dynamic Random Access Memory is carried out periodic refresh, to keep the correct of data storage.

5. by the controller of the described Synchronous Dynamic Random Access Memory of claim 1, it is characterized in that described controller can be supported the memory array of capacity maximum to 4096 G bits.

6. by the controller of the described Synchronous Dynamic Random Access Memory of claim 1, it is characterized in that described controller circuitry is all realized with hardware, write a slice fpga chip.