CN113114550A - I2C communication control method, device and storage medium - Google Patents
I2C communication control method, device and storage medium Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40019—Details regarding a bus master
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Abstract
I2C communication control method, device and storage medium for realizing I through I/O interface2C, the method is implemented based on a timer and a dual-state machine, and comprises the following steps: for I2C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine in each communication state; for the transition from one communication state to the other communication state, according to I2C communication protocol or received I2C, communication command, the second state machine is converted into a target communication state based on bytes; wherein, I2The communication state of the C communication comprises a starting state, an addressing state, a data sending state, a data receiving state and a stopping state. Scheme I2The real-time performance and controllability of the C communication are well guaranteed, and meanwhile, the control and stability of the communication are achieved, the system overhead is saved, and the real-time performance of the system is improved.
Description
Technical Field
The invention relates to the technical field of communication control schemes among instruments and equipment, in particular to a communication control method I2C communication control method, apparatus and storage medium.
Background
At present I2C communication control technology and protocol are mature, and almost all microcontrollers have one or even more I2C communication controller, however, in practice implementing master and slave I2In the communication process between the C, the implementation modes are not limited to two types: one, using I inside the microcontroller2And C, controlling the module, and if the module is designed without defects, effectively processing various communication process abnormalities and interrupts, which is the most stable and reliable adoption mode with the highest efficiency. However, with the complexity of the actual microprocessor operating conditions and external I2The diversity of communication equipment, when the actual equipment works, various interrupts and abnormal conditions often occur, I2C communication process can be interrupted and even abnormal, and many microcontrollers have internal I2C, the communication control itself has design defects, and situations such as incomplete data transmission, clock loss, and bus occupation errors may occur. Moreover, due to system complexity, such anomalies and errors occur without fixed regularity, sometimes even sporadically, which is true for I2For C communication system, the reliability and stability of the system are seriously damaged, resulting in I2The reliability and stability of the C communication system are poor. Second, using I/O ports, to I2The C bus carries out analog communication, the mode can avoid the design defects of the module, I/O simulation is completely adopted, due to the change of the high and low levels of the bus, very strict requirements are made on time sequence, a large number of waiting delay modes are required in the period, the overhead of system design increased by the design consumes the operation speed resource of a processor although the stability becomes controllable, and the actual communication process is greatly reducedThe real-time performance of the system is low.
Therefore, the prior art scheme, either I2The reliability and stability of the C communication system are poor, or I2The reliability and stability of the C communication system are well controlled, and the operation speed resource of the processor is consumed, so that I2The real-time performance of the C communication system is poor.
Disclosure of Invention
The embodiment of the invention provides a2C communication control method, equipment and storage medium to overcome I in the prior art2And C, the communication system cannot achieve the technical problem that the reliability or the stability and the real-time performance are well controlled.
In a first aspect, there is provided an I2C communication control method for realizing I through I/O interface2C, in the communication device of communication, based on the timer and the dual-state machine implementation, the method includes:
for I2C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine in each communication state;
for the transition from one communication state to the other communication state, according to I2C communication protocol or received I2C, communication command, the second state machine is converted into a target communication state based on bytes;
wherein, I2The communication state of the C communication comprises a starting state, an addressing state, a data sending state, a data receiving state and a stopping state.
Preferably, the first and second electrodes are formed of a metal,
said conversion between communication states is according to I2C communication protocol or received I2C, communication command, determining the target communication state converted by the second state machine, including:
if the communication state is a starting state, according to I2C, the communication protocol determines that the second state machine is converted into an addressing state;
if the communication state is the addressing state, numberAccording to the sending state or the data receiving state, according to the received I2C communication command, determining the second state machine to be converted into I2C, communication state corresponding to the communication command;
if the communication state is a stop state, according to I2The communication protocol C determines that the second state machine transitions to an idle state.
Preferably, the first and second electrodes are formed of a metal,
in I2In the starting state of the communication C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine comprises the following steps:
if the potential of the clock line is high level, entering a starting state from S4, and generating a bus clock signal and a bus data signal based on the data bit in the S5, S6 and S7 sub-states in the starting state based on the state rotation of the first state machine;
if the potential of the clock line is at a low level and the potential of the data line is at a high level, entering a start state from S2, and generating a bus clock signal and a bus data signal based on the data bit in the S3, S4, S5, S6 and S7 sub-states in the start state based on the timer;
if the position of the clock line and the potential of the data line are both low level, entering a starting state from S0, and generating a bus clock signal and a bus data signal based on the data bit in the S1, S2, S3, S4, S5, S6 and S7 sub-states in the starting state based on the timer;
wherein S0, S1, S2, S3, S4, S5, S6 and S7 are sub-states of the starting state.
Preferably, in I2In the addressing state of the communication C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine comprises the following steps:
aiming at a 7-bit address bit and a 1-bit read/write flag bit of an addressing state, the first state is converted into the following states:
controlling the potential of the A0 sub-state data line to change according to the level of the current data bit;
the potential of the clock line controlling the a1 substate is high;
in the A2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
in the a3 substate, the potential of the control clock line is low;
for the 9 th bit of data in the addressing process, the first state machine translates as follows:
controlling the potential of the A0 sub-state data line to change according to the level of the current data bit;
the potential of the clock line controlling the a1 substate is high;
in the A2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
reading the potential of the data line in an A3 substate, if the potential is high level, determining that no ACK signal is received, and if the potential is low level, determining that the ACK signal is received;
wherein, the ACK signal is an address response signal;
in the A3 substate of the 9 th data bit in the addressing process, the second state machine is converted into a data sending state, a data receiving state or a stop state according to the received communication signal;
wherein A0, A1, A2, and A3 are the sub-states of the addressing state.
Preferably, in I2In the data sending state of C communication, through the state rotation of the first state machine, the bus clock signal and the bus data signal based on the data bit in each communication state are generated based on the timer, including:
for each of the 8-bit data bits in the data transmit state:
in the T0 substate, the data line changes according to the level of the current data bit;
in the T1 substate, the potential of the clock line is high;
in the T2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
aiming at the 9 th bit of the data sending stage, the first state machine makes the following conversion:
controlling the potential of the T0 substate data line to change according to the level of the 9 th bit data bit;
controlling the potential of the clock line of the T1 substate to be high;
in the T2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
reading the potential of the data line in a T3 substate, if the potential is high level, determining that no ACK signal is received, and if the potential is low level, determining that the ACK signal is received;
wherein, the ACK signal is a data response signal;
in the T3 substate of the 9 th bit data bit in the data transmission process, the second state machine continues to execute the data transmission state or enter the stop process and the bus idle state according to the received communication signal;
wherein, T0, T1, T2 and T3 are sub-states of the data transmission state.
Preferably, in I2In the stop state of C communication, through the state round of first state machine, produce bus clock signal and bus data signal based on data bit in each communication state based on the timer, include:
in the P0 substate, the first state machine controls the data line to low;
in the P1 substate, the first state control waits one clock cycle;
in the P2 substate, the first state machine controls the potential of the clock line to be high;
in the P3 substate, the first state machine controls to wait for one clock cycle;
in the P4 substate, the first state machine controls the potential of the data line to be high;
the stop states include a P0 sub-state, a P1 sub-state, a P2 sub-state, a P3 sub-state, and a P4 sub-state.
In a second aspect, an I-based device is provided according to an embodiment of the present invention2The C communication control system is realized based on a timer and a dual-state machine, and comprises:
a first conversion module for I2C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine in each communication state;
a second conversion module for converting one communication state to another communication state according to I2C communication protocol or received I2C, communication command, the second state machine is converted into a target communication state based on bytes;
wherein, I2The communication state of the C communication comprises a starting state, an addressing state, a data sending state, a data receiving state and a stopping state.
Preferably, the second conversion module is further configured to:
if the communication state is a starting state, according to I2C, the communication protocol determines that the second state machine is converted into an addressing state;
if the communication state is an addressing state, a data sending state or a data receiving state, according to the received I2C communication protocol, determining the second state machine to be converted into I2C, communication state corresponding to the communication protocol;
if the communication state is a stop state, according to I2The communication protocol C determines that the second state machine transitions to an idle state.
In a third aspect, there is provided an I2C, communication control equipment comprising a memory and a processor, wherein the memory and the processor are mutually connected in a communication way, the memory is stored with computer instructions, and the processor executes the computer instructions so as to execute the I2C, communication control method.
In a fourth aspect, according to an embodiment of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a computer to execute I of any one of the above2C, communication control method.
The invention adopts a state machine implementation mode based on a timer mode, and completely follows I2C communication mode,Under the precondition of communication protocol, I/O simulation I is also adopted2C communication bus technology, except that I is performed completely by a timer2On one hand, the baud rate of transmission can be accurately controlled by controlling a timer; on the other hand, the real-time performance of the equipment is effectively improved by a rotating cycle control mode of the double-state machine, and a waiting delay mode is not needed; thirdly, I can be simulated completely accurately2C various communication states in communication, and quickly processing various abnormities and interruptions of the bus, because of adopting a timer interruption mode, I2The real-time performance and controllability of the C communication are well guaranteed. In the application process of the actual engineering project, the method provided by the invention is proved to be controllable and stable in communication, save the system overhead and improve the real-time property of the system.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 shows a schematic diagram of an embodiment of the present invention2C, schematic diagram of each communication state included in communication;
FIG. 2 is a drawing I provided in the present embodiment2C, a flow chart of a communication control method;
FIG. 3 is a flowchart of step S14 according to an embodiment of the present invention;
FIG. 4 is a drawing I provided as an example of the present invention2A timing chart of bus signals (including a clock line signal and a data line signal) of each sub-state of the start state of the C communication;
FIG. 5 shows a graph I2A bus signal (comprising a clock line signal and a data line signal) timing chart of each sub-state of the addressing state of the communication C;
FIG. 6 shows a graph I2A timing chart of bus signals (including clock line signals and data line signals) of each sub-state of the data transmission state of the communication C;
FIG. 7 shows a graph I2A timing chart of bus signals (including clock line signals and data line signals) of each sub-state of the data receiving state of the communication C;
FIG. 8 is a drawing providing illustration I of an embodiment of the present invention2A timing chart of bus signals (including a clock line signal and a data line signal) of each sub-state of the stop state of the C communication;
FIG. 9a, 9b is I2C, a timing chart of bus signals (including clock line signals and data line signals) under the condition of single-byte transmission and multi-byte transmission in communication;
FIG. 10a, 10b is I2C, a timing diagram of bus signals (including clock line signals and data line signals) under the conditions of single-byte reading and multi-byte reading in communication;
11a, 11b are timing diagrams of clock line signals and data line signals generated by a first state machine and a second state machine according to the scheme of the present invention for data with 2 bits;
FIG. 12 shows a block diagram of a block diagram I2C, a block diagram of the communication control equipment;
FIG. 13 shows a block diagram of a mobile device I according to an embodiment of the present invention2C, a bus diagram of the communication control device.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The invention is mainly based on I2C communication bus and communication protocol, I2The C communication bus can be mainly divided into 5 main states or processes, as shown in fig. 1, including a START State (START), an address state (ADDR), a data SEND State (SEND), a data receive state (RECV), a STOP State (STOP), and the like. All of I2C communication processes (actual transmission processes) are all permutation and combination of the processes and conversion of the processes, so that the next-stage communication process state machine is generated, and communication process control such as sending one byte, sending a plurality of bytes, receiving one byte, receiving a plurality of bytes and the like is generated. Between these 5 states and the idle state (bus idle) 6 states, the switching of the states can be realized by different communication conditions, which are automatically selected and switched according to the actual communication process. In FIG. 1, S0, S1, S2, S3, S4, S5, S6, and S7 are START States (START)A sub-state; a0, A1, A2, A3 are the sub-states of the addressing state (ADDR); t0, T1, T2, T3 are sub-states of the data SEND State (SEND); p0, P1, P2, P3, P4 are sub-states of STOP State (STOP); r0, R1, R2, R3 are sub-states of the data reception state (receive). This figure 1 will be described in further detail below.
Example 1
The embodiment of the invention provides a2C communication control method for realizing I through I/O interface2C, in the communication device for communication, the implementation is based on a timer and a dual-state machine, as shown in fig. 2, the method includes:
step S12 for I2C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine in each communication state;
step S14, for the conversion between one of the communication states to the other communication state, according to I2C communication protocol or received I2C, communication command, the second state machine is converted into a target communication state based on bytes;
wherein, I2The communication state of the C communication comprises a starting state, an addressing state, a data sending state, a data receiving state and a stopping state.
It should be noted that, in the embodiment of the present invention, instead of only including one step S12 and one step S14, the steps S12 and S14 are nested and used, and in I2C, internally executing step S12 in each communication state of the communication, after generating the complete clock signal and data signal of the current communication state through step S12, generating the clock signal and data signal between two adjacent communication states through step S14, and after converting to the next communication state, continuing to generate the clock signal and data signal of the communication state through step S12.
Note here that "I" mentioned in step S122Each communication state of C communication is I2C, starting state, addressing state, data development state, data receiving state or stopping state of communication.
In the embodiment of the invention, the point I2C, completing the conversion of each sub-state in the current state based on a first state machine of a timer in each state (starting state, addressing state, data sending state, data receiving state or stopping state) of communication to form each bit clock signal and data signal in the communication process; in I2C, switching among the states of communication is to determine the second state machine to switch to the next communication stage according to the specific communication process control, and each communication stage generates a bus clock signal and a data signal based on a timer through the state rotation of the first state machine.
The bus clock signal (of the current stage) and the data signal are generated based on the timer through the state rotation of the first state machine. Thereby not only ensuring I2C communication reliability and stability, and can enlarge system overhead and effectively ensure I2And C, the timeliness of communication.
In the embodiment of the present invention, referring to fig. 3, step S14 includes:
step S141, if the communication state is the starting state, according to I2C, the communication protocol determines that the second state machine is converted into an addressing state;
step S142, if the communication state is addressing state, data transmitting state or data receiving state, according to the received I2C communication protocol, determining the second state machine to be converted into I2C, communication state corresponding to the communication protocol;
step S143, if the communication state is the stop state, according to I2The communication protocol C determines that the second state machine transitions to an idle state.
I provided by the embodiment of the invention2C communication control method based on I2C, if the communication state is the starting state, after the starting state is executed, the communication protocol can only be converted into the addressing state; similarly, if the communication state is the stop state, the second state machine can be determined to be converted into the idle state according to the protocol, and in the addressing state, the data sending state or the data receiving state, after the addressing state, the data sending state or the data receiving state is executedCan be based on the received I2C communication command determining the second state machine to be converted into I2C, communication state corresponding to the communication command.
Further, in the present embodiment, in I2In the starting state of the communication C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine comprises the following steps:
if the potential of the clock line is high level, entering a starting state from S4, and generating a bus clock signal and a bus data signal based on the data bit in the S5, S6 and S7 sub-states in the starting state based on the state rotation of the first state machine;
if the potential of the clock line is at a low level and the potential of the data line is at a high level, entering a start state from S2, and generating a bus clock signal and a bus data signal based on the data bit in the S3, S4, S5, S6 and S7 sub-states in the start state based on the timer;
if the position of the clock line and the potential of the data line are both low level, entering a starting state from S0, and generating a bus clock signal and a bus data signal based on the data bit in the S1, S2, S3, S4, S5, S6 and S7 sub-states in the starting state based on the timer;
wherein S0, S1, S2, S3, S4, S5, S6 and S7 are sub-states of the starting state.
Specifically, the START (START) state is initiated first, primarily for I2The C-bus generates a START Signal (START) from an idle state. The generation of the START signal needs to make different state transitions according to the difference of the high and low levels of the current data line SDA and the clock line SCL, and the START process is mainly divided into 3 cases: the clock line SCL is high, and then counts into the START State (START) from the S4 sub-state regardless of whether the level of the data line SDA is high or low; if the clock line SCL is low and the data line SDA is high, the START state is entered from the S2 sub-state, and the S4 sub-state is reached through the S3 sub-state; when both the clock line SCL and the data line SDA are low, the S0 sub-state goes through the S1 sub-state, the S2 sub-state, and the S3 sub-state to the S4 sub-state. By timingThe method comprises the steps that a timer runs according to the frequency which is 4 times of the baud rate, the current state automatically carries out the next conversion every time the timer reaches, the high-low level changing action or the reading action can be carried out on a data line SDA and a clock line SCL every time, the START input state is an (IDLE) IDLE state, 3 seed states such as S0, S2 and S4 input to START, the S4 sub-state data line SDA is set to be at a low level, the S5 sub-state waits for one period, the S6 sub-state clock line SCL is set to be at a low level, and finally the data line signal, the S6 and the S7 sub-state are output after passing through the S5 sub-state, the S6 sub-state and the S7 sub-state, and the complete START signal is generated by.
In the examples of the present invention, in I2In the addressing state of the communication C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine comprises the following steps:
1) aiming at a 7-bit address bit and a 1-bit read/write flag bit of an addressing state, the first state is converted into the following states:
2) controlling the potential of the A0 sub-state data line to change according to the level of the current data bit;
3) the potential of the clock line controlling the a1 substate is high;
4) in the A2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
5) in the a3 substate, the potential of the control clock line is low;
for the 9 th bit of data in the addressing process, the first state machine translates as follows:
1) controlling the potential of the A0 sub-state data line to change according to the level of the current data bit;
2) the potential of the clock line controlling the a1 substate is high;
3) in the A2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
4) reading the potential of the data line in an A3 substate, if the potential is high level, determining that no ACK signal is received, and if the potential is low level, determining that the ACK signal is received;
wherein, the ACK signal is an address response signal;
in the A3 substate of the 9 th data bit in the addressing process, the second state machine is converted into a data sending state, a data receiving state or a stop state according to the received communication signal;
wherein A0, A1, A2, and A3 are the sub-states of the addressing state.
In particular, in I2Addressing State (ADDRESS) of C communication, mainly I2The C communication bus sends the ADDRESS responded by the slave device, and mainly comprises 9 bits of ADDRESS (7 bits), read/write flag (1bit) and response (1bit), each bit transmission comprises 4 sub-state transitions of A0 sub-state, A1 sub-state, A2 sub-state and A3 sub-state, the ADDRESS process state is input from A0 sub-state, and A3 sub-state is output. The potential of the state data line SDA of A0 changes according to the potential of the corresponding data bit, the clock line SCL of A1 sub-state is set to high level, whether the clock line SCL of A2 sub-state is high, if not, the current state is continued to wait, the clock line SCL of A3 sub-state is set to low level, each data bit carries out 4 sub-state (A0, A1, A2 and A3) conversion processes, the next data bit carries out state circulation until the sending of 8 bits of total address bit (7bit) and read/write bit (1bit) is completed, the state of A3 reads the high-low state of the data line at the 9 th bit, and whether the slave generates the ACK response signal is determined. After the cycle is performed for 9 times, whether slave devices with corresponding addresses exist on the bus can be judged, and in the sub-state of the 9bit a3, according to the communication control requirement, either a data sending process (SEND), a data receiving process (receive), or a STOP process (STOP) can be performed, or the bus IDLE (IDLE) state can be directly entered, as shown in fig. 5.
In the examples of the present invention, in I2In the data sending state of C communication, through the state rotation of the first state machine, the bus clock signal and the bus data signal based on the data bit in each communication state are generated based on the timer, including:
for each of the 8-bit data bits in the data transmit state:
1) in the T0 substate, the data line changes according to the level of the current data bit;
2) in the T1 substate, the potential of the clock line is high;
3) in the T2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
aiming at the 9 th bit of the data sending stage, the first state machine makes the following conversion:
1) controlling the potential of the T0 substate data line to change according to the level of the 9 th bit data bit;
2) controlling the potential of the clock line of the T1 substate to be high;
3) in the T2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
4) reading the potential of the data line in a T3 substate, if the potential is high level, determining that no ACK signal is received, and if the potential is low level, determining that the ACK signal is received;
wherein, the ACK signal is a data response signal;
in the T3 substate of the 9 th bit data bit in the data transmission process, the second state machine continues to execute the data transmission state or enter the stop process and the bus idle state according to the received communication signal;
wherein, T0, T1, T2 and T3 are sub-states of the data transmission state.
In particular, in I2In the communication C, the data state is divided into two different state processes of a data sending State (SEND) and a data receiving state (RECV), wherein the state switching process is similar and comprises 4 sub-state switching processes. The data sending State (SEND) mainly comprises 8 bits of data bits and 1bit of response bits, 9 bits in total, and each bit also comprises 4 sub-state conversion processes.
The data Sending (SEND) process is similar to the ADDRESS (ADDRESS) process, the sub-state data line SDA of T0 changes according to the potential of the corresponding data bit, the clock line SCL of the sub-state of T1 is set to be at a high level, the first state machine of the sub-state of T2 reads whether the clock line SCL is at a high level, otherwise, the current state is continuously waited, the clock line SCL of the sub-state of T3 is set to be at a low level, each data bit carries out 4 sub-state conversion processes, the next data bit carries out state circulation similar to the previous data bit until the data 8bit is sent, and the sub-state of T3 reads the level high-low state of the data line SDA at the 9bit to determine whether the slave machine generates an ACK signal. According to the 9 th bit, whether the slave generates a response ACK signal or continues a data Sending (SEND) state or a STOP State (STOP) is determined, or the slave can directly enter a bus IDLE (IDLE) state to wait for other actions of a subsequent bus, which is specifically shown in fig. 6.
It is noted that the data Receive (RECV) process, similar to the transmit (SEND) process, differs in that the R0 substate does not change the state of the data line SDA, but changes the state of the data line SDA bit input, prepares to read the data on the SDA data line, and generates an ACK signal or a NACK signal to the slave at bit 9, depending on whether the last byte is currently present. In the R3 sub-state of the data receiving process, the high-low state of the data line SDA is read, and the data line SDA is shifted and stored, and meanwhile, if the bit is the 9 th bit, according to the communication control requirement, the data Receiving (RECV) process is continued, or the STOP process (STOP) is stopped, or the data line SDA can directly enter the bus IDLE (IDLE) state to wait for other actions of the subsequent bus, which is specifically shown in fig. 7.
In the examples of the present invention, in I2In the stop state of C communication, through the state round of first state machine, produce bus clock signal and bus data signal based on data bit in each communication state based on the timer, include:
1) in the P0 substate, the first state machine controls the data line to low;
2) in the P1 substate, the first state control waits one clock cycle;
3) in the P2 substate, the first state machine controls the potential of the clock line to be high;
4) in the P3 substate, the first state machine controls to wait for one clock cycle;
5) in the P4 substate, the first state machine controls the potential of the data line to be high;
the stop states include a P0 sub-state, a P1 sub-state, a P2 sub-state, a P3 sub-state, and a P4 sub-state.
In particular, a STOP (STOP) condition for flag I2The C communication bus exits the active state, i.e. is about to return to the IDLE state (IDLE), and contrary to the START state, the STOP state generates a STOP signal, passing through the P0, P1, P2, P3, P45 substates. Among them, the stop state is input from the P0 substate, and can be entered into the P0 substate from the IDLE (IDLE) state, the address state (ADDR), the data transmission (SEND) state, the data Reception (RECV) state, and the like, and be output from the P4 substate, and entered into the IDLE (IDLE) state. The P0 sub-state SDA data line is set to low level, the P1 sub-state waits for one clock cycle, the P2 sub-state clock line SCL is set to high level, the P3 sub-state waits for one clock cycle, the P4 sub-state data line SDA data line is set to high level, and finally the bus state enters an IDLE state (IDLE) from the STOP process (STOP), and the specific STOP state clock signal and data signal potential changes are shown in fig. 8.
In the examples of the invention, according to I2C communication bus and communication protocol, data sending State (SEND) cannot be switched directly to data receiving state (receive), and likewise data receiving state (receive) (neither can be switched directly to data sending State (SEND)2The C-bus communication process STARTs from a START state START, reaches an address state ADDR, then is a data process state, or a data SEND State (SEND), or a data accept state (RECV), cannot be switched in the middle, and finally enters a STOP State (STOP) and then returns to an IDLE state (IDLE).
In the examples of the present invention, I2C, sending data in communication is divided into single-byte sending and multi-byte sending, and the sending of data with different lengths causes the difference of the initialization operation parameters of the first state machine or the second state machine. Wherein, one byte sends: the initialization process is controlled to, START —>ADDRESS—>SEND—>STOP, including STOP process, directly entering ACK state returning judgment from start State (STOP), reading whether ACK signal is correctly returned in the above process, and finally returning to IDLE state (IDLE), as shown in fig. 9 a; the multi-byte sending initialization process control is as follows: START->
ADDRESS — > SEND, does not include a STOP process, and according to the length of the byte to be sent, selects to enter the second state machine that SENDs the next byte, or SENDs the second state machine that SENDs the last byte, then enters an ACK state return judgment, and finally returns to an idle state if an ACK signal, including two signals of ADDRESS ACK and data ACK, is correctly returned in the reading process, as shown in fig. 9 b.
And I2Data transmission in C communication is similar, I2The data reading process in the communication C is divided into single-byte reading and multi-byte reading, and different from the data sending, the data receiving process needs to firstly carry out the data sending process, mainly sending the address of a lower computer register, and the difference is I2The device address of C is called the internal register address of the slave. From the idle state, all require the transmission of register address data, including START —>ADDR—>SEND (register Address) — A register address>STOP, and the like. Depending on the length of the received data, i.e., the read length, the next state machine to a byte is to read a byte, including START —>ADDRESS—>RECIEVE(NACK)—>The STOP process, then returning the read data, and finally returning to an idle state; reading multi-byte data enters a first byte state machine START->ADDRESS—>A receive (ACK) that, according to the length of the read byte, enters reading the next byte or the last byte, during the middle reading process, the master device needs to send an ACK signal, when reading the last byte data, the host does not need ACK, that is, NACK, and after generating a STOP signal, returns to the data content read for the last time, and then the first state machine and the second state machine enter an idle state, as shown in fig. 10a and 10b specifically.
In the actual communication process, if the slave device address sent by the master device does not exist, the address sending process directly generates NACK, instead of generating NACK in the data sending process. I is2In the writing process, after the master device finishes writing the last byte, the slave device returns an ACK signal, and then the master device sends a STOP signal to finish communication; however, during the reading process, the master device will return NACK after receiving the last byte sent by the slave device, since the master device has already sent NACK at this timeUpon receipt of enough bytes, the NACK tells the slave that no more data is to be sent, and the master then sends a STOP signal to end the communication.
With the method described in this scheme, 2 bits for a data bit, the timing diagrams of fig. 11a and 11b can be generated by the nested use of the first state machine and the second state machine.
Example 2
In a second aspect, there is provided an I2The C communication control device, implemented based on a timer and a dual-state machine, as shown in fig. 12, includes:
first conversion Module 121, for I2C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine in each communication state;
a second conversion module 122 for converting one communication state to another communication state according to I2C communication protocol or received I2C, communication command, the second state machine is converted into a target communication state based on bytes;
wherein, I2The communication state of the C communication comprises a starting state, an addressing state, a data sending state, a data receiving state and a stopping state.
In an embodiment of the present invention, the second converting module 122 is further configured to:
if the communication state is a starting state, according to I2C, the communication protocol determines that the second state machine is converted into an addressing state;
if the communication state is an addressing state, a data sending state or a data receiving state, according to the received I2C communication protocol, determining the second state machine to be converted into I2C, communication state corresponding to the communication protocol;
if the communication state is a stop state, according to I2The communication protocol C determines that the second state machine transitions to an idle state.
The embodiment of the invention provides a method for realizing I based on a timer and a dual-state machine2C communication control system byThe first conversion module and the second conversion module control the first state machine and the second state machine to be nested for use, and the first conversion module and the second conversion module are used in I2C, inside each communication state, the first state machine is adopted to realize the time sequence change of the clock line SCL and the data line SDA, and in I2C, between the communication states, forming I through the time sequence change of the second state and the clock line SCL and the data line SDA realizing the adjacent two states2C full clock line signal and data line signal of communication.
Example 3
This embodiment provides a method for implementing I based on timer and dual state machine2C communication control device, as shown in FIG. 13, the I2The C communication control device includes a processor 1301 and a memory 1302, where the processor 1301 and the memory 1302 may be connected by a bus or in other ways, and fig. 13 illustrates an example of a connection by a bus.
The Processor 1301 may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), an embedded Neural Network Processor (NPU), or other dedicated deep learning coprocessor, an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like, or a combination thereof.
The memory 1302, which is a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as program instructions/modules (e.g., the first conversion module 131 and the second conversion module 122 shown in fig. 12) corresponding to the video frame continuity detection method in the embodiment of the present invention. The processor 1301 executes various functional applications and data processing of the processor, namely, implementing I in the above method embodiments, by running non-transitory software programs, instructions and modules stored in the memory 13022C, communication control method.
The memory 1302 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created by the processor 1301, and the like. Further, memory 1302 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 1302 may optionally include memory located remotely from processor 1301, which may be connected to processor 1301 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The one or more modules are stored in the memory 1302 and, when executed by the processor 1301, perform I as shown in FIG. 22C, communication control method.
In this embodiment, the memory 1302 stores program instructions or modules for the video continuity detection method, and the processor 1301 executes the program instructions or modules stored in the memory 1302 for I2C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine in each communication state; for the transition from one communication state to the other communication state, according to I2C communication protocol or received I2C, communication command, the second state machine is converted into a target communication state based on bytes; wherein, I2The communication state of the C communication comprises a starting state, an addressing state, a data sending state, a data receiving state and a stopping state. So that I2The real-time performance and controllability of the C communication are well guaranteed, the system overhead is saved, and the real-time performance of the system is improved.
Embodiments of the present invention further provide a non-transitory computer storage medium, where the computer storage medium stores computer-executable instructions, and the computer-executable instructions can execute I in any of the above method embodiments2C, communication control method. Wherein the storage medium may be magneticA Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, device or computer readable storage medium all relating to or including a computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. I2C communication control method for realizing I through I/O interface2C, communication equipment is characterized in that the method is realized based on a timer and a dual-state machine, and comprises the following steps:
for I2C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine in each communication state;
for the transition from one communication state to the other communication state, according to I2C communication protocol or received I2C, communication command, the second state machine is converted into a target communication state based on bytes;
wherein, I2The communication state of the C communication comprises a starting state, an addressing state, a data sending state, a data receiving state and a stopping state.
2. The method of claim 1,
said conversion between communication states is according to I2C communication protocol or received I2C, communication command, determining the target communication state converted by the second state machine, including:
if the communication state is a starting state, according to I2C, the communication protocol determines that the second state machine is converted into an addressing state;
if the communication state is an addressing state, a data sending state or a data receiving state, according to the received I2C communication command, determining the second state machine to be converted into I2C, communication state corresponding to the communication command;
if the communication state is a stop state, according to I2The communication protocol C determines that the second state machine transitions to an idle state.
3. The method of claim 2,
in I2In the starting state of the communication C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine comprises the following steps:
if the potential of the clock line is high level, entering a starting state from S4, and generating a bus clock signal and a bus data signal based on the data bit in the S5, S6 and S7 sub-states in the starting state based on the state rotation of the first state machine;
if the potential of the clock line is at a low level and the potential of the data line is at a high level, entering a start state from S2, and generating a bus clock signal and a bus data signal based on the data bit in the S3, S4, S5, S6 and S7 sub-states in the start state based on the timer;
if the position of the clock line and the potential of the data line are both low level, entering a starting state from S0, and generating a bus clock signal and a bus data signal based on the data bit in the S1, S2, S3, S4, S5, S6 and S7 sub-states in the starting state based on the timer;
wherein S0, S1, S2, S3, S4, S5, S6 and S7 are sub-states of the starting state.
4. The method of claim 2, wherein at I2In the addressing state of the communication C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine comprises the following steps:
aiming at a 7-bit address bit and a 1-bit read/write flag bit of an addressing state, the first state is converted into the following states:
controlling the potential of the A0 sub-state data line to change according to the level of the current data bit;
the potential of the clock line controlling the a1 substate is high;
in the A2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
in the a3 substate, the potential of the control clock line is low;
for the 9 th bit of data in the addressed state, the first state machine translates as follows:
controlling the potential of the A0 sub-state data line to change according to the level of the current data bit;
the potential of the clock line controlling the a1 substate is high;
in the A2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
reading the potential of the data line in an A3 substate, if the potential is high level, determining that no ACK signal is received, and if the potential is low level, determining that the ACK signal is received;
wherein, the ACK signal is an address response signal;
in the A3 substate of the 9 th data bit in the addressing process, the second state machine is converted into a data sending state, a data receiving state or a stop state according to the received communication signal;
wherein A0, A1, A2, and A3 are the sub-states of the addressing state.
5. The method of claim 2, wherein at I2In the data sending state of C communication, through the state rotation of the first state machine, the bus clock signal and the bus data signal based on the data bit in each communication state are generated based on the timer, including:
for each of the 8-bit data bits in the data transmit state:
in the T0 substate, the data line changes according to the level of the current data bit;
in the T1 substate, the potential of the clock line is high;
in the T2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
aiming at the 9 th bit of the data sending stage, the first state machine makes the following conversion:
controlling the potential of the T0 substate data line to change according to the level of the 9 th bit data bit;
controlling the potential of the clock line of the T1 substate to be high;
in the T2 substate, reading whether the potential of the clock line is at a high level, and if not, continuing to wait;
reading the potential of the data line in a T3 substate, if the potential is high level, determining that no ACK signal is received, and if the potential is low level, determining that the ACK signal is received;
wherein, the ACK signal is a data response signal;
in the T3 substate of the 9 th bit data bit in the data transmission process, the second state machine continues to execute the data transmission state or enter the stop process and the bus idle state according to the received communication signal;
wherein, T0, T1, T2 and T3 are sub-states of the data transmission state.
6. The method of claim 2, wherein at I2In the stop state of C communication, through the state round of first state machine, produce bus clock signal and bus data signal based on data bit in each communication state based on the timer, include:
in the P0 substate, the first state machine controls the data line to low;
in the P1 substate, the first state control waits one clock cycle;
in the P2 substate, the first state machine controls the potential of the clock line to be high;
in the P3 substate, the first state machine controls to wait for one clock cycle;
in the P4 substate, the first state machine controls the potential of the data line to be high;
the stop states include a P0 sub-state, a P1 sub-state, a P2 sub-state, a P3 sub-state, and a P4 sub-state.
7. I2C communication control equipment, characterized by being realized based on a timer and a dual-state machine, the equipment comprises:
a first conversion module for I2C, generating a bus clock signal and a bus data signal based on a data bit in each communication state based on a timer through state rotation of a first state machine in each communication state;
a second conversion module for converting one communication state to another communication state according to I2C communication protocol or received I2C, communication command, the second state machine is converted into a target communication state based on bytes;
wherein, I2The communication state of the C communication comprises a starting state, an addressing state, a data sending state, a data receiving state and a stopping state.
8. The apparatus of claim 7, wherein the second conversion module is further configured to:
if the communication state is a starting state, according to I2C, the communication protocol determines that the second state machine is converted into an addressing state;
if the communication state is an addressing state, a data sending state or a data receiving state, according to the received I2C communication protocol, determining the second state machine to be converted into I2C, communication state corresponding to the communication protocol;
if the communication state is a stop state, according to I2The communication protocol C determines that the second state machine transitions to an idle state.
9. I2C communication control device, characterized in that it comprises a memory and a processor, said memory and said processor are connected with each other in communication, said memory stores computer instructions, said processor executes said computer instructions, thereby executing I of any of claims 1-62C, communication control method.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions for causing a computer to execute I of any one of claims 1-62C, communication control method.
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