CN207529371U - CPU fetchings system and electronic equipment - Google Patents
CPU fetchings system and electronic equipment Download PDFInfo
- Publication number
- CN207529371U CN207529371U CN201721135986.9U CN201721135986U CN207529371U CN 207529371 U CN207529371 U CN 207529371U CN 201721135986 U CN201721135986 U CN 201721135986U CN 207529371 U CN207529371 U CN 207529371U
- Authority
- CN
- China
- Prior art keywords
- cpu
- instruction
- bus control
- control unit
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Advance Control (AREA)
Abstract
The utility model provides a kind of CPU fetchings system and electronic equipment, and the CPU in CPU fetching systems is used to send the IA in the first address range to each bus control unit；At least two bus control units distinguish corresponding command memory connection, when a determine instruction address at least two bus control units is located in its instruction-fetching range, it is storage address by instruction address translation, the instruction for being stored in storage address is read in corresponding command memory, interval in the instruction-fetching range of the different and each bus control unit of the value range of each bus control unit between two IAes of arbitrary neighborhood is equal to the quantity of bus control unit, the instruction-fetching range of at least two bus control units forms the first address range, reaching CPU continual can enable different bus controller complete different fetching processes, reduce the stand-by period of CPU, improve the technique effect of fetching efficiency.
Description
Technical field
The utility model is related to field of computer technology, more particularly, to a kind of CPU fetchings system and electronic equipment.
Background technology
As microcontroller (Micro Controller Unit, MCU) is in the extensive use of computer realm, program institute
The space occupied is increasing, and this requires chip has the memory space of bigger.However, the memory space of bigger means into
This rising, in order to obtain balance between function and cost, more and more producers select string type perimeter interface (Serial
Peripheral Interface, SPI), two-wire system string type perimeter interface (Dual Serial Peripheral
Interface, DSPI) or four-wire type string type perimeter interface (Queued Serial Peripheral Interface,
QSPI external Flash), CPU are performed by the Flash outside SPI, DSPI or QSPI interface access chip into line program.
But the interface of SPI only has 1 data lines, the interface of DSPI only has 2 data lines, and the interface of QSPI only has 4
Data line, this can largely limitation CPU read instruction data volume, cause fetching bottleneck so that CPU often in etc.
It treats state, very big loss is caused to the performance of CPU, reduce the working efficiency of CPU.
Utility model content
In view of this, the purpose of this utility model is to provide CPU fetchings system and electronic equipment, to alleviate the prior art
Present in CPU fetchings process there are fetching bottlenecks, CPU that very big damage is caused to the performance of CPU often in wait state
The technical issues of losing, reducing the working efficiency of CPU.
In a first aspect, the utility model embodiment provides a kind of CPU fetchings system, including：CPU, at least two buses
Controller and with one-to-one at least two command memory of the bus control unit；
The CPU is connect respectively at least two bus control units, for being sent to each bus control unit
IA in first address range；
At least two bus control units distinguish corresponding command memory connection, when at least two buses
A determining described instruction address in controller is located in its instruction-fetching range, and the bus control unit utilizes preset function relationship
Described instruction address conversion is storage address by formula, is read in corresponding described instruction memory and is stored in the storage address
The instruction at place, the value range of each bus control unit is different and the instruction-fetching range of each bus control unit in it is arbitrary
Interval between two adjacent IAes is equal to the quantity of bus control unit, the fetching of at least two bus control units
Range forms first address range.
With reference to first aspect, the utility model embodiment provides the first possible embodiment of first aspect,
In, it further includes：Cache memory Cache；
The Cache is set between the bus control units of the CPU and at least two, is received for storage pre-
If quantity IA and the instruction obtained according to described instruction address, so as to when with receiving IA and described instruction
When location is any one in currently stored preset quantity IA, by storage according to the acquisition of described instruction address
Instruction is sent to the CPU.
With reference to first aspect, the utility model embodiment provides second of possible embodiment of first aspect,
In, the quantity of the Cache memory storages instruction is less than or equal to the quantity of the instruction of at least two command memory memory storages.
With reference to first aspect, the utility model embodiment provides the third possible embodiment of first aspect,
In, the corresponding command memory of the bus control unit is connected by four-wire type spi bus.
With reference to first aspect, the utility model embodiment provides the 4th kind of possible embodiment of first aspect,
In, described instruction memory is Double Data Rate synchronous DRAM DDR.
With reference to first aspect, the utility model embodiment provides the 5th kind of possible embodiment of first aspect,
In, the quantity of the bus control unit and described instruction memory is two.
With reference to first aspect, the utility model embodiment provides the 6th kind of possible embodiment of first aspect,
In, the instruction-fetching range of the bus control unit includes：IA is even address or IA is odd address.
With reference to first aspect, the utility model embodiment provides the 7th kind of possible embodiment of first aspect,
In, the quantity of the bus control unit and described instruction memory is three.
With reference to first aspect, the utility model embodiment provides the 8th kind of possible embodiment of first aspect,
In, the instruction-fetching range of the bus control unit includes：The multiple that integral multiple that IA is three, IA are three mores than one,
The multiple that IA is three mores than two etc..
Second aspect, the utility model embodiment also provide a kind of electronic equipment, including the CPU fetchings described in first aspect
System.
The utility model embodiment brings following advantageous effect：The utility model embodiment can be total to address in CPU
After line sends IA, at least two bus control units monitor IA respectively, and basis takes positioned at it respectively
IA in how goes corresponding command memory to read instruction, and CPU continual can enable different bus controller
Different fetching processes is completed, reduces the stand-by period of CPU, improves fetching efficiency.
Other feature and advantage of the utility model will illustrate, also, in the following description partly from specification
In become apparent or understood by implementing the utility model.The purpose of this utility model and other advantages are illustrating
Specifically noted structure is realized and is obtained in book, claims and attached drawing.
For the above-mentioned purpose of the utility model, feature and advantage is enable to be clearer and more comprehensible, preferred embodiment cited below particularly, and
Attached drawing appended by cooperation, is described in detail below.
Description of the drawings
It, below will be right in order to illustrate more clearly of specific embodiment of the present invention or technical solution of the prior art
Specific embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, it is described below
In attached drawing be the utility model some embodiments, for those of ordinary skill in the art, do not paying creativeness
Under the premise of labour, other attached drawings are can also be obtained according to these attached drawings.
Fig. 1 is the structure chart of CPU fetching systems that the utility model embodiment provides；
Fig. 2 is a kind of structure chart of CPU fetching systems that the utility model embodiment provides；
Fig. 3 is another structure chart of CPU fetching systems that the utility model embodiment provides；
Fig. 4 is the structure chart of electronic equipment that the utility model embodiment provides.
Specific embodiment
Purpose, technical scheme and advantage to make the utility model embodiment are clearer, below in conjunction with attached drawing to this
The technical solution of utility model is clearly and completely described, it is clear that described embodiment is that the utility model part is real
Example is applied, instead of all the embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making
All other embodiments obtained under the premise of creative work, shall fall within the protection scope of the present invention.
Since the interface of current SPI only has 1 data lines, the interface of DSPI only has 2 data lines, and the interface of QSPI only has
4 data lines, this largely can read the data volume instructed by limitation CPU, cause fetching bottleneck so that CPU often locates
In wait state, very big loss is caused to the performance of CPU, reduces the working efficiency of CPU, based on this, the utility model is implemented
Example provide a kind of CPU fetchings system and electronic equipment, can CPU to address bus send IA after, at least two
The bus control unit monitors IA respectively, and is gone accordingly according to the IA being located in its instruction-fetching range respectively
Command memory reads instruction, and CPU is obtained without waiting for upper one instruction and finished, you can is started fetching process next time, is subtracted
The stand-by period of few CPU, improve fetching efficiency.
For ease of understanding the present embodiment, first to a kind of CPU fetchings system disclosed in the utility model embodiment
System describes in detail, as shown in Figure 1, CPU fetching systems include：CPU 01, at least two bus control units 02 and with it is described
One-to-one at least two command memory 03 of bus control unit；
The CPU 01 is connect respectively at least two bus control units 02, for each bus control unit
02 sends the IA in the first address range；
In practical applications, CPU 01 can send IA to address bus, and then bus control unit 02 is from address
IA is read in bus, CPU 01, can be by each IA in the first address range when sending IA
It is sent on address bus one by one according to the incremental sequence of IA, it can also by each instruction in the first address range
Location is sent in a manner of instructing combination on address bus, and the IA in each instructing combination is continuous and quantity and total line traffic control
The quantity of device 02 processed is equal, for example, it is assumed that the quantity of bus control unit 02 is two, then the IA in instructing combination is also
Two, and should be without other IAes between the two IAes；For another example the quantity for assuming bus control unit 02 is
Three, then the IA in instructing combination is also for three, and in these three IAes the adjacent IA of each two it
Between without other IAes.
At least two bus control units 02 are distinguished corresponding command memory 03 and are connected, when described at least two
A determining described instruction address in bus control unit 02 is located in its instruction-fetching range, and the bus control unit 02 utilizes default
Described instruction address conversion is storage address by functional relation, is read in corresponding described instruction memory 03 and is stored in institute
State the instruction of storage address.
In the utility model embodiment, instruction-fetching range can refer to that IA is odd address, IA is even number
The multiple that integral multiple that address, IA are three, IA are three mores than the multiple that 1, IA is three and mores than 2 etc..Institute
The corresponding command memory 03 of bus control unit 02 is stated to connect by four-wire type spi bus.
Each bus control unit 02 after IA is read, can decision instruction address whether be located at its fetching model
In enclosing, and since the value range of each bus control unit 02 is different and the instruction-fetching range of each bus control unit 02
Interval between two IAes of interior arbitrary neighborhood is equal to the quantity of bus control unit 02, at least two bus marcos
The instruction-fetching range of device 02 forms first address range, so each bus control unit at least two bus control units 02
02 is merely able to carry out fetching according to the IA in its instruction-fetching range respectively, and each bus control unit 02 will can instruct ground respectively
Location is converted into storage address of the instruction in command memory 03, and then each bus control unit 02 goes its corresponding instruction respectively
Instruction is read at 03 memory storage address of memory.
As a preferred embodiment, as shown in Fig. 2, the quantity of bus control unit be two, command memory
Quantity is also two, and bus control unit is connected with corresponding command memory, and first IA 0 is sent to address bus in CPU
After (IA 0 is odd address), two bus control units can read the IA 0, two bus control unit meetings
Judge whether the IA 0 is located in its instruction-fetching range respectively, it is assumed that 1 corresponding instruction-fetching range of bus control unit is instruction ground
Location is odd address, and it is even address that the instruction-fetching range of bus control unit 2, which is IA, then bus control unit 1 is being read
After IA 0, it can judge whether the IA 0 is odd address, similarly, bus control unit 2 can judge the IA 0
Whether it is even address, since IA 0 is odd address, is taken so bus control unit 1 can determine whether that the IA is located at
In how, then IA can be converted into storage address of the instruction in command memory, Jin Ercong by bus control unit 1
Storage address reads instruction in its corresponding command memory, is taken since bus control unit 2 determines that the IA is not located at
In how, so bus control unit 2 terminates process flow.
After CPU sends IA 1 (IA 1 is even address) to address bus, two bus control units are equal
The IA 1 can be read, two bus control units can judge whether the IA 1 is located in its instruction-fetching range respectively,
Assuming that it is odd address that the instruction-fetching range of bus control unit 1, which is IA, the instruction-fetching range of bus control unit 2 is IA
For even address, then bus control unit 1 can judge whether the IA 1 is located at its fetching model after IA 1 is read
In enclosing, similarly, bus control unit 2 can judge whether the IA 1 is located in its instruction-fetching range, since IA 1 is even
Number address, so bus control unit 1 can determine whether that the IA is not located in instruction-fetching range and terminates process flow, bus marco
Device 2 can determine whether that the IA is located in instruction-fetching range, and then IA can be converted into instruction and instructed by bus control unit 2
Storage address in memory, and then storage address reads 2 meeting of instruction bus controller from its corresponding command memory
Instruction is read from its corresponding command memory.
In the utility model embodiment, the preset function relational expression of each bus control unit is different, due to difference
The IA of bus control unit processing is different, so to IA is converted into command memory continuously
Location needs different functional relations to convert, for example, when only existing two bus control units and two command memories,
Then the preset function relational expression of bus control unit 1 can be：Storage address=IA/2, the default letter of bus control unit 2
Counting relational expression can be：Storage address=(IA+1)/2.
Similarly, it is assumed that the quantity of bus control unit is three, when the quantity of command memory is also three, in IA
The multiple that integral multiple, IA for three are three more than the multiple that 1, IA is three more than 2 when, there are three bus marcos respectively
Device reads instruction in corresponding command memory.
The quantity of bus control unit may be set according to actual conditions, and the utility model does not limit.Described instruction stores
Device can be Double Data Rate synchronous DRAM DDR, be read in command memory in order to accelerate bus control unit
The speed of instruction.
The utility model embodiment can be in CPU after address bus sends IA, at least two total line traffic controls
Device processed monitors IA respectively, and removes corresponding command memory according to the IA being located in its instruction-fetching range respectively
Instruction is read, CPU is obtained without waiting for upper one instruction and finished, you can is started fetching process next time, is reduced the waiting of CPU
Time improves fetching efficiency.
In the another embodiment of the utility model, as shown in figure 3, the CPU fetchings system, further includes：Speed buffering
Memory Cache 04；
The cache memory Cache 04 is set between the bus control units of the CPU and at least two,
I.e. described Cache 04 can receive the IA of CPU transmissions and each bus control unit is read according to IA
Instruction, and can storing IA is corresponding with instruction, for the preset quantity IA that receives of storage and according to
The instruction that described instruction address obtains, to be currently stored preset quantity when receiving IA and described instruction address
During any one in a IA, the instruction obtained according to described instruction address of storage is sent to the CPU.
In the utility model embodiment, the quantity of 04 memory storages of the Cache instruction is less than or equal at least two
The quantity of the instruction of command memory memory storage, those skilled in the art could be aware that, the quantity of Cache memory storages instruction
More, CPU fetching speed is faster.
For each bus control unit, inside can perform following CPU fetching methods, the method includes walking as follows
Suddenly.
Step S101 receives the IA in the first address range that CPU is sent；
Step S102, judges whether described instruction address is located in its instruction-fetching range；
When described instruction address is located in its instruction-fetching range, step S103, using preset function relational expression by the finger
Address conversion is enabled as storage address, in the instruction-fetching range of the bus control unit between two IAes of arbitrary neighborhood between
Every the quantity equal to bus control unit；
Step S104 reads the instruction for being stored in the storage address in corresponding described instruction memory.
The step S102 may comprise steps of.
Judge whether described instruction address is odd address；When described instruction address is odd address, the finger is determined
Address is enabled to be located at its instruction-fetching range.
Alternatively, the step S102 may comprise steps of.
Judge whether described instruction address is even address；When described instruction address is even address, the finger is determined
Address is enabled to be located at its instruction-fetching range.
As shown in figure 4, in the another embodiment of the utility model, a kind of electronic equipment 05 is also provided, including such as aforementioned
CPU fetchings system 06 described in embodiment.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description
With the specific work process of device, the corresponding process in preceding method embodiment can be referred to, details are not described herein.
In addition, in the description of the utility model embodiment unless specifically defined or limited otherwise, term " installation ",
" connected ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected or integrally connect
It connects；Can be mechanical connection or electrical connection；It can be directly connected, can also be indirectly connected by intermediary, it can
To be the connection inside two elements.For the ordinary skill in the art, can above-mentioned term be understood with concrete condition
Concrete meaning in the utility model.
If the function is realized in the form of SFU software functional unit and is independent product sale or in use, can be with
It is stored in a computer read/write memory medium.Based on such understanding, the technical solution of the utility model substantially or
Person says that the part of the part contribute to the prior art or the technical solution can be embodied in the form of software product,
The computer software product is stored in a storage medium, and being used including some instructions (can be with so that computer equipment
Be personal computer, server or the network equipment etc.) perform the whole or portion of each embodiment the method for the utility model
Step by step.And aforementioned storage medium includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), with
Various Jie that can store program code such as machine access memory (RAM, Random Access Memory), magnetic disc or CD
Matter.
In the description of the present invention, it should be noted that term " " center ", " on ", " under ", it is "left", "right", " perpendicular
Directly ", the orientation of the instructions such as " level ", " interior ", " outer " or position relationship are based on orientation shown in the drawings or position relationship, are only
The utility model must have specific with the device or element for simplifying description rather than instruction or hint meaning for ease of description
Orientation, with specific azimuth configuration and operation, therefore it is not intended that limitation to the utility model.In addition, term " the
One ", " second ", " third " are only used for description purpose, and it is not intended that instruction or hint relative importance.
Finally it should be noted that：Embodiment described above, only specific embodiment of the present utility model, to illustrate this
The technical solution of utility model, rather than its limitations, the scope of protection of the utility model is not limited thereto, although with reference to aforementioned
The utility model is described in detail in embodiment, it will be understood by those of ordinary skill in the art that：It is any to be familiar with this skill
It, still can be to the skill recorded in previous embodiment in the technical scope that the technical staff in art field discloses in the utility model
Art scheme, which is modified or can be readily occurred in, to be changed or carries out equivalent replacement to which part technical characteristic；And these modifications,
Variation is replaced, the spirit and model of the utility model embodiment technical solution that it does not separate the essence of the corresponding technical solution
It encloses, should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model described should be wanted with right
Subject to the protection domain asked.
Claims (10)
1. a kind of CPU fetchings system, which is characterized in that including：CPU, at least two bus control units and with the bus marco
One-to-one at least two command memory of device；
The CPU is connect respectively at least two bus control units, for being sent not to the different bus control units
Same IA；
At least two bus control units distinguish corresponding command memory connection, and the bus control unit is according to
IA reads instruction in corresponding described instruction memory.
2. CPU fetchings system according to claim 1, which is characterized in that further include：Cache memory Cache；
The Cache is set between the bus control units of the CPU and at least two, for storing the present count received
Amount IA and the instruction obtained according to described instruction address, so as to when receiving IA and described instruction address is
During any one in currently stored preset quantity IA, by the instruction obtained according to described instruction address of storage
It is sent to the CPU.
3. CPU fetchings system according to claim 2, which is characterized in that the quantity of the Cache memory storages instruction is less than
Or the quantity of the instruction equal at least about two command memory memory storages.
4. CPU fetchings system according to claim 3, which is characterized in that the corresponding instruction of the bus control unit
Memory is connected by four-wire type spi bus.
5. CPU fetchings system according to claim 4, which is characterized in that described instruction memory is synchronized for Double Data Rate
Dynamic RAM DDR.
6. CPU fetchings system according to claim 5, which is characterized in that the bus control unit and described instruction storage
The quantity of device is two.
7. CPU fetchings system according to claim 6, which is characterized in that the instruction-fetching range of the bus control unit includes：
IA is even address or IA is odd address.
8. CPU fetchings system according to claim 5, which is characterized in that the bus control unit and described instruction storage
The quantity of device is three.
9. CPU fetchings system according to claim 8, which is characterized in that the instruction-fetching range of the bus control unit includes：
The multiple that integral multiple that IA is three, IA are three mores than the multiple that one, IA is three and mores than two.
10. a kind of electronic equipment, which is characterized in that including the CPU fetching systems as described in claim 1 to 9 is any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721135986.9U CN207529371U (en) | 2017-09-06 | 2017-09-06 | CPU fetchings system and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721135986.9U CN207529371U (en) | 2017-09-06 | 2017-09-06 | CPU fetchings system and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207529371U true CN207529371U (en) | 2018-06-22 |
Family
ID=62575852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721135986.9U Active CN207529371U (en) | 2017-09-06 | 2017-09-06 | CPU fetchings system and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207529371U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107562658A (en) * | 2017-09-06 | 2018-01-09 | 北京融通高科微电子科技有限公司 | CPU fetchings system and fetching method |
-
2017
- 2017-09-06 CN CN201721135986.9U patent/CN207529371U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107562658A (en) * | 2017-09-06 | 2018-01-09 | 北京融通高科微电子科技有限公司 | CPU fetchings system and fetching method |
| CN107562658B (en) * | 2017-09-06 | 2024-05-28 | 北京世通凌讯科技有限公司 | CPU finger picking system and finger picking method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10114749B2 (en) | Cache memory system and method for accessing cache line | |
| CN107562672B (en) | System and method for improving data transmission rate of vector network analyzer | |
| US9569381B2 (en) | Scheduler for memory | |
| CN101794271A (en) | Implementation method and device of consistency of multi-core internal memory | |
| US20170091127A1 (en) | Techniques to Couple with a Storage Device via Multiple Communication Ports | |
| CN110647292B (en) | Method and system for expanding storage capacity in server system | |
| CN202257553U (en) | Protocol converter for converting universal serial port to MODBUS | |
| CN106489132A (en) | The method of read-write data, device, storage device and computer system | |
| CN106407145A (en) | An interface access method and system and a memory card | |
| CN107329929B (en) | Data transmission system and data transmission method based on SoC FPGA | |
| CN207529371U (en) | CPU fetchings system and electronic equipment | |
| CN110515343B (en) | Communication connection device, programmable logic controller, communication method and product | |
| CN104111908A (en) | USB device, working system, working mode conversion method and data communication method | |
| CN101783165A (en) | Semiconductor memory, semiconductor memory system and corresponding programming method | |
| CN103678056A (en) | Method for testing control function of PCIE bus equipment | |
| CN104951237A (en) | High-speed storage device based on SATA interface solid state disk | |
| CN114641763B (en) | Protocol converter module system and method for using the same | |
| CN104182181A (en) | Data processing method, device and terminal of memory card | |
| CN101594719B (en) | Offline control device | |
| CN101094076B (en) | Multiplex communication server in Ethernet and control method | |
| CN107562658A (en) | CPU fetchings system and fetching method | |
| CN208547908U (en) | Store the electric power controller of equipment | |
| CN113032300A (en) | Data transmission control method | |
| CN202435022U (en) | Electrified railway traction network microcomputer feed line protection device | |
| CN106057226B (en) | The access control method of dual-port storage system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220824 Address after: Room 1302-2, 13th Floor, Building 1, No. 1 Shangdi Information Road, Haidian District, Beijing 100089 Patentee after: Beijing Shitong lingxun Technology Co.,Ltd. Address before: 100085 203-06, 2nd floor, 39 Xierqi street, Haidian District, Beijing Patentee before: BEIJING RT-HITECH MICROELECTRONIC TECHNOLOGY CO.,LTD. |
|
| TR01 | Transfer of patent right |