CN113098472A - Sampling circuit and method - Google Patents
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Abstract
A sampling circuit and a sampling method are provided. The sampling circuit includes a differentiating circuit and a signal converting circuit. The differentiating circuit is used for differentiating the first digital signal into a second digital signal. The first digital signal has an input frequency. The signal conversion circuit is used for converting the second digital signal into a digital output signal. The digital output signal has a sampling frequency, and the input frequency is different from the sampling frequency. The signal conversion circuit comprises an accumulation circuit and an addition circuit. The accumulation circuit is used for accumulating the second digital signal in the time interval into a third digital signal. The adder circuit is used for generating a digital output signal according to the third digital signal, the input frequency and the sampling frequency. The sampling circuit and the method can perform the conversion of the sampling frequency with low operand and high signal-to-noise ratio on the original digital signal with frequency offset, achieve the aim of obtaining the digital signal without frequency offset or with low frequency offset, and also can avoid the problem that the operation load of the sampling circuit is greatly improved when an interpolation/extraction method is used for converting the sampling frequency of the signal.
Description
Technical Field
The present disclosure relates to a sampling circuit, and more particularly, to a sampling circuit using a differential circuit.
Background
As signal transmission technology is becoming more and more advanced, the speed of signals is becoming faster and faster, and when a circuit is sampling a received signal, the function of sampling in the circuit is becoming more and more critical in order to avoid frequency offset, because clock frequency offset in the high-speed transmitted signal is becoming more and more significant.
Disclosure of Invention
One embodiment of the present disclosure relates to a sampling circuit, which includes a differentiating circuit and a signal converting circuit. The differentiating circuit is used for differentiating the first digital signal into a second digital signal. The first digital signal has an input frequency. The signal conversion circuit is used for converting the second digital signal into a digital output signal. The digital output signal has a sampling frequency, and the input frequency is different from the sampling frequency. The signal conversion circuit comprises an accumulation circuit and an addition circuit. The accumulation circuit is used for accumulating the second digital signal in the time interval into a third digital signal. The adder circuit is used for generating a digital output signal according to the third digital signal, the input frequency and the sampling frequency.
One embodiment of the present disclosure relates to a sampling method, which includes the following operations. Performing, by a differentiation circuit, an X-order differentiation on the first digital signal to generate a second digital signal; and performing, by the signal processing circuit, Y-order integration on the second digital signal to generate a digital output signal. X and Y are positive integers, and X plus 1 is greater than or equal to Y. The first digital signal has an input frequency, the digital output signal has a sampling frequency, and the input frequency is different from the sampling frequency. Performing a Y-order integration on the second digital signal comprises: accumulating the second digital signal into a plurality of accumulated signals according to the input frequency and the sampling frequency in the time interval; and summing the accumulated signal into a digital output signal according to the input frequency and the sampling frequency.
In summary, the sampling circuit and the method provided by some embodiments of the present disclosure can perform signal resampling with low computation and high snr under the condition that the original digital signal has a frequency offset, so as to achieve the purpose of obtaining a digital signal without a frequency offset or with a reduced frequency offset. The method can also avoid the problem that the operation load of the sampling circuit for converting the sampling frequency by an interpolation/extraction mode is greatly improved.
Drawings
The disclosure may be more completely understood in consideration of the following detailed description of embodiments in connection with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a sampling circuit according to some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of a frequency spectrum of the differentiating circuit shown in FIG. 1 according to some embodiments of the present disclosure;
FIG. 3 is a schematic diagram of a frequency spectrum of the signal conversion circuit shown in FIG. 1 according to some embodiments of the present disclosure;
FIG. 4 is a schematic diagram of a frequency spectrum of the sampling circuit shown in FIG. 1 according to some embodiments of the present disclosure;
FIG. 5 is a schematic diagram of a sampling circuit shown in accordance with some embodiments of the present disclosure;
FIG. 6 is a schematic diagram of a sampling circuit according to some other embodiments of the present disclosure; and
fig. 7 is a flow chart of a sampling method shown in accordance with some embodiments of the present disclosure.
Description of the symbols
100 sampling circuit
110A/D converter
120 differential circuit
121 differentiator
130 signal conversion circuit
131 accumulation circuit
131a accumulator
132D/A converter
133 adder circuit
133a adder
134 integrating circuit
136 analog-to-digital converter
140 filter circuit
x (t) analog signal
xi (t) input signal
x (n) digital signal
x1(n) digital signal
xp (t) analog signal
xac1 summation of signals
xac2 summation of signals
xac3 summation of signals
xac4 summation of signals
z1 integral signal
z2 integral signal
z3 integral signal
z4 integral signal
z (n) digital signal
D delayer
S integrator
Coefficient of d
800 method
S810 operation
S820 operation
S830 operation
S840 operation
Detailed Description
The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are only for explaining the embodiments of the present disclosure and not for limiting the present disclosure, and the description of the structural operation is not for limiting the execution sequence thereof, and any structure obtained by recombining the elements to have equivalent technical effects is included in the scope of the disclosure of the embodiments of the present disclosure.
As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to two or more elements operating or acting together.
Refer to fig. 1. Fig. 1 is a schematic diagram illustrating a sampling circuit 100 according to some embodiments of the present disclosure. The sampling circuit 100 is used to sample the analog signal x (t) and output it as the output signal z (n). The output signal z (n) is a digital signal having a sampling frequency Fs.
As shown in fig. 1, the sampling circuit 100 includes an analog-to-digital converter 110, a differentiating circuit 120, and a signal converting circuit 130. The analog-to-digital converter 110 is coupled to the differentiating circuit 120, and the differentiating circuit 120 is coupled to the signal converting circuit 130.
In some embodiments, the adc 110 receives the analog signal x (t) and converts the analog signal x (t) into a digital signal x (n). The digital signal x (n) has an input frequency that is different from the sampling frequency Fs.
In some embodiments, the differentiating circuit 120 receives the digital signal x (n) and differentiates the digital signal x (n) into the digital signal x1 (n). The differentiating circuit 120 includes an X-order differentiator 121 for performing an X-order differentiation on the digital signal X (n). As shown in fig. 1, the differentiating circuit 120 is a 4 th order differentiating circuit, which includes 4 differentiators 121 connected in series. The differentiating circuit 120 receives the digital signal x (n), a first differentiator 121 differentiates the digital signal x (n) into a first digital differentiated signal, a second differentiator 121 differentiates the first digital differentiated signal into a second digital differentiated signal, a third differentiator 121 differentiates the second digital differentiated signal into a third digital differentiated signal, and a fourth differentiator 121 differentiates the third digital differentiated signal into a digital signal x1 (n).
As shown in fig. 1, the differentiator 121 comprises a delay D for subtracting the currently received signal from the previously received signal. Taking the first differentiator 121 as an example, the differentiator 121 receives the digital signal x (n), the delay D delays the digital signal x (n) by a unit time period, and the differentiator 121 receives the digital signal x (n + 1). The differentiator 121 subtracts the digital signal x (n +1) from the digital signal x (n) at a node, and outputs the result as a first digital differentiated signal to the second differentiator 121. The other differentiators 121 have similar functions and will not be described herein.
In some embodiments, the signal conversion circuit 130 is configured to convert the digital signal x1(n) into the output signal z (n). The signal conversion circuit 130 includes a digital-to-analog converter 132, an integration circuit 134, and an analog-to-digital converter 136. In some embodiments, the digital-to-analog converter 132 is configured to convert the digital signal x1(n) into an analog signal xp (t), the integrating circuit 134 is configured to integrate the analog signal xp (t) into an analog signal z (t), and the analog-to-digital converter 136 is configured to convert the analog signal z (t) into an output signal z (n) of the new sampling frequency.
In some embodiments, the integration circuit 134 comprises a Y-stage integrator S for performing Y-stage integration on the analog signal xp (t). As shown in fig. 1, the integrator circuit 134 is a 4 th-order integrator circuit, the first integrator S integrates the analog signal xp (t) into a first integrated signal z1, the second integrator S integrates the first integrated signal z1 into a second integrated signal z2, the third integrator S integrates the second integrated signal z2 into a third integrated signal z3, and the fourth integrator S integrates the third integrated signal z3 into a fourth integrated signal z 4.
In some embodiments, the order X of the differentiating circuit 120 has a relationship of X +1 ≧ Y with the order Y of the integrating circuit 130 for stabilization of the sampling circuit. The above-mentioned orders of the differentiating circuit 120 and the integrating circuit 130 are for illustrative purposes only, and various orders X, Y are within the scope and the scope of the present disclosure. For example, X and Y are 7 th order.
In some embodiments, sampling circuit 100 includes a delta-sigma circuit implemented with at least a differentiation circuit 120, an analog-to-digital converter 132, and an integration circuit 134.
Refer to fig. 2. Fig. 2 is a spectral schematic of the differentiating circuit 120 shown in fig. 1 according to some embodiments of the present disclosure. In some embodiments, the differentiating circuit 120 has a spectrum as shown in fig. 2, which may be a digital signal x (n) filtered into a digital signal x1(n) according to the spectrum. As shown in fig. 2, the differentiating circuit 120 attenuates the sampling frequency Fs of 0 times, the sampling frequency Fs of 1 times, and the sampling frequency Fs of 2 times (i.e., the sampling frequency Fs of an integral multiple).
Refer to fig. 3. Fig. 3 is a schematic diagram of a frequency spectrum of the signal conversion circuit 130 shown in fig. 1 according to some embodiments of the present disclosure. In some embodiments, the signal conversion circuit 130 has a spectrum as shown in fig. 3, which may be a filter for filtering the digital signal x1(n) into the analog signal z (t) according to the spectrum. As shown in FIG. 3, the spectra of FIGS. 3 and 2 have an approximately reversible relationship in the interval of [ -Fs/2, Fs/2 ]. The signal conversion circuit 130 amplifies a low frequency signal (around the sampling frequency Fs of 0 times) and attenuates a high frequency signal (the sampling frequency Fs of 1 time, the sampling frequency Fs of 2 times, and so on) further, and the distance between the attenuation of the signal and the sampling frequency Fs increases exponentially.
Refer to fig. 4. Fig. 4 is a spectral schematic of the sampling circuit 100 shown in fig. 1 according to some embodiments of the present disclosure. In some embodiments, the frequency spectrum of the sampling circuit 100 is a superposition of the frequency spectrum of the differentiating circuit 120 shown in fig. 2 and the frequency spectrum of the signal converting circuit 130 shown in fig. 3. As shown in FIG. 4, the spectrum has a flat characteristic in the range of + -Fs/2. That is, the sampling circuit 100 is a low-pass filter, which can effectively recover the digital signal to the analog signal z (t), and then re-sample to obtain the output z (n) of the new sampling frequency.
Refer back to fig. 1. The process by which signal conversion circuit 130 converts digital signal x1(n) into output signal z (n) can be expressed as a mathematical equation that can be used to derive the specific circuit implementation of fig. 5. When the digital signal x1(n) is converted into the analog signal xp (t) by the digital-to-analog converter 132, it can be represented by equation eq 1.
Where T is the period of the digital signal x1(n), i.e., the reciprocal of the input frequency of the digital signal x1 (n). The integration circuit 134 integrates the analog signal xp (t), and outputs a fourth integrated signal z4 ═ z (t). The fourth integrated signal z4 is a 4-order integral of the analog signal xp (t), wherein the first integrated signal z1, the second integrated signal z2, the third integrated signal z3 and the fourth integrated signal z4 can be expressed by a state transition equation eq 2.
Where z1 '(t) -z 4' (t) is the differential of z1(t) -z 4(t), state transition equation eq2 is expressed in equation eq3 for convenience of calculation.
Z′(t)＝A·Z(t)+B·xp(t) eq3
Then, Laplace transform (Laplace transform) is performed on equation eq3 to obtain equation eq 4.
Z(S)＝(sI-A)-1·Z(0)+(sI-A)-1·B·X(S) eq4
Then, the equation eq4 is subjected to laplace inverse transformation, and the equation eq1 is used to expand xp (t) to obtain the equation eq 5.
Wherein H (t) and xp (t) are represented by the following formulae.
And H (t) has the property of a matrix exponential function: h (t1+ t2) ═ H (t1) × H (t 2). By using this property, the relationship between z (t) at two time points t1 and t2 can be expressed by equation eq 6.
Where the second term of equation eq6 is the summation of the digital signals x1(n) between time points t1 and t2, where H (: 1) is the first row of the H matrix. Sampling z (T) with an output frequency of 1/T' (i.e., sampling frequency Fs) results in two adjacent sampling points: t1 ═ k × T ', T2 ═ k +1) T'. Substituting T1 ═ k × T ', and T2 ═ k +1) T' into equation eq6 yields equation eq 7.
Where dn ═ [ (k +1) T' -nT ], then normalizing the period T of the digital signal x1(n) in equation eq7, equation eq8 can be obtained.
Where d is T '/T, the relationship between dn and T'/T is expressed by equation eq 9.
It can be seen that z (k +1) is only related to the last states z (k) and T'/T, and that z (k) is related to the digital signal x1(n) occurring in the z (k +1) time interval.
As shown in the above equations eq 1-eq 9, the signal conversion circuit 130 can perform signal conversion according to the result of equation eq 8. The signal conversion circuit 130 resets the accumulation operation after the accumulation is finished according to the input frequency (1/T) and the sampling frequency Fs (1/T') of the digital signal x1(n) and the digital signal x1(n) between the accumulation z (k) and z (k +1), so that the work load of the circuit is reduced, and a large amount of integrated data does not need to be processed.
Refer to fig. 5. Fig. 5 is a schematic diagram of a sampling circuit 100 according to further embodiments of the present disclosure. In some embodiments, the signal conversion circuit 130 in the sampling circuit 100 is set according to the result of the above equation eq 8.
As shown in fig. 5, the sampling circuit 100 includes a differentiating circuit 120 and a signal converting circuit 130. The differentiating circuit 120 is the same as the differentiating circuit 120 in fig. 1, and will not be described herein. The signal conversion circuit 130 in fig. 5 includes an accumulation circuit 131 and an addition circuit 133. The summation circuit 131 is used for accumulating the digital signal x1(n) in a time interval and transmitting the accumulated digital signal x1(n) to the summation circuit 133. The adder circuit 133 generates the output signal z (n) according to the accumulated digital signal x1(n), the frequency (1/T) of the digital signal x (n), and the sampling frequency Fs (1/T').
In some embodiments, the accumulation circuit 131 comprises a plurality of accumulators 131a, each accumulator 131a comprising a delay D. As shown in fig. 5, the accumulation circuit 131 comprises four accumulators 131a corresponding to the equation eq8, wherein each accumulator 131a is responsible for multiplying the accumulated digital signal x1(nT) by four coefficients (1, d) in the matrixn、dn 2/2、dn 3/6) to generate the accumulated signals xac 1-xac 4. For example, the accumulator 131a corresponding to the coefficient 1 is the lowest accumulator 131a in FIG. 5, which is used for accumulating in the time interval (kT'<nT ≦ (k +1) T') digital signal x1(nT) to generate the accumulated signal xac 1. Another example, corresponding to coefficient dn 3Accumulator 131a of/6 is the uppermost accumulator 131a of FIG. 5, which is used to accumulate in (kT'<Multiplying the digital signal x1(nT) of nT ≦ (k +1) T') by a coefficient dn 3/6 to produce an accumulated signal xac4, wherein the coefficient dn 3The input frequencies (1/T) of/6 and x1(n) are related to the sampling frequency Fs (1/T').
In some embodiments, the adder circuit 133 includes a plurality of adders 133a, each adder 133a including one delay D. As shown in fig. 5, the adder circuit 133 comprises four adders 133a corresponding to the equation eq8, wherein each adder 133a is used for generating the first integrated signal z1, the second integrated signal z2, the third integrated signal z3 and the fourth integrated signal z4, respectively. For example, the leftmost adder 133a in fig. 5 is used to add the first row of equation eq8, i.e., add z1(k) and the accumulated signal xca1 generated by the bottommost accumulator 133a is z1(k + 1). For another example, the rightmost adder 133a in fig. 5 is used to add the fourth row of the equation eq8, i.e. add z1(k), z2(k), z3(k) and z4(k) by multiplying the corresponding coefficients (d) respectively3/6、d 22, d, 1) and the accumulated signal xac4 generated by the uppermost accumulator 133a is z4(k + 1). The adding circuit 133 is used to output z4 as an output signal z (n).
In some embodiments, the adder circuit 133 resets the accumulator circuit 131 after the time interval is over, so that the accumulator circuit 131 recalculates the accumulated signals xac 1-xac 4.
In some embodiments, the first integrated signal z1, the second integrated signal z2, the third integrated signal z3 and the fourth integrated signal z4 are also referred to as addition signals.
Compared to fig. 1, the first integrated signal z1, the second integrated signal z2, the third integrated signal z3 and the fourth integrated signal z4 in fig. 1 are analog signals, and the first integrated signal z1, the second integrated signal z2, the third integrated signal z3 and the fourth integrated signal z4 in fig. 5 are digital signals. The signal conversion circuit 130 in fig. 5 directly processes the digital signal x1(n) and outputs as the output signal z (n), wherein the operation does not convert the signal into an analog signal.
In some embodiments, when the input digital signal x (n) is an over-sampled signal, the sampling circuit can achieve a better signal-to-noise ratio. The oversampling rate osr (sampling rate) (/) is the sampling frequency/(maximum frequency of the analog signal) × 2. When the oversampling rate OSR is high, the multi-tone power ratio (MTPR) of the signal can be increased in the multi-carrier system.
Refer to fig. 6. Fig. 6 is a schematic diagram of a sampling circuit 100 according to some other embodiments of the present disclosure. Compared to the sampling circuit 100 in fig. 5, the sampling circuit 100 in fig. 6 further includes a filter circuit 140, and the filter circuit 140 can increase the over-sampling rate OSR of the input signal x (n) by interpolation filtering. The filter circuit 140 is coupled to the differentiating circuit 120.
In some embodiments, the filter circuit 140 is configured to receive the input signal xi (n) and interpolate the input signal xi (n) to generate the digital signal x (n), so that the input frequency of the digital signal x (n) is greater than the frequency of the input signal xi (n), thereby increasing the over-sampling rate OSR of the input signal of the sampling circuit.
Compared to the sampling circuit 100 of fig. 5, the sampling circuit 100 of fig. 6 interpolates the signal into a signal with a higher frequency in advance, and then performs the subsequent operations of the differentiating circuit 120 and the signal processing circuit 130. Therefore, the OSR of the sampling circuit 100 in fig. 6 is higher than that of the sampling circuit 100 in fig. 5 due to the filter circuit 140, which helps to increase the MTPR of the sampling circuit 100.
Refer to fig. 7. Fig. 7 is a flow diagram illustrating a sampling method 700 according to some embodiments of the present disclosure. In some embodiments, the sampling method 700 is used to sample the input signal xi (n) and output the output signal z (n), wherein the sampling frequency Fs of the output signal z (n) is different from the frequency of the input signal xi (n), so as to achieve the purpose of converting the sampling frequency and eliminating or reducing the frequency offset. In some embodiments, the sampling method 700 is implemented by at least part of the sampling circuit 100 of fig. 1, 5, 6. As shown in fig. 7, the sampling method 700 includes operations S710, S720, S730, and S740.
In operation S710, the input signal xi (n) is interpolated by the filter circuit 140 to generate a digital signal x (n) such that the digital signal x (n) has a higher frequency than the input signal xi (n). In other words, in operation S710, the frequency of the input signal xi (n) is increased by the filter circuit 140 to output as the digital signal x (n).
In operation S720, an X-order differentiation is performed on the digital signal X (n) by the differentiating circuit 120 to generate a digital signal X1 (n). X is a positive integer.
In operation S730, the accumulation circuit 131 accumulates the digital signal x1(n) according to the input frequency of the digital signal x1(n) and the sampling frequency Fs to obtain accumulated signals xac1 to xac4 within a time interval, wherein the time interval is the inverse of the sampling frequency Fs, i.e., the period of the output signal z (n).
In operation S740, the summation signal xac 1-xac 4 and the integration signal z 1-z 4 are added to the output signal z (n) by the adder circuit 133 according to the input frequency of the digital signal x1(n) and the sampling frequency Fs.
In some embodiments, operations S730 and S740 are performed by the signal processing circuit 130, which is equivalent to performing Y-order integration on the digital signal x1(n) to generate the output signal z (n). Y is a positive integer. In some embodiments, X +1 is greater than or equal to Y.
The figures described above contain exemplary operations, but the operations are not limited to the order shown. Operations may be added, substituted, changed in order, and/or omitted as appropriate in accordance with the considerations and scope of embodiments of the present disclosure.
The figures described above contain exemplary operations, but the operations are not limited to the order shown. Operations may be added, substituted, changed in order, and/or omitted as appropriate in accordance with the considerations and scope of embodiments of the present disclosure.
In some embodiments, a sampling circuit includes a differentiation circuit and a signal conversion circuit. The differentiating circuit is used for differentiating the first digital signal into a second digital signal. The first digital signal has an input frequency. The signal conversion circuit is used for converting the second digital signal into an output signal. The output signal has a sampling frequency. The signal conversion circuit comprises an accumulation circuit and an addition circuit. The accumulation circuit is used for accumulating the second digital signal in the time interval into a plurality of accumulation signals. The adder circuit is used for generating an output signal according to the accumulation signal, the input frequency and the sampling frequency.
In various embodiments, in the above-mentioned sampling circuit, the differentiating circuit includes a first differentiator and at least a second differentiator. The first differentiator is used for differentiating the first digital signal. The at least one second differentiator is used for differentiating the first digital signal differentiated by the first differentiator to generate a second digital signal.
In various embodiments, in the sampling circuit, the accumulation circuit includes a first accumulator and at least one second accumulator. The first accumulator is used for accumulating the second digital signal in the time interval into a first accumulated signal in the accumulated signals. The at least one second accumulator is used for accumulating a second digital signal in the time interval according to the input frequency and the sampling frequency to be a second accumulated signal in the accumulated signals.
In various embodiments, in the sampling circuit, the adding circuit includes a first adder and at least one second adder. The first adder is used for generating a first addition signal according to the first accumulation signal. The at least one second adder is used for generating an output signal according to the input frequency, the sampling frequency, the first addition signal and the second accumulation signal.
In various embodiments, in the above-mentioned sampling circuit, the adding circuit is further configured to reset the accumulating circuit after the accumulating circuit accumulates the second digital signal within the time interval.
In various embodiments, the sampling circuit further includes a filter circuit. The filter circuit is used for interpolating an input signal to generate a first digital signal. The input frequency of the first digital signal is greater than the frequency of the input signal.
In various embodiments, in the above sampling circuit, the differentiating circuit is an X-order differentiating circuit, and the signal converting circuit is a Y-order integrating circuit. X plus 1 is greater than or equal to Y, and X and Y are positive integers.
In some embodiments, a sampling method includes the operations of: performing, by a differentiation circuit, an X-order differentiation on the first digital signal to generate a second digital signal; and performing, by the signal processing circuit, Y-order integration on the second digital signal to generate an output signal. X and Y are positive integers, and X plus 1 is greater than or equal to Y. The first digital signal has an input frequency, the output signal has a sampling frequency, and the input frequency is different from the sampling frequency. Performing a Y-order integration on the second digital signal comprises: accumulating the second digital signal into a plurality of accumulated signals according to the input frequency and the sampling frequency in the time interval; and summing the accumulated signal into an output signal according to the input frequency and the sampling frequency.
In various embodiments, the sampling method further includes interpolating the input signal to increase the frequency of the input signal, and outputting the interpolated input signal as the first digital signal.
In various embodiments, in the above sampling method, the time interval is a period of the output signal.
Although the embodiments of the present disclosure have been described in detail, it should be understood that they have been presented by way of example only, and not limitation, and that various changes, modifications and alterations can be made therein by those skilled in the art without departing from the spirit and scope of the embodiments of the present disclosure.
Claims (10)
1. A sampling circuit, comprising:
a differentiating circuit for differentiating a first digital signal into a second digital signal, wherein the first digital signal has an input frequency; and
a signal conversion circuit for converting the second digital signal into an output signal, wherein the output signal has a sampling frequency, and the input frequency is different from the sampling frequency, the signal conversion circuit comprising:
an accumulation circuit for accumulating the second digital signal in a time interval into a plurality of accumulated signals; and
an adder circuit for generating the output signal according to the accumulated signal, the input frequency and the sampling frequency.
2. The sampling circuit of claim 1, wherein the differentiating circuit comprises:
a first differentiator for differentiating the first digital signal; and
at least one second differentiator for differentiating the first digital signal differentiated by the first differentiator to generate the second digital signal.
3. The sampling circuit of claim 1, wherein the accumulation circuit comprises:
a first accumulator for accumulating the second digital signal in the time interval as a first accumulated signal of the accumulated signals; and
at least one second accumulator for accumulating the second digital signal in the time interval as a second accumulated signal of the accumulated signals according to the input frequency and the sampling frequency.
4. The sampling circuit of claim 3, wherein the summing circuit comprises:
a first adder for generating a first addition signal according to the first accumulation signal; and
at least one second adder for generating the output signal according to the input frequency, the sampling frequency, the first addition signal and the second accumulation signal.
5. The sampling circuit of claim 1, wherein the summing circuit is further configured to reset the summing circuit after the summing circuit has summed the second digital signal over the time interval.
6. The sampling circuit of claim 1, further comprising:
the filter circuit is used for interpolating an input signal to generate the first digital signal, wherein the input frequency of the first digital signal is greater than a frequency of the input signal.
7. The sampling circuit of claim 1, wherein the differentiating circuit is an X-order differentiating circuit and the signal converting circuit is a Y-order integrating circuit, wherein X plus 1 is greater than or equal to Y, and X and Y are positive integers.
8. A method of sampling, comprising:
performing X-order differentiation on a first digital signal through a differentiating circuit to generate a second digital signal; and
performing Y-order integration on the second digital signal through a signal processing circuit to generate an output signal,
wherein X and Y are positive integers and X plus 1 is greater than or equal to Y,
the first digital signal has an input frequency, the output signal has a sampling frequency, the input frequency is different from the sampling frequency, an
Performing a Y-order integration on the second digital signal comprises:
accumulating the second digital signal into a plurality of accumulated signals according to the input frequency and the sampling frequency within a time interval; and
and summing the accumulated signal into the output signal according to the input frequency and the sampling frequency.
9. The sampling method of claim 8, further comprising:
an input signal is interpolated to increase a frequency of the input signal and the interpolated input signal is output as the first digital signal.
10. The sampling method of claim 8, wherein the time interval is a period of the output signal.
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| CN201911336321.8A CN113098472B (en) | 2019-12-23 | 2019-12-23 | Sampling circuit and method |
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