CN212231426U - Digital decimation filter and analog-to-digital converter - Google Patents
Digital decimation filter and analog-to-digital converter Download PDFInfo
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- CN212231426U CN212231426U CN202021735367.5U CN202021735367U CN212231426U CN 212231426 U CN212231426 U CN 212231426U CN 202021735367 U CN202021735367 U CN 202021735367U CN 212231426 U CN212231426 U CN 212231426U
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Abstract
The utility model discloses a digit extraction wave filter and adc, digit extraction wave filter includes: a first integrator that integrates an input signal based on a first sampling clock signal to obtain a first signal; the second integrator is used for integrating the first signal based on the first sampling clock signal to obtain a second signal; the first temporary memory stores the first signal based on the second sampling clock signal to obtain a third signal; the second temporary memory stores the second signal based on the second sampling clock signal to obtain a fourth signal; and the arithmetic unit is used for calculating the second signal, the third signal and the fourth signal based on a second sampling clock signal to obtain a fifth signal which is used as the output of the digital decimation filter, wherein the period of the second sampling clock signal is 1/N of the period of the first sampling clock signal, and N is a positive integer. The digital decimation filter has fewer registers while achieving digital decimation filtering.
Description
Technical Field
The utility model relates to the field of electronic technology. And more particularly to a digital decimation filter and an analog-to-digital converter.
Background
A Sigma-Delta (Delta-Sigma) modulator and a digital decimation filter are key circuit modules for realizing a high-precision analog-to-digital converter (ADC) with more than 16 bits. The sigma-delta modulator shifts the quantization Noise in the baseband to the high band by means of Noise suppression (Noise Shaping) technique implemented by oversampling and closed-loop negative feedback control, while the digital decimation filter filters out the Noise in the out-of-band high band while reducing the output frequency bandwidth to the nyquist sampling frequency (2 f) of the input signalB) And finally, high-precision analog-to-digital conversion of the input signal is realized. With the increase of the oversampling multiple N, the components of the quantization noise spectrum and the signal spectrum which are overlapped are less and less, noise energy is moved to a high-frequency part by noise shaping, and quantization noise with | omega | greater than pi/N outside a frequency band is filtered by the digital decimation filter. The purpose of the digital decimation filter is to make the oversampling frequency fsIs restored to the Nyquist sampling frequency f by filtering and down-samplingN＝2fBAnd simultaneously only retaining useful signals within the range of | omega | ≦ pi/N as far as possible, and filtering noise outside a Nyquist frequency band.
In signal processing, a Sinc filter is an ideal low-pass filter, and in the field of digital communications, a digital decimation filter, a Cascaded Integrator-Comb (CIC) filter, which approximates the Sinc response is often used. The CIC digital decimation filter only utilizes an adder and a register (without a multiplier), occupies less resources and is simple and quick to implement. The sigma-delta modulator with more than one order and over-sampling multiple N has CIC digital decimation filter with order of L and transfer function of
Wherein the molecule (1-Z)-N)LIs an L-order comb filter, denominator (1-Z)-1)LIs an L-order integrator, the order L representing the number of cascaded filter stages.
A second order CIC digital decimation filter having a transfer function of
As shown in fig. 1, a conventional filter signal diagram implementation structure of a CIC digital decimation filter is formed by cascading two integrators and two comb filters.
However, the second-order CIC digital decimation filter of the conventional 1-bit sigma-delta modulator shown in fig. 1 requires at least 4 sets of registers and 4 sets of addition (subtraction) devices. And to achieve high snr and prevent accumulator overflow, it is necessary to ensure that the number of data bits is long enough. The number of bits of each group of registers is more than or equal to Llog2And N is an integer.
For example,
the order L is 2, and if the oversampling multiple N is 256, the register required by the first-stage integrator needs at least 8 bits; the registers required by the second-stage integrator need 16 bits at least; the register required by the first stage comb filter needs 16 bits at least; the registers needed by the second stage comb filter need 16 bits at least; a minimum of 8-bit adders is required; three minimum 16-bit adders;
the order L is 2, and if the oversampling multiple N is 32768, the register required by the first-stage integrator needs 15 bits at least; the registers required by the second-stage integrator need 30 bits at least; the registers required by the first stage comb filter need 30 bits at least; the registers required by the second stage comb filter need 30 bits at least; a minimum of 15 bits of adder is required; three minimum 30-bit adders;
each stage of register and adding (subtracting) device are both a small resource consumption, and the delay is relatively large.
SUMMERY OF THE UTILITY MODEL
In view of this, the present invention provides a digital decimation filter, including: a first integrator configured to integrate an input signal based on a first sampling clock signal to obtain a first signal; the second integrator is configured to integrate the first signal based on the first sampling clock signal to obtain a second signal; the first temporary storage is configured to store the first signal based on the second sampling clock signal to obtain a third signal; a second temporary memory configured to store the second signal based on the second sampling clock signal to obtain a fourth signal; and an arithmetic unit configured to calculate the second signal, the third signal and the fourth signal based on a second sampling clock signal to obtain a fifth signal as an output of the digital decimation filter, wherein a period of the second sampling clock signal is 1/N of a period of the first sampling clock signal, and N is a positive integer.
In some embodiments of the present application, the arithmetic unit includes a multiplier, an adder, and a subtractor, wherein the multiplier multiplies the third signal by N to obtain a sixth signal, the adder adds the sixth signal to the second signal based on the second sampling clock signal to obtain a seventh signal, and the subtractor subtracts the fourth signal from the seventh signal to obtain a fifth signal.
In some embodiments of the present application, the first temporary memory and the second temporary memory are latches.
In some embodiments of the present application, the digital decimation filter further comprises a frequency divider configured to divide the frequency of the first sampling clock signal to obtain the second sampling clock signal.
A second aspect of the present invention provides an analog-to-digital converter, including the sigma-delta modulator and the digital decimation filter of the first aspect, the sigma-delta modulator modulates the input analog signal into a digital signal having a sampling frequency higher than the nyquist frequency, and the digital decimation filter performs decimation filtering on the digital signal to reduce its sampling frequency to the nyquist sampling frequency.
The utility model has the advantages as follows:
the utility model discloses to current problem, provide a digit extraction wave filter and adc, through novel implementation structure or execution step, can utilize register still less when realizing digit extraction filtering, reduced resource consumption and time delay.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a simplified block diagram of a prior art second order CIC digital decimation filter.
Fig. 2 is a simplified block diagram of a digital decimation filter according to an embodiment of the present application.
Fig. 3 is a block diagram of an analog-to-digital converter according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions and advantages of the present invention clearer, the following will describe the embodiments of the present invention in further detail with reference to the accompanying drawings.
In the description of the present invention, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the art, the transfer function of a second-order CIC filter that implements digital decimation filtering is:
where N represents the oversampling factor. That is, the transfer function of expression (1) can achieve filtering of out-of-band high-band noise while reducing the output frequency bandwidth to the nyquist sampling frequency (2 f) of the input signalB) The function of (c).
In the present application, considering transforming this expression (1), one can obtain:
H(Z)＝(1+Z-1+Z-2+…+Z-N+1)2 (2)，
further mathematical transformation, one can get:
H(Z)＝1+2Z-1+3Z-2+…+NZ-N+1+(N-1)Z-N+(N-2)Z-N-1+… (3)，
+2Z-N-N+3+Z-N-N+2
further mathematical transformation, one can get:
H(Z)＝(1+2Z-1+3Z-2+…+NZ-N+1)
+N[Z-N+Z-(N+1)+…+Z-(N+N-3)+Z-(N+N-2)] (4)，
-[Z-N+2Z-(N+1)+…+(N-2)Z-(N+N-3)+(N-1)Z-(N+N-2)]
further mathematical transformation can also result in:
H(Z)＝(1+2Z-1+3Z-2+…+NZ-N+1)
+NZ-N[1+Z-1+…+Z-N+3+Z-N+2+Z-N+1] (5)，
-Z-N[1+2Z-1+…+(N-2)Z-N+3+(N-1)Z-N+2+NZ-N+1]
according to the embodiment of the present application, the expression (5) obtained by transformation may be decomposed into the following processes:
[1+Z-1+…+Z-N+3+Z-N+2+Z-N+1]can be expressed as: accumulating the current conversion input to the digital decimation filter and the previous N-1 continuously output conversion numbers;
(1+2Z-1+3Z-2+…+NZ-N+1) Can be expressed as: two-stage accumulation of the current conversion input to the digital decimation filter and the first N-1 continuously output conversion numbers;
NZ-N[1+Z-1+…+Z-N+3+Z-N+2+Z-N+1]can be expressed as: delaying N oversampling clock cycles after accumulating the current conversion input to the digital decimation filter and the first N-1 continuously output conversion numbers, and then expanding by N times;
Z-N[1+2Z-1+…+(N-2)Z-N+3+(N-1)Z-N+2+NZ-N+1]can be expressed as: the current conversion input to the digital decimation filter and the first N-1 consecutive output conversion numbers are delayed by N oversampling clock cycles after two-stage accumulation.
Based on the above transformation derivation, the present application considers the transfer function expressed by expression (1) that digitally decimates the analog-to-digital converted signal of the sigma-delta modulator to be finally expressed as: the two-stage accumulation result of the current conversion input into the digital decimation filter and the first N-1 conversion numbers which are continuously output is added with the result of delaying N oversampling clock periods and expanding N times after the current conversion input into the digital decimation filter and the first N-1 conversion numbers which are continuously output are accumulated, and then the subtraction is carried out with the result of delaying N oversampling clock periods after the two-stage accumulation of the current conversion input into the digital decimation filter and the first N-1 conversion numbers which are continuously output.
Specifically, as shown in fig. 2, the present application provides a digital decimation filter, which can implement the above-mentioned derivation process as a specific structure in the signal structure diagram shown in the figure.
According to an embodiment of the present application, the digital decimation filter may include: an integrator 1 (corresponding to a first integrator), an integrator 2 (corresponding to a second integrator), a register 1 (corresponding to a first register), a register 2 (corresponding to a second register), and an operator, wherein the integrator 1 is configured to integrate input data based on a first sampling clock signal to obtain a first integrated value; the integrator 2 is configured to integrate the first integration value based on the first sampling clock signal, resulting in a second integration value; the temporary storage 1 is configured to store the first integral value based on the second sampling clock signal, resulting in first stored data; the temporary storage 2 is configured to store a second integral value based on a second sampling clock signal, resulting in second stored data; the arithmetic unit is configured to calculate the first stored data, the second stored data and the second integral value based on the second sampling clock signal to obtain the output of the digital decimation filter; and the period of the second sampling clock signal is 1/N of the period of the first sampling clock signal, and N is a positive integer. That is, the integration of the integrator 1 and the integrator 2 is performed in synchronization with the first sampling clock signal, and the storage of the register 1 and the register 2 is performed in synchronization with the second sampling clock signal. Those skilled in the art will appreciate that the first sampling clock signal may be an oversampling clock signal and N may be an oversampling multiple. However, the present application is not intended to be limited thereto, and when the digital decimation filter is applied to other applications, the first sampling clock signal may be a clock representing other meanings as long as the relationship between the first sampling clock signal and the second sampling clock signal is satisfied.
Accordingly, a first input of the integrator 1 receives an input signal, i.e. a data input; a second input end of the integrator 1 is a clock signal end and receives a first sampling clock signal; the output of the integrator 1 is connected to the first input of the integrator 2 and to the first input of the register 1. The second input end of the temporary register 1 is a clock signal end and receives a second sampling clock signal; the output end of the temporary storage 1 is connected with the first input end of the arithmetic unit. A second input end of the integrator 2 is a clock signal end and receives a first sampling clock signal; a first output terminal of the integrator 2 may be connected to a second input terminal of the operator via a switch, wherein a control terminal of the switch receives the second sampling clock signal; the second output terminal of the integrator 2 is connected to the first input terminal of the register 2. The second input end of the temporary storage 2 is a clock signal end for receiving the second sampling clock signal, and the output end of the temporary storage 2 is connected with the third input end of the arithmetic unit.
As shown in fig. 2, according to the embodiment of the present application, if the frequency of the first sampling clock signal is fs, the first integrated value S is generated as an integrated output after being accumulated by the integrator 1 of the first stage in synchronization with the first sampling clock signal1First integral value S1The down-sampled second sampling clock signal having a frequency fs/N is stored in the register 1 to store an accumulated number of N first sampling clock signals, i.e., a first integrated value of N first sampling clock signals. It will be understood by those skilled in the art that the register 1 may be various latches, such as a D latch, a JK latch, etc., which can be used to implement the above data buffering method. Meanwhile, the first integrated value S is synchronized with the first sampling clock signal1The integrator 2 input to the second stage accumulates to generate a second integration value S as an integration output2Second integral value S2The down-sampled second sampling clock signal is latched into the register 2 to hold the accumulated number N times before the first sampling clock, i.e., to hold the second integrated value N times before the first sampling clock signal. Similarly, the register 2 may be various latches, such as a D latch, a JK latch, etc., which can be used to implement the data buffering method. At the same time, the second integral value S2Outputting S in synchronization with the down-sampled second sampling clock signal2NInto an arithmetic unit. As can be seen, S is output in synchronization with the down-sampled second sampling clock signal2NThe process into the operator may be implemented as controlling the gating switch on and off with the down-sampled second sampling clock signal, i.e. S2NA second integration value of the integrator 2 at the moment when the gating switch is controlled to be turned on for the second sampling clock signal. Thus, the operator will S2NPlus N times D1 minus D2And generating a second-order digital decimation filter output result.
The first integral value S of the temporary storage 1 to the integrator 1 based on the second sampling clock signal1The storing is performed such that the accumulated number of the integrator 1 before the N first sampling clocks is saved, that is, the integrated value before the N first sampling clock signals is delayed by N sampling clocks, that is: z-N[1+Z-1+…+Z-N+3+Z-N+2+Z-N+1]The maximum accumulated value of the process is N, the number of bits required by the register is at most log2N；
The first integral value S of the temporary storage 2 to the integrator 2 based on the second sampling clock signal2The storage is performed such that the accumulated number of N first sampling clocks of the integrator 2 is held, that is, the integrated value before the N first sampling clock signals is delayed by N sampling clocks, that is, Z-N[1+2Z-1+…+(N-2)Z-N+3+(N-1)Z-N+2+NZ-N+1Z-N+1Z-N+1]The maximum accumulated value of the process is N (N +1)/2, and the number of bits required for the register is at most 2log2N；
Meanwhile, the switch connected between the integrator 2 and the operator is controlled based on the second sampling clock signal so that the integrated value of the integrator 2, that is, the integrated value at the time when the switch is turned on, i.e., (1+ 2Z), is read once every N first sampling clock cycles-1+3Z-2+…+NZ-N+1) The maximum accumulated value of the process is N (N +1)/2, and the number of bits required for the register is at most 2log2N。
In an alternative embodiment, the operator may include a multiplier, an adder, and a subtractor. As shown in fig. 2, the multiplier is an N-fold multiplier. Input of multiplier and temporary storage 1The output end is connected, and at the moment, the input end of the multiplier can be used as the first input end of the arithmetic unit; the first input end of the adder is connected with the output end of the multiplier, the second input end of the adder is connected with the output end of the integrator 2 through a switch, at the moment, the second input end of the adder can be used as the second input end of the arithmetic unit, the output end of the adder is connected with the first input end of the subtracter, the second input end of the subtracter is connected with the output end of the temporary storage 2, at the moment, the second input end of the subtracter can be used as the third input end of the arithmetic unit, and the output end of the subtracter is used as the output end of the digital. Accordingly, since the storage of the temporary memory 1 and the temporary memory 2 and the on/off of the switch are realized based on the second sampling clock signal, the output of the operation according to the embodiment is S2N+ND1-D2And S is2NThe data access is only available at the moment when the switch controlled by the second sampling clock signal is turned on, so that the arithmetic unit is only available at S2NThe time when there is data has an output, that is, the arithmetic operation of the arithmetic unit is performed based on the second sampling clock signal.
In an alternative embodiment, the data decimation filter according to embodiments of the present application may further include an N-divider that may divide the first sampling clock signal into the second sampling clock signal. And when the first sampling clock signal is the oversampling clock signal, the second sampling clock signal after the frequency division of the N frequency divider is the degraded sampling clock signal. It will be appreciated by those skilled in the art that the present application is not so limited and the divided clock to the first sampling clock signal, i.e., the second sampling clock signal, may also be provided by a component part other than the data decimation filter.
According to the embodiment of the present application, if the oversampling multiple N is assumed to be 256, the integrator 1 requires a minimum of 8 bits for the register; the register needed by the integrator 2 needs 16 bits at least, the register needed by the register 1 needs 8 bits at least, and the register needed by the register 2 needs 16 bits at least; the whole second-order digital decimation filter needs a minimum of 48 registers in total; the N-fold operator only needs to perform two's complement extension log on the register 1 output D12N bits without additional multiplier and registerA machine; the adder required in the integrator 1 is 8 bits, the adder required in the integrator 2 is 16 bits, and both the adders in the arithmetic unit are 16 bits, which reduces 8-bit registers compared with the traditional second-order digital decimation filter shown in fig. 1, wherein the traditional second-order digital decimation filter shown in fig. 1 needs 8 bits of registers required by the first-stage integrator at least; the registers required by the second-stage integrator need 16 bits at least; the register required by the first stage comb filter needs 16 bits at least; the registers needed by the second stage comb filter need 16 bits at least; a minimum of 8-bit adders is required; three minimum 16-bit adders;
if the oversampling multiple N is 32768, the required register of the integrator 1 needs 15 bits at least; the register needed by the integrator 2 needs 30 bits at least, the register needed by the register 1 needs 15 bits at least, and the register needed by the register 2 needs 30 bits at least; the whole second-order digital decimation filter needs at least 90 registers in total; the N-fold operator only needs to perform two's complement extension log on the register 1 output D12N bits, no extra multiplier and register are needed; the adder required in the integrator 1 is 15 bits, the adder required in the integrator 2 is 30 bits, and both the adders in the arithmetic unit are 30 bits, so that the two-bit digital decimation filter reduces 15-bit registers compared with a second-order digital decimation filter in the prior art.
It will be appreciated by those skilled in the art that the above comparisons are exemplary and intended to illustrate the benefits of the digital decimation filter of the embodiments of the present application, and that similarly when the oversampling multiple is other values, the digital decimation filter of the embodiments of the present application may also require fewer registers than the prior art.
Therefore, the digital decimation filter according to the embodiment of the application can realize digital decimation filtering and simultaneously has fewer registers through a novel structure, and resource consumption and delay are reduced.
As shown in fig. 3, there is also provided an analog-to-digital converter according to an embodiment of the present application, including: a sigma-delta modulator that modulates an input analog signal into a digital signal having a frequency higher than nyquist, the sampling frequency of the digital signal being an oversampling frequency, the oversampling multiple being N, and a digital decimation filter. The digital decimation filter decimates and filters the digital signal output by the sigma-delta modulator to reduce the sampling frequency to the Nyquist sampling frequency. The digital decimation filter may implement the digital decimation filter according to the embodiments of the present application as described above, and will not be described in detail in the present embodiment.
According to the digital decimation filter, the novel structure is adopted, the digital decimation filter is realized, meanwhile, fewer registers are arranged, and the resource consumption and the time delay are reduced.
Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it is obvious for those skilled in the art to make other variations or changes based on the above descriptions, and all the embodiments cannot be exhausted here, and all the obvious variations or changes that belong to the technical solutions of the present invention are still in the protection scope of the present invention.
Claims (5)
1. A digital decimation filter, comprising:
a first integrator configured to integrate an input signal based on a first sampling clock signal to obtain a first signal;
a second integrator configured to integrate the first signal based on the first sampling clock signal to obtain a second signal;
a first temporary memory configured to store the first signal based on a second sampling clock signal to obtain a third signal;
a second temporary memory configured to store the second signal based on the second sampling clock signal to obtain a fourth signal; and
an operator configured to operate on the second signal, the third signal, and the fourth signal based on the second sampling clock signal to obtain a fifth signal as an output of the digital decimation filter,
and the period of the second sampling clock signal is 1/N of the period of the first sampling clock signal, and N is a positive integer.
2. The digital decimation filter according to claim 1, wherein said operator comprises a multiplier, an adder and a subtractor, wherein,
the multiplier multiplies the third signal by N times to obtain a sixth signal,
the adder adding the sixth signal to the second signal based on the second sampling clock signal to obtain a seventh signal,
the subtractor subtracts the fourth signal from the seventh signal to obtain the fifth signal.
3. The digital decimation filter according to claim 1, wherein said first temporary storage and said second temporary storage are latches.
4. The digital decimation filter according to claim 1, further comprising a frequency divider configured to divide the frequency of said first sampling clock signal to obtain said second sampling clock signal.
5. An analog-to-digital converter comprising a sigma-delta modulator that modulates an input analog signal into a digital signal having a sampling frequency higher than the nyquist frequency and a digital decimation filter that decimates the digital signal down to the nyquist sampling frequency according to any one of claims 1 to 4.
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