CN113098472B - Sampling circuit and method - Google Patents
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- CN113098472B CN113098472B CN201911336321.8A CN201911336321A CN113098472B CN 113098472 B CN113098472 B CN 113098472B CN 201911336321 A CN201911336321 A CN 201911336321A CN 113098472 B CN113098472 B CN 113098472B
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- 238000005070 sampling Methods 0.000 title claims abstract description 123
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000006243 chemical reaction Methods 0.000 claims abstract description 24
- 238000009825 accumulation Methods 0.000 claims abstract description 17
- 230000010354 integration Effects 0.000 claims description 9
- 230000004069 differentiation Effects 0.000 claims description 6
- 238000000605 extraction Methods 0.000 abstract description 2
- 238000001228 spectrum Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 12
- 238000001914 filtration Methods 0.000 description 6
- 238000012952 Resampling Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
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- 230000002441 reversible effect Effects 0.000 description 1
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- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
- H03K17/785—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling field-effect transistor switches
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Abstract
A sampling circuit and a sampling method are provided. The sampling circuit comprises a differentiating circuit and a signal converting circuit. The differentiating circuit is used for differentiating the first digital signal into the second digital signal. The first digital signal has an input frequency. The signal conversion circuit is used for converting the second digital signal into a digital output signal. The digital output signal has a sampling frequency, and the input frequency is different from the sampling frequency. The signal conversion circuit comprises an accumulation circuit and an addition circuit. The accumulation circuit is used for accumulating the second digital signal into a third digital signal in a time interval. The adding circuit is used for generating a digital output signal according to the third digital signal, the input frequency and the sampling frequency. The sampling circuit and the sampling method can perform sampling frequency conversion with low operand and high signal to noise ratio on the original digital signal with frequency offset, achieve the purpose of obtaining the digital signal without frequency offset or with low frequency offset, and can also avoid the problem that the operation load of the sampling circuit is greatly improved when the signal sampling frequency is converted by using an interpolation/extraction method.
Description
Technical Field
The present disclosure relates to sampling circuits, and more particularly to sampling circuits using differential circuits.
Background
With the increasing growth of signal transmission technology, the speed of signals is also increasing, and when the circuit is sampling the received signals, the clock frequency offset in the signals transmitted at high speed is more and more obvious, so that the function of sampling in the circuit is more and more critical to avoid the frequency offset.
Disclosure of Invention
An embodiment of the present disclosure relates to a sampling circuit, which includes a differentiating circuit and a signal converting circuit. The differentiating circuit is used for differentiating the first digital signal into the second digital signal. The first digital signal has an input frequency. The signal conversion circuit is used for converting the second digital signal into a digital output signal. The digital output signal has a sampling frequency, and the input frequency is different from the sampling frequency. The signal conversion circuit includes an accumulation circuit and an addition circuit. The accumulation circuit is used for accumulating the second digital signal into a third digital signal in a time interval. The adding circuit is used for generating a digital output signal according to the third digital signal, the input frequency and the sampling frequency.
An embodiment of the present disclosure relates to a sampling method, which includes the following operations. Performing an X-order differentiation on the first digital signal by a differentiating circuit to generate a second digital signal; and performing, by the signal processing circuit, Y-order integration on the second digital signal to produce a digital output signal. X and Y are positive integers, and X plus 1 is greater than or equal to Y. The first digital signal has an input frequency, the digital output signal has a sampling frequency, and the input frequency is different from the sampling frequency. Performing Y-order integration on the second digital signal includes the following operations: accumulating the second digital signal into a plurality of accumulated signals according to the input frequency and the sampling frequency in a time interval; and summing the accumulated signals to digital output signals according to the input frequency and the sampling frequency.
In summary, the sampling circuit and the method according to some embodiments of the present disclosure can perform signal resampling with low operation amount and high signal-to-noise ratio under the condition that the original digital signal has frequency offset, so as to achieve the purpose of obtaining the digital signal without frequency offset or with reduced frequency offset. The method can also avoid the problem that the operation load of the sampling circuit for converting the sampling frequency by interpolation/extraction is greatly improved.
Drawings
The present disclosure will be more fully understood from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a sampling circuit according to some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of the spectrum of the differentiating circuit shown in FIG. 1 according to some embodiments of the present disclosure;
FIG. 3 is a schematic diagram of the frequency spectrum of the signal conversion circuit of FIG. 1 according to some embodiments of the present disclosure;
FIG. 4 is a schematic diagram of the frequency spectrum of the sampling circuit of FIG. 1 according to some embodiments of the present disclosure;
FIG. 5 is a schematic diagram of a sampling circuit shown according to some embodiments of the present disclosure;
FIG. 6 is a schematic diagram of a sampling circuit shown according to some other embodiments of the present disclosure; and
fig. 7 is a flow chart of a sampling method shown in accordance with some embodiments of the present disclosure.
Symbol description
100. Sampling circuit
110. Analog-to-digital converter
120. Differential circuit
121. Differentiator
130. Signal conversion circuit
131. Accumulation circuit
131a accumulator
132. Digital-to-analog converter
133. Addition circuit
133a adder
134. Integrating circuit
136. Analog-to-digital converter
140. Filtering circuit
x (t) analog signal
xi (t) input signal
x (n) digital signal
x1 (n) digital signal
xp (t) analog signal
xac1 accumulated signal
xac2 accumulated signal
xac3 accumulated signal
xac4 accumulated signal
z1 integral signal
z2 integral signal
z3 integral signal
z4 integral signal
z (n) digital signal
D delay device
S integrator
d coefficient
800. Method of
S810 operation
S820 operation
S830 operation
S840 operation
Detailed Description
The following detailed description of the embodiments is provided in conjunction with the accompanying drawings, but the specific embodiments described are merely illustrative of the embodiments of the disclosure and are not intended to limit the disclosure, and the description of the structure operation is not intended to limit the order in which the operations may be performed, any arrangement of elements that may be rearranged to produce a result with equivalent technical results is within the scope of the disclosure of the embodiments of the disclosure.
As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also mean that two or more elements are in operation or action with each other.
Reference is made to fig. 1. Fig. 1 is a schematic diagram of a sampling circuit 100 according to some embodiments of the present disclosure. The sampling circuit 100 is used for sampling the analog signal x (t) to output as the output signal z (n). The output signal z (n) is a digital signal having a sampling frequency Fs.
As shown in fig. 1, the sampling circuit 100 includes an analog-to-digital converter 110, a differentiating circuit 120, and a signal converting circuit 130. The analog-to-digital converter 110 is coupled to the differentiating circuit 120, and the differentiating circuit 120 is coupled to the signal converting circuit 130.
In some embodiments, the analog-to-digital converter 110 receives an analog signal x (t) and converts the analog signal x (t) to a digital signal x (n). The digital signal x (n) has an input frequency, which is different from the sampling frequency Fs.
In some embodiments, the differentiating circuit 120 receives the digital signal x (n) and is configured to differentiate the digital signal x (n) into the digital signal x1 (n). The differentiating circuit 120 includes an X-order differentiator 121 for performing an X-order differentiation on the digital signal X (n). As shown in fig. 1, the differentiating circuit 120 is a 4-order differentiating circuit, which includes 4 differentiators 121 connected in series. The differentiating circuit 120 receives the digital signal x (n), the first differentiator 121 differentiates the digital signal x (n) into a first digital differentiated signal, the second differentiator 121 differentiates the first digital differentiated signal into a second digital differentiated signal, the third differentiator 121 differentiates the second digital differentiated signal into a third digital differentiated signal, and the fourth differentiator 121 differentiates the third digital differentiated signal into a digital signal x1 (n).
As shown in fig. 1, the differentiator 121 includes a delay D for subtracting the next received signal from the previous received signal. Taking the first differentiator 121 as an example, the differentiator 121 receives the digital signal x (n), and the delay D delays the digital signal x (n) by a unit period, and the differentiator 121 receives the digital signal x (n+1). The differentiator 121 subtracts the digital signal x (n+1) from the digital signal x (n) at a node, and outputs the digital signal x (n) as a first digital differentiated signal to the second differentiator 121. The other differentiators 121 have similar functions and are not described here.
In some embodiments, the signal conversion circuit 130 is configured to convert the digital signal x1 (n) into the output signal z (n). The signal conversion circuit 130 includes a digital-to-analog converter 132, an integrating circuit 134, and an analog-to-digital converter 136. In some embodiments, the digital-to-analog converter 132 is configured to convert the digital signal x1 (n) into an analog signal xp (t), the integrating circuit 134 is configured to integrate the analog signal xp (t) into an analog signal z (t), and the analog-to-digital converter 136 is configured to convert the analog signal z (t) into an output signal z (n) with a new sampling frequency.
In some embodiments, the integrating circuit 134 includes a Y-stage integrator S to perform Y-stage integration on the analog signal xp (t). As shown in fig. 1, the integrating circuit 134 is a 4-order integrating circuit, the first integrator S integrates the analog signal xp (t) into a first integrated signal z1, the second integrator S integrates the first integrated signal z1 into a second integrated signal z2, the third integrator S integrates the second integrated signal z2 into a third integrated signal z3, and the fourth integrator S integrates the third integrated signal z3 into a fourth integrated signal z4.
In some embodiments, the order X of the differentiating circuit 120 has a relationship of X+1+_Y with the order Y of the integrating circuit 130 for the stabilization of the sampling circuit. The order of the differentiating circuit 120 and the integrating circuit 130 is merely exemplary, and various orders X, Y are within the scope and contemplation of the present disclosure. For example, X and Y are 7 th order.
In some embodiments, the sampling circuit 100 includes a delta-sigma (ΔΣ: delta-sigma) circuit implemented with at least a differentiating circuit 120, an analog-to-digital converter 132, and an integrating circuit 134.
Reference is made to fig. 2. Fig. 2 is a schematic diagram of the spectrum of the differentiating circuit 120 shown in fig. 1 according to some embodiments of the present disclosure. In some embodiments, the differentiating circuit 120 has a spectrum as shown in fig. 2, which may be a filter of the digital signal x (n) into the digital signal x1 (n) according to the spectrum. As shown in fig. 2, the differentiating circuit 120 attenuates the sampling frequency Fs of 0 times, the sampling frequency Fs of 1 times, and the sampling frequency Fs of 2 times (i.e., the sampling frequency Fs of an integer multiple).
Reference is made to fig. 3. Fig. 3 is a schematic diagram of the frequency spectrum of the signal conversion circuit 130 of fig. 1 according to some embodiments of the present disclosure. In some embodiments, the signal conversion circuit 130 has a spectrum as shown in fig. 3, which may be a filter of the digital signal x1 (n) into the analog signal z (t) according to the spectrum. As shown in FIG. 3, the spectra of FIG. 3 and FIG. 2 have approximately reversible relationships over the [ -Fs/2, fs/2] interval. The signal conversion circuit 130 amplifies a low-frequency (around 0 times the sampling frequency Fs) signal, and further attenuates a high-frequency signal (around 1 times the sampling frequency Fs, around 2 times the sampling frequency Fs, etc.), the attenuation of the signal increases exponentially with the distance of the sampling frequency Fs.
Refer to fig. 4. Fig. 4 is a schematic diagram of a frequency spectrum of the sampling circuit 100 of fig. 1 according to some embodiments of the present disclosure. In some embodiments, the spectrum of the sampling circuit 100 is a superposition of the spectrum of the differentiating circuit 120 shown in fig. 2 and the spectrum of the signal converting circuit 130 shown in fig. 3. As shown in fig. 4, the spectrum has a flat characteristic in the range of ±fs/2. That is, the sampling circuit 100 is a low-pass filter, and the digital signal can be effectively recovered into the analog signal z (t) by using the low-pass filter, and then resampling can be performed to obtain the output z (n) with the new sampling frequency.
Referring back to fig. 1. The process by which the signal conversion circuit 130 converts the digital signal x1 (n) into the output signal z (n) may be represented by a mathematical equation that may be used to derive the particular circuit implementation of fig. 5. When the digital signal x1 (n) is converted to the analog signal xp (t) by the digital-to-analog converter 132, it can be represented by equation eq 1.
Where T is the period of the digital signal x1 (n), i.e. the inverse of the input frequency of the digital signal x1 (n). Next, the integrating circuit 134 integrates the analog signal xp (t), and outputs a fourth integrated signal z4=z (t). The fourth integrated signal z4 is a 4-order integration of the analog signal xp (t), wherein the first integrated signal z1, the second integrated signal z2, the third integrated signal z3 and the fourth integrated signal z4 can be represented by a state transition equation eq 2.
Wherein z1 '(t) to z4' (t) are the differentiation of z1 (t) to z4 (t), and equation eq2 for calculating the state transition is expressed as equation eq3 for convenience.
Z′(t)＝A·Z(t)+B·xp(t) eq3
Then, equation eq3 is transformed by Laplace transform (Laplace transform) to obtain equation eq4.
Z(S)＝(sI-A) -1 ·Z(0)+(sI-A) -1 ·B·X(S) eq4
Then, laplace inverse transformation is performed on equation eq4, and xp (t) is expanded by equation eq1 to obtain equation eq5.
Wherein H (t) and xp (t) can be represented by the following formula.
Whereas H (t) has the property of a matrix exponential function: h (t1+t2) =h (t 1) ×h (t 2). By taking advantage of this property, the relationship between z (t) at two points t1 and t2 can be represented by equation eq 6.
Wherein the second term of equation eq6 is the sum of the digital signals x1 (n) between the time intervals of time t1 and t2, and H (: 1) is the first row of the H matrix. Sampling z (T) with an output frequency of 1/T' (i.e., sampling frequency Fs) results in two adjacent sampling points: t1=k×t ', t2= (k+1) T'. Substituting t1=k×t ', and t2= (k+1) T', into equation eq6 yields equation eq7.
Wherein dn= [ (k+1) T' -nT ], then normalize the period T of the digital signal x1 (n) in equation eq7, equation eq8 can be obtained.
Where d=t '/T, so the relationship of dn to T'/T is expressed by equation eq 9.
It follows that z (k+1) is only related to the last states z (k) and T'/T, and that z (k) is related to the digital signal x1 (n) occurring in the time interval of z (k+1).
As can be seen from the above equations eq1 to eq9, the signal conversion circuit 130 can perform signal conversion according to the result of the equation eq8. The signal conversion circuit 130 resets the accumulation operation after the accumulation is finished according to the input frequency (1/T) of the digital signal x1 (n) and the digital signal x1 (n) between the sampling frequency Fs (1/T') and the accumulated z (k) and z (k+1), so that the workload of the circuit is reduced, and a large amount of integrated data is not required to be processed.
Reference is made to fig. 5. Fig. 5 is a schematic diagram of a sampling circuit 100 according to further embodiments of the present disclosure. In some embodiments, the signal conversion circuit 130 in the sampling circuit 100 is set according to the result of the above equation eq8.
As shown in fig. 5, the sampling circuit 100 includes a differentiating circuit 120 and a signal converting circuit 130. The differentiating circuit 120 is the same as the differentiating circuit 120 in fig. 1, and will not be described again. The signal conversion circuit 130 in fig. 5 includes an accumulation circuit 131 and an addition circuit 133. The accumulating circuit 131 is configured to accumulate the digital signal x1 (n) in a time interval, and transmit the accumulated digital signal x1 (n) to the adding circuit 133. The adder 133 generates an output signal z (n) according to the accumulated digital signal x1 (n), the frequency (1/T) of the digital signal x (n) and the sampling frequency Fs (1/T').
In some embodiments, the accumulation circuit 131 includes a plurality of accumulators 131a, each accumulator 131a including a delay D. As shown in fig. 5, the accumulating circuit 131 includes four accumulators 131a, corresponding to equation eq8, each accumulator 131a is responsible for accumulating the digital signal x1 (nT) multiplied by four coefficients (1, d n 、d n 2 /2、d n 3 And/6) to generate the summation signals xac 1-xac 4. For example, the accumulator 131a corresponding to the coefficient 1 is the lowermost accumulator 131a in fig. 5, which is used to accumulate (kT 'in the time interval)'<nT++1T') to generate the accumulated signal xac1. Another example corresponds to the coefficient d n 3 The accumulator 131a of/6 is the uppermost accumulator 131a in fig. 5, which is used to accumulate (kT 'over the time interval'<Digital signal x1 (nT) having nT + (k+1) T') is multiplied by coefficient d n 3 /6 to generate an accumulated signal xac, wherein the coefficient d n 3 The input frequency (1/T) of/6 and x1 (n) is related to the sampling frequency Fs (1/T').
In some embodiments, the adder 133 includes a plurality of adders 133a, each adder 133a including a delay D. As shown in fig. 5, the adder circuit 133 includes four adders 133a, corresponding to the equation eq8, each adder 133a is configured to generate a first integrated signal z1, a second integrated signal z2, a third integrated signal z3 and a fourth integrated signal z4, respectively. For example, the leftmost adder 133a in FIG. 5 is used to sum the first column in equation eq8, i.e., sum z1 (k) and the bottommost Fang Leijia generated by the adder 133aThe accumulated signal xca is z1 (k+1). As another example, the rightmost adder 133a in FIG. 5 is used to sum the fourth row of equation eq8, i.e., sum z1 (k), z2 (k), z3 (k), and z4 (k) multiplied by the corresponding coefficients (d 3 /6、d 2 The sum xac of/2, d, 1) and the uppermost Fang Leijia unit 133a is z4 (k+1). The adding circuit 133 is configured to output z4 as an output signal z (n).
In some embodiments, the adder 133 is configured to reset the adder 131 after the time interval is ended, so that the adder 131 recalculates the accumulated signals xac-xac 4.
In some embodiments, the first integrated signal z1, the second integrated signal z2, the third integrated signal z3, and the fourth integrated signal z4 are also referred to as addition signals.
Compared to fig. 1, the first integrated signal z1, the second integrated signal z2, the third integrated signal z3 and the fourth integrated signal z4 in fig. 1 are analog signals, and the first integrated signal z1, the second integrated signal z2, the third integrated signal z3 and the fourth integrated signal z4 in fig. 5 are digital signals. The signal conversion circuit 130 in fig. 5 directly processes the digital signal x1 (n) and outputs as an output signal z (n), in which the operation does not convert the signal into an analog signal.
In some embodiments, the sampling circuit may achieve a better signal-to-noise ratio when the input digital signal x (n) is an over-sampled signal. Oversampling rate OSR (oversampling ratio) = sampling frequency/(highest frequency of analog signal x 2). The multi-tone power ratio (MTPR) of the signal may also be increased in a multi-carrier system when the over-sampling rate OSR is relatively high.
Refer to fig. 6. Fig. 6 is a schematic diagram of a sampling circuit 100 shown in accordance with some other embodiments of the present disclosure. The sampling circuit 100 in fig. 6 further includes a filtering circuit 140 as compared to the sampling circuit 100 in fig. 5, wherein the filtering circuit 140 can use interpolation filtering to increase the oversampling ratio OSR of the input signal x (n). The filter circuit 140 is coupled to the differentiating circuit 120.
In some embodiments, the filtering circuit 140 is configured to receive the input signal xi (n) and interpolate the input signal xi (n) to generate the digital signal x (n) such that the input frequency of the digital signal x (n) is greater than the frequency of the input signal xi (n) to increase the oversampling rate OSR of the input signal of the sampling circuit.
Compared to the sampling circuit 100 of fig. 5, the sampling circuit 100 of fig. 6 interpolates the signal into a signal with a higher frequency in advance, and then performs the operations of the subsequent differentiating circuit 120 and the signal processing circuit 130. Therefore, the OSR of the sampling circuit 100 in fig. 6 is higher than the OSR of the sampling circuit 100 in fig. 5 because of the filter circuit 140, which helps to increase the MTPR of the sampling circuit 100.
Refer to fig. 7. Fig. 7 is a flow chart of a sampling method 700 shown according to some embodiments of the present disclosure. In some embodiments, the sampling method 700 is used to sample the input signal xi (n) and output the output signal z (n), wherein the sampling frequency Fs of the output signal z (n) is different from the frequency of the input signal xi (n), so as to achieve the purposes of converting the sampling frequency, eliminating or reducing the frequency offset. In some embodiments, the sampling method 700 is implemented by at least a portion of the sampling circuit 100 of fig. 1, 5, 6. As shown in FIG. 7, the sampling method 700 includes operations S710, S720, S730, and S740.
In operation S710, the input signal xi (n) is interpolated by the filtering circuit 140 to generate a digital signal x (n) such that the digital signal x (n) has a higher frequency than the input signal xi (n). In other words, in operation S710, the frequency of the input signal xi (n) is increased by the filter circuit 140 to be output as the digital signal x (n).
In operation S720, X-order differentiation is performed on the digital signal X (n) by the differentiating circuit 120 to generate a digital signal X1 (n). X is a positive integer.
In operation S730, the accumulating circuit 131 accumulates the digital signal x1 (n) according to the input frequency of the digital signal x1 (n) and the sampling frequency Fs to obtain accumulated signals xac-xac, wherein the time interval is the inverse of the sampling frequency Fs, i.e. the period of the output signal z (n).
In operation S740, the adding circuit 133 adds the accumulated signals xac 1-xac and the integrated signals z 1-z 4 to the output signal z (n) according to the input frequency and the sampling frequency Fs of the digital signal x1 (n).
In some embodiments, operations S730 and S740 are performed by the signal processing circuit 130, which is equivalent to performing a Y-order integration on the digital signal x1 (n) to generate the output signal z (n). Y is a positive integer. In some embodiments, x+1 is greater than or equal to Y.
The figures described above contain exemplary operations, but the operations are not limited to the order shown. Operations may be added, substituted, sequenced, and/or omitted as appropriate in accordance with embodiments of the present disclosure.
The figures described above contain exemplary operations, but the operations are not limited to the order shown. Operations may be added, substituted, sequenced, and/or omitted as appropriate in accordance with embodiments of the present disclosure.
In some embodiments, a sampling circuit includes a differentiating circuit and a signal converting circuit. The differentiating circuit is used for differentiating the first digital signal into the second digital signal. The first digital signal has an input frequency. The signal conversion circuit is used for converting the second digital signal into an output signal. The output signal has a sampling frequency. The signal conversion circuit includes an accumulation circuit and an addition circuit. The accumulation circuit is used for accumulating the second digital signal in the time interval into a plurality of accumulation signals. The adding circuit is used for generating an output signal according to the accumulated signal, the input frequency and the sampling frequency.
In various embodiments, the sampling circuit includes a first differentiator and at least a second differentiator. The first differentiator is used for differentiating the first digital signal. The at least one second differentiator is used for differentiating the first digital signal differentiated by the first differentiator to generate a second digital signal.
In various embodiments, the sampling circuit includes a first accumulator and at least a second accumulator. The first accumulator is used for accumulating the second digital signal in the time interval as a first accumulated signal in the accumulated signals. The at least one second accumulator is used for accumulating the second digital signal in the time interval according to the input frequency and the sampling frequency to be a second accumulated signal in the accumulated signal.
In various embodiments, the sampling circuit includes a first adder and at least one second adder. The first adder is used for generating a first addition signal according to the first accumulation signal. The at least one second adder is used for generating an output signal according to the input frequency, the sampling frequency, the first adding signal and the second adding signal.
In various embodiments, in the sampling circuit, the adding circuit is further configured to reset the accumulating circuit after the accumulating circuit has accumulated the second digital signal within the time interval.
In various embodiments, the sampling circuit further includes a filter circuit. The filter circuit is used for interpolating an input signal to generate a first digital signal. The input frequency of the first digital signal is greater than the frequency of the input signal.
In various embodiments, the differential circuit is an X-order differential circuit and the signal conversion circuit is a Y-order integrated circuit. X plus 1 is equal to or greater than Y, and X and Y are positive integers.
In some embodiments, a sampling method includes the operations of: performing an X-order differentiation on the first digital signal by a differentiating circuit to generate a second digital signal; and performing, by the signal processing circuit, Y-order integration on the second digital signal to produce an output signal. X and Y are positive integers, and X plus 1 is greater than or equal to Y. The first digital signal has an input frequency, the output signal has a sampling frequency, and the input frequency is different from the sampling frequency. Performing Y-order integration on the second digital signal includes the following operations: accumulating the second digital signal into a plurality of accumulated signals according to the input frequency and the sampling frequency in a time interval; and summing the accumulated signals to output signals according to the input frequency and the sampling frequency.
In various embodiments, the sampling method further includes interpolating the input signal to increase the frequency of the input signal, and outputting the interpolated input signal as the first digital signal.
In various embodiments, in the sampling method, the time interval is a period of the output signal.
Although the embodiments of the present disclosure have been disclosed above, it should be understood that the present disclosure is not limited thereto, and that various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the present disclosure, and therefore, the scope of the embodiments of the present disclosure is defined by the appended claims.
Claims (10)
1. A sampling circuit, comprising:
a differentiating circuit for differentiating a first digital signal into a second digital signal, wherein the first digital signal has an input frequency; and
a signal conversion circuit for converting the second digital signal into an output signal, wherein the output signal has a sampling frequency, the input frequency is different from the sampling frequency, the signal conversion circuit comprising:
an accumulation circuit for accumulating the second digital signal into a plurality of accumulation signals in a time interval; and
an adder circuit for generating the output signal according to the accumulated signal, the input frequency and the sampling frequency.
2. The sampling circuit of claim 1, wherein the differentiating circuit comprises:
a first differentiator for differentiating the first digital signal; and
at least one second differentiator for differentiating the first digital signal differentiated by the first differentiator to generate the second digital signal.
3. The sampling circuit of claim 1, wherein the accumulation circuit comprises:
a first accumulator for accumulating the second digital signal in the time interval as a first accumulated signal in the accumulated signals; and
and at least one second accumulator for accumulating the second digital signal in the time interval into a second accumulated signal in the accumulated signals according to the input frequency and the sampling frequency.
4. The sampling circuit of claim 3, wherein the summing circuit comprises:
a first adder for generating a first addition signal according to the first accumulation signal; and
at least one second adder for generating the output signal according to the input frequency, the sampling frequency, the first adding signal and the second adding signal.
5. The sampling circuit of claim 1, wherein the adding circuit is further configured to reset the accumulating circuit after the accumulating circuit has accumulated the second digital signal during the time interval.
6. The sampling circuit of claim 1, further comprising:
the filter circuit is used for interpolating an input signal to generate the first digital signal, wherein the input frequency of the first digital signal is larger than a frequency of the input signal.
7. The sampling circuit of claim 1, wherein the differentiating circuit is an X-order differentiating circuit, and the signal converting circuit is a Y-order integrating circuit, wherein X plus 1 is greater than or equal to Y, and X and Y are positive integers.
8. A sampling method, comprising:
performing X-order differentiation on a first digital signal by a differentiating circuit to generate a second digital signal; and
performing Y-stage integration on the second digital signal by a signal processing circuit to generate an output signal,
wherein X and Y are positive integers, and X plus 1 is greater than or equal to Y,
the first digital signal has an input frequency, the output signal has a sampling frequency, the input frequency is different from the sampling frequency, and
performing Y-order integration on the second digital signal comprises:
accumulating the second digital signal into a plurality of accumulated signals according to the input frequency and the sampling frequency in a time interval; and
and summing the accumulated signals into the output signal according to the input frequency and the sampling frequency.
9. The sampling method of claim 8, further comprising:
an input signal is interpolated to increase a frequency of the input signal and the input signal with the inner difference is output as the first digital signal.
10. The sampling method according to claim 8, wherein the time interval is a period of the output signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911336321.8A CN113098472B (en) | 2019-12-23 | 2019-12-23 | Sampling circuit and method |
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| CN201911336321.8A CN113098472B (en) | 2019-12-23 | 2019-12-23 | Sampling circuit and method |
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| JP2008199220A (en) * | 2007-02-09 | 2008-08-28 | Toshiba Corp | Ad conversion processing circuit and demodulation device |
| CN101677246A (en) * | 2008-09-19 | 2010-03-24 | 扬智科技股份有限公司 | Digital-to-analogue conversion system with sampling frequency conversion and sampling frequency conversion method thereof |
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| US7038733B2 (en) * | 2002-01-30 | 2006-05-02 | Ericsson Inc. | Television receivers and methods for processing signal sample streams synchronously with line/frame patterns |
| JP4982080B2 (en) * | 2005-12-16 | 2012-07-25 | パナソニック株式会社 | Digital filter |
| US8738679B2 (en) * | 2009-07-03 | 2014-05-27 | Stmicroelectronics International N.V. | Offset-free sinc interpolator and related methods |
| US8212594B2 (en) * | 2010-08-11 | 2012-07-03 | Integrated Device Technology, Inc. | Methods and apparatuses for clock domain crossing |
| JP5624585B2 (en) * | 2012-06-15 | 2014-11-12 | 株式会社東芝 | PLL circuit and communication device |
| EP2966778B1 (en) * | 2014-07-11 | 2016-11-09 | The Swatch Group Research and Development Ltd. | Digital interpolator and method of interpolating |
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| JP2008199220A (en) * | 2007-02-09 | 2008-08-28 | Toshiba Corp | Ad conversion processing circuit and demodulation device |
| CN101677246A (en) * | 2008-09-19 | 2010-03-24 | 扬智科技股份有限公司 | Digital-to-analogue conversion system with sampling frequency conversion and sampling frequency conversion method thereof |
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