CN113098466A - Positive and negative group delay offset group delay planarization processing system - Google Patents
Positive and negative group delay offset group delay planarization processing system Download PDFInfo
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- CN113098466A CN113098466A CN202110338706.9A CN202110338706A CN113098466A CN 113098466 A CN113098466 A CN 113098466A CN 202110338706 A CN202110338706 A CN 202110338706A CN 113098466 A CN113098466 A CN 113098466A
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
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Abstract
The invention discloses a group delay flattening processing system for counteracting positive and negative group delay, which comprises a positive group delay network and a negative group delay network which are connected in sequence, wherein the input end of the positive group delay network is the input end of a signal, the signal is subjected to positive group delay signal processing in the positive group delay network, the output end of the positive group delay network is connected with the input end of the negative group delay network, the signal is subjected to negative group delay signal processing in the negative group delay network, and the output end of the negative group delay network is the output end of the signal. The signal delay processing system for counteracting the positive group delay and the negative group delay has the characteristics of group delay flattening, wide delay working bandwidth, adjustable delay value and the like.
Description
Technical Field
The invention relates to the technical field of microwave, radio frequency and digital integrated circuits, in particular to a positive and negative group delay offset group delay planarization processing system.
Background
In recent years, with the development of modern communication technology, the requirements of microwave/radio frequency systems such as computer digital systems and radars on signal delay are increasing, and delay circuits with flat group delay and adjustable delay value are widely applied in many fields as one of important components in microwave/radio frequency systems and digital systems.
The delay circuit is used for delaying an electric signal for a period of time, and changing a delay value, group delay flatness and effective working bandwidth of the delay circuit by adjusting internal device values, so that the delay circuit is widely applied to various electronic and communication systems, such as computer digital systems, microwave/radio frequency communication transceiver systems, microwave photonics fields and the like.
The non-flatness of the group delay of the system usually causes phase distortion of signals, reduces the signal-to-noise ratio and the speed of the system, and how to improve the flatness of the group delay of the signals and perform offset or advance processing of the signal delay by adjusting the delay value of the system is a technical problem to be solved urgently in the current communication system.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a signal delay processing system for positive and negative group delay offset, which has the advantages of group delay flattening, wide delay working bandwidth and adjustable delay value.
The purpose of the invention is realized by the following technical scheme:
the utility model provides a positive negative group delay counteractive group delay flattening processing system, is including the positive group delay network and the negative group delay network that connect gradually, the input of positive group delay network is the input of signal, and the signal carries out positive group delay signal processing at positive group delay network, and the output of positive group delay network is connected with the input of negative group delay network, and the signal carries out negative group delay signal processing at negative group delay network, and the output of negative group delay network is the output of signal.
Preferably, the positive group delay network is formed by a left-handed transmission line formed by a capacitor and an inductor, the capacitor and the inductor form a T-shaped structure, a signal enters through one end of the first capacitor, the other end of the first capacitor is connected with one end of the inductor and one end of the second capacitor, the other end of the inductor is connected with the ground, and the output end of the second capacitor is the output end of the positive group delay network. By adjusting the variable capacitance value, the positive group delay value and the effective working bandwidth are changed.
Preferably, the positive group delay value and the effective operating bandwidth are varied by adjusting a variable capacitance value of the positive group delay network.
Preferably, the negative group delay network is composed of an adjustable resistor, an adjustable capacitor and an inductor, and the adjustable resistor, the adjustable capacitor and the inductor are connected in parallel.
Preferably, the group delay flatness of the positive and negative group delay offset is realized by adjusting the resistance value and the capacitance value of the negative group delay network, changing the negative group delay value and the effective working bandwidth, and adjusting the group delay flatness.
The invention has the beneficial effects that: the invention adopts the positive group delay network and the negative group delay network which are composed of the passive capacitance inductor and the resistor as the delay adjusting circuit, changes the group delay value and the working bandwidth by adjusting the capacitance and the resistance value, realizes the cancellation of the positive group delay and the negative group delay and the planarization of the group delay, improves the delay adjustability of the system and the planarization of the group delay, and has the advantages of easy integration, adjustable delay, flat group delay, easy realization and the like.
Drawings
FIG. 1 is an overall schematic diagram of a positive and negative group delay cancelled group delay planarization system of the present invention;
FIG. 2 is a schematic diagram of the structure of the positive group delay network according to the present invention using left-handed material;
fig. 3 is a schematic diagram of the negative group delay network structure of the present invention.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
Fig. 1 is an overall schematic diagram of a positive-negative group delay offset group delay flattening processing system according to a preferred embodiment of the present invention, which includes a positive group delay network and a negative group delay network, wherein an input end of the positive group delay network is an input end of a signal, an output end of the positive group delay network is connected to an input end of the negative group delay network, and an output end of the negative group delay network is an output end of the signal.
Firstly, inputting a signal into a positive group delay network, carrying out positive group delay adjustment, then entering a negative group delay network, carrying out negative group delay adjustment, carrying out delay value and bandwidth adjustment through element values in an adjusting module, realizing positive and negative group delay offset and group delay flattening processing, and finally outputting the signal from an output end of the negative group delay network.
Fig. 2 is a schematic structural diagram of the positive group delay network using the left-handed material according to the present invention. The structure utilizes the characteristics of large positive group delay variation range, easy integration and easy realization of left-handed materials, the left-handed materials consisting of two adjustable capacitors and an inductor are used as a positive group delay network module, the capacitors and the inductor form a T-shaped structure, a signal enters through one end of a first capacitor, the other end of the first capacitor is connected with one end of the inductor and one end of a second capacitor, the other end of the inductor is connected with the ground, and the output end of the second capacitor is the output end of the positive group delay network. By changing the capacitance value, the adjustment of the positive group delay value and the bandwidth is performed.
Fig. 3 is a schematic diagram of a negative group delay network structure according to the present invention, in which an adjustable resistor, an adjustable capacitor and an inductor are connected in parallel to form a negative group delay network module, one end of the parallel connection of the resistor, the capacitor and the inductor is connected to an input terminal, and the other end is used as a signal output terminal. The signal enters the negative group delay network to generate the advanced processing of the delay time, namely, the negative group delay is generated, the negative group delay value and the bandwidth of the signal are changed by adjusting the resistance value and the capacitance value, and the component values in the positive group delay network module and the negative group delay network module are comprehensively adjusted, so that the adjustment of the delay time of the whole delay circuit, the offset processing of the positive group delay and the negative group delay, the flattening of the group delay and the change of the effective working bandwidth of the signal can be realized.
The invention relates to a group delay flattening processing system for counteracting positive and negative group delay, which comprises a positive group delay network and a negative group delay network which are cascaded, wherein the group delay characteristic of the whole system is counteracted and compensated by adopting a method based on positive and negative group delay cascade, so that the integrally output group delay is flattened; the positive group delay network is made of left-handed materials composed of inductance and capacitance, and the negative group delay network is made of inductance and capacitance resistance parallel networks. The invention adopts passive devices to realize the adjustment of the working frequency range signal delay amount and the group delay flatness, and has the advantages of simple composition, easy integration, low power consumption, wide signal bandwidth and the like.
The delay processing method and the delay circuit for implementing group delay flattening by positive and negative group delay cancellation according to the present invention are described above by way of example with reference to the accompanying drawings. However, it should be understood by those skilled in the art that various modifications can be made to the positive and negative group delay offset group delay flattening processing method of the present invention without departing from the scope of the present invention. Therefore, the scope of the present invention should be determined by the contents of the appended claims.
Claims (5)
1. The positive group delay network and the negative group delay network are sequentially connected, the input end of the positive group delay network is the input end of a signal, the output end of the positive group delay network is connected with the input end of the negative group delay network, and the output end of the negative group delay network is the output end of the signal.
2. The positive-negative group delay cancelled group delay flattening processing system according to claim 1, wherein the positive group delay network is formed by a left-handed transmission line composed of a capacitor and an inductor, the capacitor and the inductor form a T-shaped structure, a signal enters through one end of a first capacitor, the other end of the first capacitor is connected with one end of the inductor and one end of a second capacitor, the other end of the inductor is connected with ground, and the output end of the second capacitor is the output end of the positive group delay network.
3. The positive-negative group delay cancelled group delay flattening processing system of claim 2, wherein the positive group delay value and the effective operating bandwidth are changed by adjusting a variable capacitance value of the positive group delay network.
4. The positive-negative group delay cancelled group delay flattening processing system of claim 1, wherein the negative group delay network is comprised of an adjustable resistor, an adjustable capacitor and an inductor, the adjustable resistor, the adjustable capacitor and the inductor being connected in parallel.
5. The positive-negative group delay offset group delay flattening processing system of claim 4, wherein the positive-negative group delay offset group delay flattening is achieved by adjusting the resistance and capacitance of the negative group delay network to change the negative group delay value and the effective operating bandwidth.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110338706.9A CN113098466A (en) | 2021-03-29 | 2021-03-29 | Positive and negative group delay offset group delay planarization processing system |
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| CN202110338706.9A CN113098466A (en) | 2021-03-29 | 2021-03-29 | Positive and negative group delay offset group delay planarization processing system |
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Citations (6)
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|---|---|---|---|---|
| JP2007088617A (en) * | 2005-09-20 | 2007-04-05 | Mitsubishi Electric Corp | Feedforward amplifier |
| CN103684346A (en) * | 2013-12-31 | 2014-03-26 | 南京理工大学 | Dual-band high-performance negative group delay circuit |
| CN103716024A (en) * | 2013-12-31 | 2014-04-09 | 南京理工大学 | Combined negative group delay circuit |
| CN104852700A (en) * | 2015-06-12 | 2015-08-19 | 王少夫 | Zero-adjustment group delay circuit |
| CN105978531A (en) * | 2016-05-09 | 2016-09-28 | 复旦大学 | Real time time-delay phase shifter based on negative group delay compensation |
| KR102010010B1 (en) * | 2018-01-26 | 2019-10-21 | 전북대학교산학협력단 | Cross Cancellation Linear Power Amplifier with Negative Group Delay Circuit |
-
2021
- 2021-03-29 CN CN202110338706.9A patent/CN113098466A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007088617A (en) * | 2005-09-20 | 2007-04-05 | Mitsubishi Electric Corp | Feedforward amplifier |
| CN103684346A (en) * | 2013-12-31 | 2014-03-26 | 南京理工大学 | Dual-band high-performance negative group delay circuit |
| CN103716024A (en) * | 2013-12-31 | 2014-04-09 | 南京理工大学 | Combined negative group delay circuit |
| CN104852700A (en) * | 2015-06-12 | 2015-08-19 | 王少夫 | Zero-adjustment group delay circuit |
| CN105978531A (en) * | 2016-05-09 | 2016-09-28 | 复旦大学 | Real time time-delay phase shifter based on negative group delay compensation |
| KR102010010B1 (en) * | 2018-01-26 | 2019-10-21 | 전북대학교산학협력단 | Cross Cancellation Linear Power Amplifier with Negative Group Delay Circuit |
Non-Patent Citations (1)
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| 张玉兴,杨玉梅,敬守钊等: "《射频模拟电路与系统》", 30 September 2008, 电子科技大学出版社 * |
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Application publication date: 20210709 |