CN204681325U - A kind of adjusting zero group delay circuitry - Google Patents

A kind of adjusting zero group delay circuitry Download PDF

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Publication number
CN204681325U
CN204681325U CN201520404158.5U CN201520404158U CN204681325U CN 204681325 U CN204681325 U CN 204681325U CN 201520404158 U CN201520404158 U CN 201520404158U CN 204681325 U CN204681325 U CN 204681325U
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China
Prior art keywords
group delay
transistor
resonant element
zero
delay circuitry
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Expired - Fee Related
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CN201520404158.5U
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Chinese (zh)
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不公告发明人
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Abstract

The utility model relates to a kind of adjusting zero group delay circuitry.This circuit structure adopts transmission line, film resistor, transistor and series connection RLC resonant circuit to realize.Mainly utilize the positive group delay (PGD) of transmission line and negative group delay (PGD) characteristic of resonant element to balance each other, produce the group delay close to zero.The utility model efficiently solve most of microwave device use time owing to producing positive group delay, cause the problem of system performance degradation.And can according to specific needs, the negative group delay size of setting, realizes adjustable function.This circuit structure adaptability is good, and stability is high.The circuit structure that the utility model adopts has wider bandwidth, can realize zero group delay function, can be widely used in needing in the corresponding band system of adjusting zero group delay in various different frequency range.

Description

A kind of adjusting zero group delay circuitry
Technical field
The utility model relates to zero group delay circuitry, and particularly a kind of adjusting zero group delay circuitry, belongs to electronics and the communications field.
Background technology
In the last few years, a series of research about group delay circuitry negative in filtering and broadband matching network had been carried out both at home and abroad.Achieve a lot of achievement in research, be especially used in mobile communication technology, be used in power-amplifier front-end and radar antenna feed part, negative group delay circuitry effectively can solve that system linear degree is low, narrow bandwidth, problem that passband external noise is large.But its project organization can only use in specific frequency range, and bandwidth is less, signal attenuation is comparatively large, causes the number having to increase power amplifier, and make system bulk comparatively large, versatility is not strong.Simultaneously traditional negative group delay circuitry is due to the problem of its circuit structure, and make temperature sensitivity extremely strong, applicability is very limited.The utility model, for above problem, can effectively solve, and to meet system requirements, and stability is high, volume is little, processing is simple, applied widely, and effective address signal is decayed excessive problem.
Summary of the invention
The utility model object be to provide a kind of principle, structure utilizing transmission line to produce positive group delay effect and negative group delay to carry out balancing simple, the zero group delay microwave circuit that negative group delay, stabilized susceptibility are little, processing is simple, multiband, wider bandwidth, volume are little, stability is high can be regulated.
The technical scheme realizing the utility model object is: a kind of adjusting zero group delay circuitry, comprises AC power, and its input impedance is ; Input port 1, output port 2, microstrip line, transistor and series connection resonant element; Wherein one end of microstrip line is connected with the gate pole of transistor, and the gate pole of transistor is by film resistor ground connection; The drain electrode of transistor with connect resonant element one end is connected, the source ground of transistor; resonant element other end ground connection; Input port 1 and output port 2 all connect 50 ohmages.
Compared with prior art, because the utility model adopts microstrip line construction and the cascade of negative group delay circuitry phase, be with
The remarkable advantage come is: (1) zero group delay is adjustable; (2) bandwidth is adjustable; (3) volume is little; (4) stability is high; (6) frequency range is controlled; Be applicable in the various system higher to performance requirement.
Accompanying drawing explanation
Fig. 1 is a kind of adjusting zero group delay circuitry of the utility model structural representation.
Fig. 2 is the negative group delay circuitry figure of a kind of adjusting zero of the utility model group delay circuitry.
Fig. 3 be the negative delay signal S21 curve chart of a kind of adjusting zero group delay circuitry of the utility model (wherein ).
Fig. 4 is the phase characteristic figure of a kind of adjusting zero group delay circuitry of the utility model.
Fig. 5 is a kind of adjusting zero group delay circuitry of the utility model figure.
Fig. 6 is a kind of adjusting zero group delay phase place of the utility model and group delay property curve (a). phase characteristic (b). and group delay property.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail.
Composition graphs 1, the utility model is a kind of adjusting zero group delay circuitry, chooses the group delay circuitry of 2-8GHz frequency range as an example, be described at this.This novel adjusting zero group delay circuitry, comprise AC power, its input impedance is ; Port one, output port 2, microstrip line, transistor and series connection resonant element; Wherein one end of microstrip line is connected with the gate pole of transistor, and the gate pole of transistor is by film resistor ground connection; The drain electrode of transistor with connect resonant element one end is connected, the source ground of transistor; resonant element other end ground connection; Input port 1 and output port 2 all connect 50 ohmages.
Transmission line (TL) adopts distributed Microstrip line to realize, and it can produce positive group delay (PGD) characteristic, and negative group delay circuitry unit adopts transistor AND gate series resonance unit component carries out cascade realization.In series connection RLC resonant element, the size of resistance R can change the size of negative group delay, thus reaches adjustable function.
Composition graphs 1, mainly utilizes the positive group delay of transmission line and the negative group delay property of resonant element to balance each other, produces the group delay property close to zero.Composition graphs 2, can be changed the size of negative group delay by the size of resistance R in series connection RLC resonant element, thus reach adjustable function, can adjust amount of bandwidth again, very easily Circuit tuning performance, to meet performance requirement.
Composition graphs 3 and Fig. 4, obviously can find out the adjustable function of negative group delay circuitry, work as resonant element choose R and get different numerical value, its negative group delay (NGD) characteristic has adjustable function.
Composition graphs 1, Fig. 5, the utility model adjusting zero group delay circuitry, its operation principle is summarized as follows: adjusting zero
The basic model of group delay circuitry is that transmission line (TL) adopts distributed Microstrip line to realize, and it can produce positive group delay property, and negative group delay circuitry unit adopts transistor AND gate series resonance unit component carries out cascade realization.Utilize the positive group delay (PGD) of transmission line and negative group delay (NGD) characteristic of resonant element to balance each other, produce the group delay property close to zero.
The utility model adjusting zero group delay circuitry is realized by microstrip line, active transistor and RLC resonant element, and processing is simple, and good stability, reliability is high.
Composition graphs 6, the utility model adjusting zero group delay circuitry, this circuit structure is realized by microstrip line, active transistor and RLC resonant element, utilizes positive and negative group delay equilibrium principle, makes this zero group delay circuitry show good performance.

Claims (3)

1. an adjusting zero group delay circuitry, is characterized in that: comprise AC power, and its input impedance is Z 0, output impedance is Z l; Input port 1, output port 2, microstrip line, transistor and series connection RLC resonant element; Wherein one end of microstrip line is connected with the gate pole of transistor, and the gate pole of transistor is by film resistor ground connection; The drain electrode of transistor is connected with series connection RLC resonant element one end, the source ground of transistor; RLC resonant element other end ground connection; Input port 1 and output port 2 all connect 50 ohmages.
2. according to the adjusting zero group delay circuitry described in claim 1, it is characterized in that: mainly utilize the positive group delay of transmission line and the negative group delay property of resonant element to balance each other, produce the group delay property close to zero; Transmission line (TL) adopts distributed Microstrip line to realize, and it can produce positive group delay property, and negative group delay circuitry unit adopts transistor AND gate RLC series resonance unit component to carry out cascade realization.
3. according to the adjusting zero group delay circuitry described in claim 1, it is characterized in that: by regulating the resistance R of series connection RLC resonant element, negative group delay can be realized adjustable.
CN201520404158.5U 2015-06-12 2015-06-12 A kind of adjusting zero group delay circuitry Expired - Fee Related CN204681325U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520404158.5U CN204681325U (en) 2015-06-12 2015-06-12 A kind of adjusting zero group delay circuitry

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520404158.5U CN204681325U (en) 2015-06-12 2015-06-12 A kind of adjusting zero group delay circuitry

Publications (1)

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CN204681325U true CN204681325U (en) 2015-09-30

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CN201520404158.5U Expired - Fee Related CN204681325U (en) 2015-06-12 2015-06-12 A kind of adjusting zero group delay circuitry

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104852700A (en) * 2015-06-12 2015-08-19 王少夫 Zero-adjustment group delay circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104852700A (en) * 2015-06-12 2015-08-19 王少夫 Zero-adjustment group delay circuit

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150930

Termination date: 20160612

CF01 Termination of patent right due to non-payment of annual fee