WO2023098918A1 - Second-order adjustable lc notch filter for pole zero tracking - Google Patents
Second-order adjustable lc notch filter for pole zero tracking Download PDFInfo
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- WO2023098918A1 WO2023098918A1 PCT/CN2022/136957 CN2022136957W WO2023098918A1 WO 2023098918 A1 WO2023098918 A1 WO 2023098918A1 CN 2022136957 W CN2022136957 W CN 2022136957W WO 2023098918 A1 WO2023098918 A1 WO 2023098918A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H2011/0488—Notch or bandstop filters
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- the invention relates to the technical field of electronic circuits, in particular to a pole-zero tracking second-order LC notch filter circuit, which belongs to the technical field of notch filter design.
- image interference refers to the interference signal generated during the up-mixing and down-mixing process of the signal.
- the generation of the image signal not only has a great impact on its own transceiver system, but also affects other useful channels through the transmitter into the space. Due to the harm of the image signal, the image rejection ratio is an indispensable index in the transceiver system.
- the method of adopting the I/Q road structure requires the I road and the Q road, which greatly increases the area and power consumption of the system. For the above reasons, the method of adopting the notch filter is more attractive to improve the performance of the transceiver system.
- the main challenge currently faced in notch filter design is how to effectively suppress image frequency signals in the wideband feedback range.
- the bandwidth and gain of the useful signal should also be kept unchanged.
- the technical problem to be solved by the present invention is: provide a second-order adjustable LC notch filter for pole-zero tracking, based on the second-order LC filter network, realize the pole-zero tracking function through parallel switching capacitors, and then realize the transceiver Tracking suppression of image signals; in the broadband range, effectively improve the image signal rejection ratio of transceivers.
- a second-order adjustable LC notch filter for pole-zero tracking including: an input terminal, a first series inductance of a filter, a second series inductance of a filter, a filter The third parallel inductance of the device, the parallel switched capacitor, the output terminal and the node; wherein, the input terminal, the first series inductor of the filter, the second series inductor of the filter, and the output terminal are sequentially connected in series, and the two ends of the parallel switched capacitor are respectively connected to the input terminal and the output terminal; the connection point of the first series inductance of the filter and the second series inductance of the filter is a node, one end of the third parallel inductance of the filter is connected to the node, and the other end is grounded.
- the parallel switched capacitors are adjustable parallel switched capacitors to achieve frequency tuning.
- the parallel switched capacitor is composed of several branches connected in parallel, the first branch is the second capacitor; the second branch is composed of the third capacitor, the fourth switching transistor, and the fourth capacitor in series; the third The first branch is composed of the fifth capacitor, the third switching transistor, and the sixth capacitor in series; the fourth branch is composed of the seventh capacitor, the second switching transistor, and the eighth capacitor in series; the fifth branch is It is composed of the ninth capacitor, the first switching transistor, and the tenth capacitor in series; the two ends of the several branches connected in parallel are the two ends of the parallel switching capacitor, one end is the second node, and the other end is the third node. node.
- the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are all N-type transistors.
- the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor, the eighth capacitor, the ninth capacitor, and the tenth capacitor have the same capacitance value.
- the capacitance value of the second capacitor (C2) is based on the zero frequency ⁇ z0 of the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor in the off state of the notch filter and the first series connection of the filter
- the inductance (L1), the second series inductance of the filter (L2), and the third series inductance of the filter (L3) are determined. Its value is calculated as follows:
- the gate of the first transistor is connected to the zeroth digital control signal
- the gate of the second transistor is connected to the first digital control signal
- the gate of the third transistor is connected to the second digital control signal
- the gate of the fourth transistor is connected to the third digital control signal Signal.
- the change of the zeroth digital control signal, the first digital control signal, the second digital control signal, and the third digital control signal can change the capacitance value of the parallel switch capacitor, so that the pole-zero frequency moves proportionally, thereby improving Image signal rejection ratio.
- the first series inductance of the filter, the second series inductance of the filter, and the third parallel inductance of the filter are planar inductors or cylindrical inductors.
- the circuit structure of the second-order LC notch filter based on pole-zero point tracking of the present invention generates a zero point at the frequency of the image signal, and simultaneously generates a pole at the frequency of the useful signal; realizes filtering the image signal while retaining the useful signal;
- the zero-pole synchronous tracking is realized by switching parallel capacitors, and the suppression of broadband image signals is realized.
- FIG. 1 is a schematic diagram of a second-order tunable LC notch filter based on pole-zero tracking in the present invention.
- FIG. 2 is a schematic diagram of a second-order adjustable LC notch filter circuit switch adjustable shunt capacitor based on a pole-zero tracking according to the present invention.
- a second-order adjustable LC notch filter for pole-zero tracking of the present invention includes: input terminal Input, filter first series inductance L1, filter second series inductance L2, filter third Parallel inductor L3, parallel switched capacitor C1, output terminal Output and node A; wherein, the input terminal Input, the first series inductor L1 of the filter, the second series inductor L2 of the filter, and the output terminal Output are sequentially connected in series, and the parallel switched capacitor C1 The two ends are respectively connected to the input terminal Input and the output terminal Output; the connection point of the first series inductance L1 of the filter and the second series inductance L2 of the filter is node A, one end of the third parallel inductance L3 of the filter is connected to the node A, and the other end grounded.
- the first series inductance L1 of the filter, the second series inductance L2 of the filter, and the third parallel inductance L3 of the filter are planar inductors or cylindrical inductors.
- the switched parallel capacitor C1 of the present invention is an adjustable parallel switched capacitor to realize frequency tuning.
- the parallel switched capacitor C1 is composed of several branches connected in parallel, the first branch is the second capacitor C2; the second branch is composed of the third capacitor C3, the fourth switching transistor M4, and the fourth capacitor C4 in sequence Composed in series; the third branch is composed of the fifth capacitor C5, the third switching transistor M3, and the sixth capacitor C6 in series; the fourth branch is composed of the seventh capacitor C7, the second switching transistor M2, and the eighth capacitor C8 is sequentially connected in series; the fifth branch is composed of the ninth capacitor C9, the first switching transistor M1, and the tenth capacitor C10; Two ends, one end is the second node N, and the other end is the third node P.
- the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, and the tenth capacitor C10 have the same capacitance value.
- the first switch transistor M1 , the second switch transistor M2 , the third switch transistor M3 , and the fourth switch transistor M4 are all N-type transistors.
- the ninth capacitor C9 is respectively connected to the second node N and the drain terminal of the first transistor M1
- the tenth capacitor C10 is respectively connected to the third node P and the source terminal of the first transistor M1
- the seventh capacitor C7 is respectively connected to the second node N and the drain end of the second transistor M2
- the eighth capacitor C8 is respectively connected to the third node P and the source end of the second transistor M2
- the fifth capacitor C5 is respectively connected to the second node N and the drain end of the third transistor M3
- the sixth capacitor C6 is respectively Connect the third node P and the source terminal of the third transistor M3
- the third capacitor C3 is respectively connected to the second node N and the drain terminal of the fourth transistor M4
- the fourth capacitor C4 is respectively connected to the third node P and the source terminal of the fourth transistor M4, and the third capacitor C3 is respectively connected to the third node P and the source terminal of the fourth transistor M4.
- the second capacitor C2 is connected between the second node N and the third node P, the gate of the first transistor M1 is connected to the zeroth digital control signal B0, the gate of the second transistor M2 is connected to the first digital control signal B1, and the gate of the third transistor M1 is connected to the first digital control signal B1.
- the gate of the transistor M3 is connected to the second digital control signal B2, and the gate of the fourth transistor M4 is connected to the third digital control signal B3.
- the pole-zero point tracking pole of the second-order LC notch filter circuit can be obtained as:
- the filter pole-to-zero ratio is independent of the switched shunt capacitor C1.
- the capacitance value of the parallel switch capacitor C1 can be changed, so that the frequency of the pole and zero points can be moved proportionally, thereby improving the image signal rejection ratio in the broadband range.
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Abstract
Disclosed in the present invention is a second-order adjustable LC notch filter for pole zero tracking. An input end (Input), a filter first series inductor (L1), a filter second series inductor (L2) and an output end (Output) are sequentially connected in series. Two ends of a parallel switch-capacitor (C1) are respectively connected to the input end (Input) and the output end (Output). The point connecting the filter first series inductor (L1) and the filter second series inductor (L2) is a node (A). One end of a filter third parallel inductor (L3) is connected to the node (A), and the other end thereof is grounded. The invention employs a parallel switch-capacitor to realize pole zero tracking on the basis of a second-order LC filter network, thereby realizing tracking and rejection of image signals by a broadband transceiver, and effectively increasing an image signal rejection ratio in a broadband range.
Description
本发明涉及电子电路技术领域，尤其是一种极零点跟踪二阶LC陷波滤波器电路，属于陷波滤波器设计的技术领域。The invention relates to the technical field of electronic circuits, in particular to a pole-zero tracking second-order LC notch filter circuit, which belongs to the technical field of notch filter design.
在收发机系统中，镜像干扰是指信号在上、下混频过程中产生的干扰信号。镜像信号的产生不仅对自身收发机系统有很大的影响，还会通过发射机发射到空间中影响其它有用信道。由于镜像信号的危害，镜像抑制比是收发机系统中不可或缺的指标。实现镜像抑制常用的方法有两种：第一种收发机系统采用I/Q路结构；第二种是增加陷波滤波器。采用I/Q路结构的方法需要I路和Q路，大大增加了系统的面积和功耗。由于以上原因，采用陷波滤波器的方法对收发系统性能提升更加有吸引力。In the transceiver system, image interference refers to the interference signal generated during the up-mixing and down-mixing process of the signal. The generation of the image signal not only has a great impact on its own transceiver system, but also affects other useful channels through the transmitter into the space. Due to the harm of the image signal, the image rejection ratio is an indispensable index in the transceiver system. There are two commonly used methods to realize image suppression: the first transceiver system adopts I/Q circuit structure; the second is to add a notch filter. The method of adopting the I/Q road structure requires the I road and the Q road, which greatly increases the area and power consumption of the system. For the above reasons, the method of adopting the notch filter is more attractive to improve the performance of the transceiver system.
目前在陷波滤波器设计中面临的主要挑战是如何在宽带反馈范围内有效抑制镜像频率信号。此外，对于极零点跟踪二阶LC陷波滤波器电路而言，在有效抑制宽带镜像信号时，还应保证有用信号的带宽和增益不变。The main challenge currently faced in notch filter design is how to effectively suppress image frequency signals in the wideband feedback range. In addition, for the pole-zero point tracking second-order LC notch filter circuit, when the broadband image signal is effectively suppressed, the bandwidth and gain of the useful signal should also be kept unchanged.
发明内容Contents of the invention
技术问题：本发明所要解决的技术问题为：提供一种极零点跟踪的二阶可调LC陷波滤波器，基于二阶LC滤波网络，通过并联开关电容实现极零点跟踪功能，进而实现收发机镜像信号的跟踪抑制；在宽带范围内，有效提高收发机镜像信号抑制比。Technical problem: The technical problem to be solved by the present invention is: provide a second-order adjustable LC notch filter for pole-zero tracking, based on the second-order LC filter network, realize the pole-zero tracking function through parallel switching capacitors, and then realize the transceiver Tracking suppression of image signals; in the broadband range, effectively improve the image signal rejection ratio of transceivers.
技术方案：为解决上述技术问题，本发明提出了.一种极零点跟踪的二阶可调LC陷波滤波器，包括：输入端、滤波器第一串联电感、滤波器第二串联电感、滤波器第三并联电感、并联开关电容、输出端和节点；其中，输入端、滤波器第一串联电感、滤波器第二串联电感、输出端顺序串联连接，并联开关电容的两端分别连接输入端和输出端；滤波器第一串联电感、滤波器第二串联电感的连接点为节点，滤波器第三并联电感的一端连接该节点，另一端接地。Technical solution: In order to solve the above technical problems, the present invention proposes. A second-order adjustable LC notch filter for pole-zero tracking, including: an input terminal, a first series inductance of a filter, a second series inductance of a filter, a filter The third parallel inductance of the device, the parallel switched capacitor, the output terminal and the node; wherein, the input terminal, the first series inductor of the filter, the second series inductor of the filter, and the output terminal are sequentially connected in series, and the two ends of the parallel switched capacitor are respectively connected to the input terminal and the output terminal; the connection point of the first series inductance of the filter and the second series inductance of the filter is a node, one end of the third parallel inductance of the filter is connected to the node, and the other end is grounded.
所述的并联开关电容为可调并联开关电容，实现频率调谐。The parallel switched capacitors are adjustable parallel switched capacitors to achieve frequency tuning.
所述并联开关电容由相互并联的几条支路组成，第一条支路为第二电容；第 二条支路为由第三电容、第四开关晶体管、第四电容顺序串联组成；第三条支路为由第五电容、第三开关晶体管、第六电容顺序串联组成；第四条支路为由第七电容、第二开关晶体管、第八电容顺序串联组成；第五条支路为由第九电容、第一开关晶体管、第十电容顺序串联组成；所述的几条支路相互并联的两端即为并联开关电容的两端，其一端为第二节点，另一端为第三节点。The parallel switched capacitor is composed of several branches connected in parallel, the first branch is the second capacitor; the second branch is composed of the third capacitor, the fourth switching transistor, and the fourth capacitor in series; the third The first branch is composed of the fifth capacitor, the third switching transistor, and the sixth capacitor in series; the fourth branch is composed of the seventh capacitor, the second switching transistor, and the eighth capacitor in series; the fifth branch is It is composed of the ninth capacitor, the first switching transistor, and the tenth capacitor in series; the two ends of the several branches connected in parallel are the two ends of the parallel switching capacitor, one end is the second node, and the other end is the third node. node.
所述第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管均为N型晶体管。The first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are all N-type transistors.
所述第三电容、第四电容、第五电容、第六电容、第七电容、第八电容、第九电容、第十电容电容值相同。The third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor, the eighth capacitor, the ninth capacitor, and the tenth capacitor have the same capacitance value.
所述第二电容(C2)电容值根据陷波滤波器第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管均关断状态下的零点频率ω
z0和滤波器第一串联电感(L1)、滤波器第二串联电感(L2)，滤波器第三串联电感(L3)决定。其值具体计算如下：
The capacitance value of the second capacitor (C2) is based on the zero frequency ω z0 of the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor in the off state of the notch filter and the first series connection of the filter The inductance (L1), the second series inductance of the filter (L2), and the third series inductance of the filter (L3) are determined. Its value is calculated as follows:
第一晶体管的栅极接第零数字控制信号，第二晶体管的栅极接第一数字控制信号，第三晶体管的栅极接第二数字控制信号，第四晶体管的栅极接第三数字控制信号。The gate of the first transistor is connected to the zeroth digital control signal, the gate of the second transistor is connected to the first digital control signal, the gate of the third transistor is connected to the second digital control signal, and the gate of the fourth transistor is connected to the third digital control signal Signal.
所述第零数字控制信号、第一数字控制信号、第二数字控制信号、第三数字控制信号的改变，可改变并联开关电容电容值，使得极零点频率等比例移动，从而在宽带范围内提升镜像信号抑制比。The change of the zeroth digital control signal, the first digital control signal, the second digital control signal, and the third digital control signal can change the capacitance value of the parallel switch capacitor, so that the pole-zero frequency moves proportionally, thereby improving Image signal rejection ratio.
所述滤波器第一串联电感、滤波器第二串联电感、滤波器第三并联电感为平面电感器或圆柱形电感器。The first series inductance of the filter, the second series inductance of the filter, and the third parallel inductance of the filter are planar inductors or cylindrical inductors.
有益效果：本发明的基于极零点跟踪二阶LC陷波滤波器电路结构，在镜像信号频率处产生零点，并同时在有用信号频率处产生极点；实现将镜像信号滤波，并同时保留有用信号；通过开关并联电容实现零极点同步跟踪，实现宽带镜像信号的抑制。Beneficial effects: the circuit structure of the second-order LC notch filter based on pole-zero point tracking of the present invention generates a zero point at the frequency of the image signal, and simultaneously generates a pole at the frequency of the useful signal; realizes filtering the image signal while retaining the useful signal; The zero-pole synchronous tracking is realized by switching parallel capacitors, and the suppression of broadband image signals is realized.
图1为本发明基于一种极零点跟踪的二阶可调LC陷波滤波器示意图。FIG. 1 is a schematic diagram of a second-order tunable LC notch filter based on pole-zero tracking in the present invention.
图2为本发明基于一种极零点跟踪的二阶可调LC陷波滤波器电路开关可调并联电容示意图。FIG. 2 is a schematic diagram of a second-order adjustable LC notch filter circuit switch adjustable shunt capacitor based on a pole-zero tracking according to the present invention.
下面结合附图对本发明做更进一步的解释。The present invention will be further explained below in conjunction with the accompanying drawings.
如图1所示，本发明的一种极零点跟踪的二阶可调LC陷波滤波器包括：输入端Input、滤波器第一串联电感L1、滤波器第二串联电感L2、滤波器第三并联电感L3、并联开关电容C1、输出端Output和节点A；其中，输入端Input、滤波器第一串联电感L1、滤波器第二串联电感L2、输出端Output顺序串联连接，并联开关电容C1的两端分别连接输入端Input和输出端Output；滤波器第一串联电感L1、滤波器第二串联电感L2的连接点为节点A，滤波器第三并联电感L3的一端连接该节点A，另一端接地。所述滤波器第一串联电感L1、滤波器第二串联电感L2、滤波器第三并联电感L3为平面电感器或圆柱形电感器。As shown in Figure 1, a second-order adjustable LC notch filter for pole-zero tracking of the present invention includes: input terminal Input, filter first series inductance L1, filter second series inductance L2, filter third Parallel inductor L3, parallel switched capacitor C1, output terminal Output and node A; wherein, the input terminal Input, the first series inductor L1 of the filter, the second series inductor L2 of the filter, and the output terminal Output are sequentially connected in series, and the parallel switched capacitor C1 The two ends are respectively connected to the input terminal Input and the output terminal Output; the connection point of the first series inductance L1 of the filter and the second series inductance L2 of the filter is node A, one end of the third parallel inductance L3 of the filter is connected to the node A, and the other end grounded. The first series inductance L1 of the filter, the second series inductance L2 of the filter, and the third parallel inductance L3 of the filter are planar inductors or cylindrical inductors.
如图2所示，本发明开关并联电容C1为可调并联开关电容，实现频率调谐。As shown in FIG. 2 , the switched parallel capacitor C1 of the present invention is an adjustable parallel switched capacitor to realize frequency tuning.
所述并联开关电容C1由相互并联的几条支路组成，第一条支路为第二电容C2；第二条支路为由第三电容C3、第四开关晶体管M4、第四电容C4顺序串联组成；第三条支路为由第五电容C5、第三开关晶体管M3、第六电容C6顺序串联组成；第四条支路为由第七电容C7、第二开关晶体管M2、第八电容C8顺序串联组成；第五条支路为由第九电容C9、第一开关晶体管M1、第十电容C10顺序串联组成；所述的几条支路相互并联的两端即为并联开关电容C1的两端，其一端为第二节点N，另一端为第三节点P。所述第三电容C3、第四电容C4、第五电容C5、第六电容C6、第七电容C7、第八电容C8、第九电容C9、第十电容C10电容值相同。The parallel switched capacitor C1 is composed of several branches connected in parallel, the first branch is the second capacitor C2; the second branch is composed of the third capacitor C3, the fourth switching transistor M4, and the fourth capacitor C4 in sequence Composed in series; the third branch is composed of the fifth capacitor C5, the third switching transistor M3, and the sixth capacitor C6 in series; the fourth branch is composed of the seventh capacitor C7, the second switching transistor M2, and the eighth capacitor C8 is sequentially connected in series; the fifth branch is composed of the ninth capacitor C9, the first switching transistor M1, and the tenth capacitor C10; Two ends, one end is the second node N, and the other end is the third node P. The third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, and the tenth capacitor C10 have the same capacitance value.
如图2所示，本发明开关并联电容C1中，第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第四开关晶体管M4均为N型晶体管。As shown in FIG. 2 , in the switched parallel capacitor C1 of the present invention, the first switch transistor M1 , the second switch transistor M2 , the third switch transistor M3 , and the fourth switch transistor M4 are all N-type transistors.
具体连接为：第九电容C9分别连接第二节点N和第一晶体管M1漏端，第十电容C10分别连第三接节点P和第一晶体管M1源端，第七电容C7分别连接第二节点N和第二晶体管M2漏端，第八电容C8分别连接第三节点P和第二晶体管M2源端，第五电容C5分别连接第二节点N和第三晶体管M3漏端，第六电容C6分别连接第三节点P和第三晶体管M3源端，第三电容C3分别连接第二节点N和第四晶体管M4漏端，第四电容C4分别连接第三节点P和第四晶体管M4源端，第二电容C2跨接与第二节点N和第三节点P之间，第一晶体管M1的栅极接第零数字控制信号B0，第二晶体管M2的栅极接第一数字控制信号B1，第三晶体管M3的栅极接第二数字控制信号B2，第四晶体管M4的栅极接第三数字控制信号B3。The specific connection is as follows: the ninth capacitor C9 is respectively connected to the second node N and the drain terminal of the first transistor M1, the tenth capacitor C10 is respectively connected to the third node P and the source terminal of the first transistor M1, and the seventh capacitor C7 is respectively connected to the second node N and the drain end of the second transistor M2, the eighth capacitor C8 is respectively connected to the third node P and the source end of the second transistor M2, the fifth capacitor C5 is respectively connected to the second node N and the drain end of the third transistor M3, and the sixth capacitor C6 is respectively Connect the third node P and the source terminal of the third transistor M3, the third capacitor C3 is respectively connected to the second node N and the drain terminal of the fourth transistor M4, and the fourth capacitor C4 is respectively connected to the third node P and the source terminal of the fourth transistor M4, and the third capacitor C3 is respectively connected to the third node P and the source terminal of the fourth transistor M4. The second capacitor C2 is connected between the second node N and the third node P, the gate of the first transistor M1 is connected to the zeroth digital control signal B0, the gate of the second transistor M2 is connected to the first digital control signal B1, and the gate of the third transistor M1 is connected to the first digital control signal B1. The gate of the transistor M3 is connected to the second digital control signal B2, and the gate of the fourth transistor M4 is connected to the third digital control signal B3.
通过计算滤波器输出电流和输入电流可得极零点跟踪二阶LC陷波滤波器电路极点为：By calculating the filter output current and input current, the pole-zero point tracking pole of the second-order LC notch filter circuit can be obtained as:
零点为：Zero is:
进而可得到零极点频率比值为：Then the zero-to-pole frequency ratio can be obtained as:
如上式所示，该滤波器极零点比值与开关并联电容C1不相关。通过控制数字信号B0-B3可改变并联开关电容C1电容值，使得极零点频率等比例移动，从而在宽带范围内提升镜像信号抑制比。As shown in the above equation, the filter pole-to-zero ratio is independent of the switched shunt capacitor C1. By controlling the digital signals B0-B3, the capacitance value of the parallel switch capacitor C1 can be changed, so that the frequency of the pole and zero points can be moved proportionally, thereby improving the image signal rejection ratio in the broadband range.
Claims (10)
- 一种极零点跟踪的二阶可调LC陷波滤波器，其特征在于，包括：输入端(Input)、滤波器第一串联电感(L1)、滤波器第二串联电感(L2)、滤波器第三并联电感(L3)、并联开关电容(C1)、输出端(Output)和节点(A)；其中，输入端(Input)、滤波器第一串联电感(L1)、滤波器第二串联电感(L2)、输出端(Output)顺序串联连接，并联开关电容(C1)的两端分别连接输入端(Input)和输出端(Output)；滤波器第一串联电感(L1)、滤波器第二串联电感(L2)的连接点为节点(A)，滤波器第三并联电感(L3)的一端连接该节点(A)，另一端接地。A second-order adjustable LC notch filter for pole-zero tracking, characterized in that it includes: an input terminal (Input), a first series inductance (L1) of a filter, a second series inductance (L2) of a filter, a filter The third parallel inductor (L3), the parallel switched capacitor (C1), the output terminal (Output) and the node (A); among them, the input terminal (Input), the first series inductor of the filter (L1), the second series inductor of the filter (L2), the output terminal (Output) are connected in series in sequence, and the two ends of the parallel switched capacitor (C1) are respectively connected to the input terminal (Input) and the output terminal (Output); the filter first series inductor (L1), the filter second The connection point of the series inductor (L2) is the node (A), one end of the third parallel inductor (L3) of the filter is connected to the node (A), and the other end is grounded.
- 根据权利要求1所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述的并联开关电容(C1)为可调并联开关电容，实现频率调谐。The pole-zero point tracking second-order adjustable LC notch filter according to claim 1, characterized in that the parallel switched capacitor (C1) is an adjustable parallel switched capacitor to realize frequency tuning.
- 根据权利要求1或2所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述并联开关电容(C1)由相互并联的几条支路组成，第一条支路为第二电容(C2)；第二条支路为由第三电容(C3)、第四开关晶体管(M4)、第四电容(C4)顺序串联组成；第三条支路为由第五电容(C5)、第三开关晶体管(M3)、第六电容(C6)顺序串联组成；第四条支路为由第七电容(C7)、第二开关晶体管(M2)、第八电容(C8)顺序串联组成；第五条支路为由第九电容(C9)、第一开关晶体管(M1)、第十电容(C10)顺序串联组成；所述的几条支路相互并联的两端即为并联开关电容(C1)的两端，其一端为第二节点(N)，另一端为第三节点(P)。The second-order adjustable LC notch filter according to claim 1 and 2, wherein the pole-zero point tracking is characterized in that, the parallel switched capacitor (C1) is made up of several branches connected in parallel, the first branch It is the second capacitor (C2); the second branch is composed of the third capacitor (C3), the fourth switching transistor (M4), and the fourth capacitor (C4) in series; the third branch is composed of the fifth capacitor (C5), the third switching transistor (M3), and the sixth capacitor (C6) are sequentially connected in series; the fourth branch is composed of the seventh capacitor (C7), the second switching transistor (M2), and the eighth capacitor (C8) The fifth branch is composed of the ninth capacitor (C9), the first switching transistor (M1), and the tenth capacitor (C10) in series; the two ends of the several branches connected in parallel are Two ends of the switched capacitor (C1) are connected in parallel, one end is the second node (N), and the other end is the third node (P).
- 根据权利要求3所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述第一开关晶体管(M1)、第二开关晶体管(M2)、第三开关晶体管(M3)、第四开关晶体管(M4)均为N型晶体管。The second-order adjustable LC notch filter according to claim 3, wherein the first switch transistor (M1), the second switch transistor (M2), the third switch transistor (M3) , and the fourth switching transistor (M4) are both N-type transistors.
- 根据权利要求3所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述第三电容(C3)、第四电容(C4)、第五电容(C5)、第六电容(C6)、第七电容(C7)、第八电容(C8)、第九电容(C9)、第十电容(C10)电容值相同。The second-order adjustable LC notch filter of pole-zero point tracking according to claim 3, is characterized in that, the third capacitor (C3), the fourth capacitor (C4), the fifth capacitor (C5), the sixth capacitor The capacitor (C6), the seventh capacitor (C7), the eighth capacitor (C8), the ninth capacitor (C9), and the tenth capacitor (C10) have the same capacitance value.
- 根据权利要求3所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述第二电容(C2)电容值根据陷波滤波器第一开关晶体管、第二开关晶体管、 第三开关晶体管、第四开关晶体管均关断状态下的零点频率ω z0和滤波器第一串联电感(L1)、滤波器第二串联电感(L2)，滤波器第三串联电感(L3)决定。 The second-order adjustable LC notch filter of pole-zero point tracking according to claim 3, is characterized in that, the capacitance value of the second capacitor (C2) is based on the first switch transistor, the second switch transistor, and the first switch transistor of the notch filter. The zero frequency ω z0 when the third switching transistor and the fourth switching transistor are both off is determined by the first series inductance of the filter (L1), the second series inductance of the filter (L2), and the third series inductance of the filter (L3) .
- 根据权利要求6所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述第二电容(C2)电容值：The second-order adjustable LC notch filter of pole-zero point tracking according to claim 6, is characterized in that, described second capacitor (C2) capacitance value:
- 根据权利要求3所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述第一晶体管(M1)的栅极接第零数字控制信号(B0)，第二晶体管(M2)的栅极接第一数字控制信号(B1)，第三晶体管(M3)的栅极接第二数字控制信号(B2)，第四晶体管(M4)的栅极接第三数字控制信号(B3)。The second-order adjustable LC notch filter of pole-zero point tracking according to claim 3 is characterized in that, the gate of said first transistor (M1) is connected to the zeroth digital control signal (B0), and the second transistor ( The gate of M2) is connected to the first digital control signal (B1), the gate of the third transistor (M3) is connected to the second digital control signal (B2), and the gate of the fourth transistor (M4) is connected to the third digital control signal ( B3).
- 根据权利要求8所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述第零数字控制信号(B0)、第一数字控制信号(B1)、第二数字控制信号(B2)、第三数字控制信号(B3)的改变，可改变并联开关电容(C1)电容值，使得极零点频率等比例移动，从而在宽带范围内提升镜像信号抑制比。The second-order adjustable LC notch filter of pole-zero point tracking according to claim 8, is characterized in that, the zeroth digital control signal (B0), the first digital control signal (B1), the second digital control signal (B2), the change of the third digital control signal (B3), can change the capacitance value of the parallel switched capacitor (C1), so that the frequency of the pole and zero point is moved proportionally, thereby improving the image signal rejection ratio in the broadband range.
- 根据权利要求1所述的极零点跟踪的二阶可调LC陷波滤波器，其特征在于，所述滤波器第一串联电感(L1)、滤波器第二串联电感(L2)、滤波器第三并联电感(L3)为平面电感器或圆柱形电感器。The second-order adjustable LC notch filter of pole-zero point tracking according to claim 1 is characterized in that, the first series inductance (L1) of the filter, the second series inductance (L2) of the filter, the second series inductance (L2) of the filter, The triple parallel inductor (L3) is a planar inductor or a cylindrical inductor.
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