CN114124029A - Second-order adjustable LC trap filter for pole zero tracking - Google Patents
Second-order adjustable LC trap filter for pole zero tracking Download PDFInfo
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- CN114124029A CN114124029A CN202111443405.9A CN202111443405A CN114124029A CN 114124029 A CN114124029 A CN 114124029A CN 202111443405 A CN202111443405 A CN 202111443405A CN 114124029 A CN114124029 A CN 114124029A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H2011/0488—Notch or bandstop filters
Abstract
The invention discloses a second-order tunable LC trap filter for pole zero tracking, which is characterized in that an Input end (Input), a first series inductor (L1) of the filter, a second series inductor (L2) of the filter and an Output end (Output) are sequentially connected in series, and two ends of a parallel switch capacitor (C1) are respectively connected with the Input end (Input) and the Output end (Output); the connection point of the first series inductor (L1) and the second series inductor (L2) of the filter is a node (A), one end of the third parallel inductor (L3) of the filter is connected with the node (A), and the other end of the third parallel inductor is grounded. The invention is based on a second-order LC filter network, realizes the pole zero tracking by utilizing the parallel switch capacitor, realizes the tracking inhibition of the image signal of the broadband transceiver, and effectively improves the image signal inhibition ratio in the broadband range.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a pole zero tracking second-order LC notch filter circuit, and belongs to the technical field of notch filter design.
Background
In a transceiver system, image interference refers to interference signals generated by signals during up and down mixing. The generation of the image signal not only has a great influence on the own transceiver system, but also affects other useful channels by being transmitted into space through the transmitter. The image rejection ratio is an indispensable indicator in the transceiver system due to the harm of the image signal. There are two common methods for achieving image rejection: the first transceiver system adopts an I/Q path structure; the second is to add a notch filter. The method adopting the I/Q path structure needs the I path and the Q path, thereby greatly increasing the area and the power consumption of the system. For the above reasons, the method using the notch filter is more attractive for improving the performance of the transceiver system.
The main challenge currently faced in notch filter design is how to effectively reject the image frequency signal in the broadband feedback range. In addition, for the pole zero tracking second-order LC notch filter circuit, the bandwidth and the gain of the useful signal are ensured to be unchanged when the broadband image signal is effectively suppressed.
Disclosure of Invention
The technical problem is as follows: the technical problem to be solved by the invention is as follows: the second-order tunable LC trap filter for pole zero tracking is provided, based on a second-order LC filter network, a pole zero tracking function is realized by connecting switch capacitors in parallel, and then tracking suppression of a transceiver image signal is realized; in a broadband range, the image signal rejection ratio of the transceiver is effectively improved.
The technical scheme is as follows: in order to solve the above technical problem, the present invention provides a second-order tunable LC notch filter for pole zero tracking, comprising: the input end, the first series inductor of the filter, the second series inductor of the filter, the third parallel inductor of the filter, the parallel switch capacitor, the output end and the node; the input end, the first series inductor of the filter, the second series inductor of the filter and the output end are sequentially connected in series, and two ends of the parallel switch capacitor are respectively connected with the input end and the output end; the connection point of the first series inductor of the filter and the second series inductor of the filter is a node, one end of the third parallel inductor of the filter is connected with the node, and the other end is grounded.
The parallel switch capacitor is an adjustable parallel switch capacitor, and frequency tuning is realized.
The parallel switch capacitor consists of a plurality of branches which are connected in parallel, and the first branch is a second capacitor; the second branch circuit is formed by sequentially connecting a third capacitor, a fourth switch transistor and a fourth capacitor in series; the third branch circuit is formed by sequentially connecting a fifth capacitor, a third switching transistor and a sixth capacitor in series; the fourth branch circuit is formed by sequentially connecting a seventh capacitor, a second switching transistor and an eighth capacitor in series; the fifth branch circuit is formed by sequentially connecting a ninth capacitor, a first switching transistor and a tenth capacitor in series; the two ends of the several branches which are connected in parallel are the two ends of the parallel switch capacitor, one end of the parallel switch capacitor is a second node, and the other end of the parallel switch capacitor is a third node.
The first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor are all N-type transistors.
And the capacitance values of the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor, the eighth capacitor, the ninth capacitor and the tenth capacitor are the same.
The capacitance value of the second capacitor (C2) is determined according to the zero point frequency omega of the notch filter in the off state of the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistorz0And a filter first series inductance (L1), a filter second series inductance (L2), and a filter third series inductance (L3). The values are specifically calculated as follows:
the grid electrode of the first transistor is connected with the zero digital control signal, the grid electrode of the second transistor is connected with the first digital control signal, the grid electrode of the third transistor is connected with the second digital control signal, and the grid electrode of the fourth transistor is connected with the third digital control signal.
The change of the zeroth digital control signal, the first digital control signal, the second digital control signal and the third digital control signal can change the capacitance value of the parallel switch capacitor, so that the pole zero frequency moves in equal proportion, and the rejection ratio of the image signal is improved in a broadband range.
The first series inductance of the filter, the second series inductance of the filter and the third parallel inductance of the filter are planar inductors or cylindrical inductors.
Has the advantages that: the pole zero tracking-based second-order LC trap filter circuit structure generates a zero at the frequency of a mirror image signal and simultaneously generates a pole at the frequency of a useful signal; filtering the image signal and simultaneously retaining a useful signal; zero-pole synchronous tracking is realized by switching a parallel capacitor, and suppression of broadband image signals is realized.
Drawings
FIG. 1 is a schematic diagram of a second-order tunable LC notch filter based on pole zero tracking according to the present invention.
FIG. 2 is a schematic diagram of a second-order tunable LC notch filter circuit switch tunable parallel capacitor based on pole zero tracking according to the present invention.
Detailed Description
The invention is further explained below with reference to the drawings.
As shown in fig. 1, a second-order tunable LC notch filter for pole zero tracking of the present invention includes: the filter comprises an Input end Input, a first filter series inductor L1, a second filter series inductor L2, a third filter parallel inductor L3, a parallel switch capacitor C1, an Output end Output and a node A; the Input end Input, the first filter series inductor L1, the second filter series inductor L2 and the Output end Output are sequentially connected in series, and two ends of the parallel switch capacitor C1 are respectively connected with the Input end Input and the Output end Output; the connection point of the filter first series inductor L1 and the filter second series inductor L2 is a node a, and one end of the filter third parallel inductor L3 is connected to the node a, and the other end is grounded. The filter first series inductance L1, the filter second series inductance L2 and the filter third parallel inductance L3 are planar inductors or cylindrical inductors.
As shown in fig. 2, the switched parallel capacitor C1 of the present invention is an adjustable parallel switched capacitor, which realizes frequency tuning.
The parallel switch capacitor C1 is composed of a plurality of branches connected in parallel, and the first branch is a second capacitor C2; the second branch circuit is formed by sequentially connecting a third capacitor C3, a fourth switching transistor M4 and a fourth capacitor C4 in series; the third branch is formed by sequentially connecting a fifth capacitor C5, a third switching transistor M3 and a sixth capacitor C6 in series; the fourth branch circuit is formed by sequentially connecting a seventh capacitor C7, a second switching transistor M2 and an eighth capacitor C8 in series; the fifth branch circuit is formed by sequentially connecting a ninth capacitor C9, a first switching transistor M1 and a tenth capacitor C10 in series; the two ends of the several branches connected in parallel are the two ends of the parallel switch capacitor C1, one end of the parallel switch capacitor C1 is the second node N, and the other end of the parallel switch capacitor C1 is the third node P. The capacitance values of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9 and the tenth capacitor C10 are the same.
As shown in fig. 2, in the switched parallel capacitor C1 of the present invention, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3 and the fourth switching transistor M4 are all N-type transistors.
The concrete connection is as follows: a ninth capacitor C9 is respectively connected with the drain terminals of the second node N and the first transistor M1, a tenth capacitor C10 is respectively connected with the source terminals of the third node P and the first transistor M1, a seventh capacitor C7 is respectively connected with the drain terminals of the second node N and the second transistor M2, an eighth capacitor C8 is respectively connected with the source terminals of the third node P and the second transistor M2, a fifth capacitor C5 is respectively connected with the drain terminals of the second node N and the third transistor M3, a sixth capacitor C6 is respectively connected with the source terminals of the third node P and the third transistor M3, a third capacitor C3 is respectively connected with the drain terminals of the second node N and the fourth transistor M4, a fourth capacitor C4 is respectively connected with the drain terminals of the third node P and the fourth transistor M4, a second capacitor C2 is connected between the second node N and the third node P, a gate electrode of the first transistor M1 is connected with a zero digital control signal B0, a gate electrode of the first transistor M2 is connected with the gate electrode of the second transistor M599, the gate of the fourth transistor M4 is connected to the third digital control signal B3.
The pole of the second-order LC trap filter circuit with pole zero tracking obtained by calculating the output current and the input current of the filter is as follows:
the zero point is:
further, the zero-pole frequency ratio can be obtained as follows:
as shown in the above equation, the filter pole-zero ratio is uncorrelated with the switched shunt capacitance C1. The capacitance value of the parallel switch capacitor C1 can be changed by controlling the digital signals B0-B3, so that the pole zero frequency moves in equal proportion, and the rejection ratio of the image signal is improved in a broadband range.
Claims (10)
1. A pole zero tracking second order tunable LC notch filter, comprising: the filter comprises an Input end (Input), a first filter series inductor (L1), a second filter series inductor (L2), a third filter parallel inductor (L3), a parallel switch capacitor (C1), an Output end (Output) and a node (A); the Input end (Input), the first filter series inductor (L1), the second filter series inductor (L2) and the Output end (Output) are sequentially connected in series, and two ends of the parallel switch capacitor (C1) are respectively connected with the Input end (Input) and the Output end (Output); the connection point of the first series inductor (L1) and the second series inductor (L2) of the filter is a node (A), one end of the third parallel inductor (L3) of the filter is connected with the node (A), and the other end of the third parallel inductor is grounded.
2. The pole-zero tracking second-order tunable LC notch filter of claim 1, wherein said shunt switch capacitor (C1) is an adjustable shunt switch capacitor to achieve frequency tuning.
3. A pole zero tracking second order tunable LC notch filter according to claim 1 or 2, characterized in that the shunt switch capacitance (C1) consists of several branches in parallel with each other, the first branch being a second capacitance (C2); the second branch circuit is formed by sequentially connecting a third capacitor (C3), a fourth switching transistor (M4) and a fourth capacitor (C4) in series; the third branch is formed by sequentially connecting a fifth capacitor (C5), a third switching transistor (M3) and a sixth capacitor (C6) in series; the fourth branch circuit is formed by sequentially connecting a seventh capacitor (C7), a second switching transistor (M2) and an eighth capacitor (C8) in series; the fifth branch circuit is formed by sequentially connecting a ninth capacitor (C9), a first switching transistor (M1) and a tenth capacitor (C10) in series; the two ends of the branches which are connected in parallel are the two ends of the parallel switch capacitor (C1), one end of the parallel switch capacitor is a second node (N), and the other end of the parallel switch capacitor is a third node (P).
4. The pole-zero tracking second-order tunable LC notch filter of claim 3, characterized in that the first (M1), second (M2), third (M3) and fourth (M4) switching transistors are all N-type transistors.
5. The pole-zero tracking second-order tunable LC notch filter of claim 3, wherein the third (C3), fourth (C4), fifth (C5), sixth (C6), seventh (C7), eighth (C8), ninth (C9), and tenth (C10) capacitors have the same capacitance value.
6. The pole-zero tracking second-order tunable LC notch filter of claim 3, wherein said second capacitor (C2) has a capacitance value according to the zero frequency ω in the off-state of the notch filter first, second, third and fourth switching transistorsz0And a filter first series inductance (L1), a filter second series inductance (L2), and a filter third series inductance (L3).
7. According to claimThe tunable second-order LC notch filter for pole-zero tracking of claim 6, wherein said second capacitor (C2) has a capacitance value of:
8. the pole-zero tracking second-order tunable LC notch filter of claim 3, wherein the gate of the first transistor (M1) is connected to the zero-th digital control signal (B0), the gate of the second transistor (M2) is connected to the first digital control signal (B1), the gate of the third transistor (M3) is connected to the second digital control signal (B2), and the gate of the fourth transistor (M4) is connected to the third digital control signal (B3).
9. The pole-zero tracked tunable LC notch filter of the preceding claim 8, wherein the change of the zeroth digital control signal (B0), the first digital control signal (B1), the second digital control signal (B2), and the third digital control signal (B3) changes the capacitance of the shunt switch capacitor (C1) such that the pole-zero frequency is shifted in equal proportion, thereby increasing the image rejection ratio in a wide band.
10. The pole-zero tracking second order tunable LC notch filter of claim 1, wherein the filter first series inductance (L1), filter second series inductance (L2), and filter third parallel inductance (L3) are planar inductors or cylindrical inductors.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111443405.9A CN114124029A (en) | 2021-11-30 | 2021-11-30 | Second-order adjustable LC trap filter for pole zero tracking |
| PCT/CN2022/136957 WO2023098918A1 (en) | 2021-11-30 | 2022-12-06 | Second-order adjustable lc notch filter for pole zero tracking |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111443405.9A CN114124029A (en) | 2021-11-30 | 2021-11-30 | Second-order adjustable LC trap filter for pole zero tracking |
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| CN114124029A true CN114124029A (en) | 2022-03-01 |
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| CN202111443405.9A Pending CN114124029A (en) | 2021-11-30 | 2021-11-30 | Second-order adjustable LC trap filter for pole zero tracking |
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| WO (1) | WO2023098918A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023098918A1 (en) * | 2021-11-30 | 2023-06-08 | 东南大学 | Second-order adjustable lc notch filter for pole zero tracking |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050040909A1 (en) * | 2003-08-20 | 2005-02-24 | Waight Matthew Glenn | Broadband integrated digitally tunable filters |
| US9143172B2 (en) * | 2009-06-03 | 2015-09-22 | Qualcomm Incorporated | Tunable matching circuits for power amplifiers |
| CN202034953U (en) * | 2010-11-26 | 2011-11-09 | 惠州Tcl王牌高频电子有限公司 | Electronic tuner having image rejection function |
| US8803615B2 (en) * | 2012-01-23 | 2014-08-12 | Qualcomm Incorporated | Impedance matching circuit with tunable notch filters for power amplifier |
| CN104038158A (en) * | 2014-06-05 | 2014-09-10 | 西安电子科技大学 | Low-noise amplifier structure |
| CN111490801A (en) * | 2019-01-29 | 2020-08-04 | 上海川土微电子有限公司 | Radio frequency receiver architecture with adjustable image rejection ratio |
| CN114124029A (en) * | 2021-11-30 | 2022-03-01 | 东南大学 | Second-order adjustable LC trap filter for pole zero tracking |
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- 2021-11-30 CN CN202111443405.9A patent/CN114124029A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023098918A1 (en) * | 2021-11-30 | 2023-06-08 | 东南大学 | Second-order adjustable lc notch filter for pole zero tracking |
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