CN113096573B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN113096573B CN113096573B CN202110294956.7A CN202110294956A CN113096573B CN 113096573 B CN113096573 B CN 113096573B CN 202110294956 A CN202110294956 A CN 202110294956A CN 113096573 B CN113096573 B CN 113096573B
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- metal layer
- signal line
- display panel
- driving transistor
- display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention discloses a display panel and a display device, and relates to the technical field of display, wherein the display panel comprises a display area and a non-display area at least partially surrounding the display area, the non-display area comprises a gate drive circuit, the gate drive circuit comprises a plurality of signal lines and a plurality of cascaded shift registers, the signal lines are electrically connected with the shift registers, the shift registers comprise drive transistors, and the drive transistors are positioned in a first area of the non-display area, which is close to the display area; the signal line comprises a first signal line and a second signal line which extend along a first direction, and the current of the first signal line is larger than that of the second signal line; the display panel comprises a substrate base plate, and the first signal line and the first area at least partially overlap in a direction perpendicular to the plane of the substrate base plate. The invention utilizes the heat generated by the first signal wire with large current to promote the semiconductor mobility of the driving transistor and improve the driving capability of the driving transistor.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
In the field of display technology, a display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith. The driving of the gate lines may be realized by an attached integrated driving circuit. In recent years, with the continuous improvement of the amorphous silicon thin film process, a gate line driving circuit can also be directly integrated On an Array substrate to form a Gate On Array (GOA) to drive a gate line. For example, the GOA formed by a plurality of cascaded shift registers may be used to provide switching state voltage signals to a plurality of rows of gate lines of the pixel array, so as to control the plurality of rows of gate lines to be sequentially opened, and provide data signals to corresponding rows of pixel units in the pixel array from the data lines, so as to form gray voltages required by gray scales of a display image, thereby displaying an image of each frame. The shift register is provided with the driving transistor, in the prior art, the driving capability of the driving transistor of the shift register is mainly limited by the capability of an exposure machine, the capability of the exposure machine limits the size of the driving transistor, the width-length ratio of the driving transistor cannot be improved if the size of the driving transistor is not changed, namely the driving capability of the driving transistor is limited, so that the driving capability of the driving transistor cannot be improved under the condition that the exposure machine is not modified.
Therefore, it is desirable to provide a display panel capable of improving the driving capability of the driving transistor.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display device, so as to improve the driving capability of the driving transistor in the shift register and improve the display performance.
In one aspect, the present invention provides a display panel, including a display region and a non-display region at least partially surrounding the display region, where the non-display region includes a gate driving circuit, the gate driving circuit includes a plurality of signal lines and a plurality of cascaded shift registers, the signal lines are electrically connected to the shift registers, the shift registers include driving transistors, and the driving transistors are located in a first region of the non-display region close to the display region;
the signal lines include a first signal line and a second signal line extending in a first direction, and a current of the first signal line is larger than a current of the second signal line;
the display panel comprises a substrate base plate, and the first signal line and the first area are at least partially overlapped in a direction perpendicular to the plane of the substrate base plate.
In another aspect, the invention further provides a display device including the display panel.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the display panel comprises a display area and a non-display area at least partially surrounding the display area, wherein the non-display area comprises a grid driving circuit, the grid driving circuit comprises a plurality of signal lines and a plurality of cascaded shift registers, each shift register comprises a driving transistor, the signal lines are electrically connected with the shift registers, and the driving transistors are positioned in a first area, close to the display area, of the non-display area; the signal line comprises a first signal line and a second signal line which extend along a first direction, and the current of the first signal line is larger than that of the second signal line; the display panel comprises a substrate, wherein in a direction perpendicular to the plane of the substrate, a first signal line and a first area are at least partially overlapped, the semiconductor mobility of a driving transistor is related to temperature, the higher the semiconductor mobility, the higher the current of the first signal line, and heat is generated in the current transmission process.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic plan view of a display panel according to the present invention;
fig. 2 is a circuit diagram of a gate driving circuit according to the present invention;
FIG. 3 is an enlarged view of a portion of the area M of FIG. 1;
FIG. 4 isbase:Sub>A cross-sectional view taken along line A-A' of FIG. 3;
FIG. 5 is a further enlarged fragmentary view of area M of FIG. 1;
FIG. 6 is a cross-sectional view taken along line B-B' of FIG. 5;
FIG. 7 is a further enlarged fragmentary view of area M of FIG. 1;
FIG. 8 is a cross-sectional view taken along line C-C' of FIG. 7;
FIG. 9 is a further enlarged fragmentary view of region M of FIG. 1;
FIG. 10 is a further enlarged fragmentary view of region M of FIG. 1;
FIG. 11 is a further enlarged fragmentary view of region M of FIG. 1;
FIG. 12 is a cross-sectional view taken along line D-D' of FIG. 11;
FIG. 13 is a further enlarged fragmentary view of region M of FIG. 1;
FIG. 14 is a cross-sectional view taken along line E-E' of FIG. 13;
FIG. 15 is a further enlarged fragmentary view of region M of FIG. 1;
FIG. 16 is a cross-sectional view taken along line F-F' of FIG. 15;
FIG. 17 is a further enlarged fragmentary view of region M of FIG. 1;
FIG. 18 is a further enlarged fragmentary view of region M of FIG. 1;
fig. 19 is a schematic plan view of a display device according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1 to 3, fig. 1 is a schematic plan view of a display panel according to the present invention, fig. 2 is a circuit diagram of a gate driving circuit according to the present invention, and fig. 3 is a partially enlarged view of a region M in fig. 1.
With reference to fig. 1 to 3, the present embodiment provides a display panel 100, which includes a display area AA and a non-display area BB at least partially surrounding the display area AA, where the non-display area BB includes a gate driving circuit GD, the gate driving circuit GD includes a plurality of signal lines 1 and a plurality of cascaded shift registers VSR, the signal lines 1 are electrically connected to the shift registers VSR, the shift registers VSR include driving transistors TFT, and the driving transistors TFT are located in a first area 3 of the non-display area BB, which is close to the display area AA;
the signal line 1 includes a first signal line 11 and a second signal line 12 extending in the first direction X, and a current of the first signal line 11 is larger than a current of the second signal line 12;
the display panel 100 includes a base substrate 10, and the first signal line 11 at least partially overlaps the first region 3 in a direction perpendicular to a plane of the base substrate 10.
The display panel of the present invention may be a liquid crystal display panel, and may also be an organic self-luminous display panel, where the type of the display panel is not specifically limited, and fig. 1 only shows a case where the non-display area BB surrounds all the display area AA, and certainly, the non-display area BB may also partially surround the display area AA, and at this time, the display panel is provided with an image pickup area, and this is not specifically limited.
The number of signal lines 1 is only schematically shown in fig. 1, but of course further signal lines 1 are included, which are not shown here. Fig. 1 also shows a pixel device having a plurality of gate lines G extending along the first direction X and arranged in the second direction Y, and a plurality of data lines D extending along the second direction Y and arranged in the first direction X, where the gate lines G and the data lines D intersect to define a pixel unit region, and the pixel unit region has pixels sp and transistors for driving the pixels sp, and of course, the number of the gate lines G and the data lines D is only schematically illustrated, and the output terminal of the shift register VSR is connected to the gate lines G to provide the gate lines G with switching-state voltage signals, and certainly, the driving chip provides the signal lines 1 with electric signals.
Referring to fig. 2, fig. 2 shows a circuit diagram of a gate driving circuit, the gate driving circuit GD in fig. 2 has an 11T1C structure, the gate driving circuit includes a scan signal input terminal including a forward scan signal input terminal FW and a reverse scan signal input terminal BW, a Reset signal control terminal is Reset, a Clock signal terminal Clock of the gate driving circuit is electrically connected to the Clock signal line, and a scan signal output terminal Gout is electrically connected to the gate line G. The gate driving circuit includes a first transistor T0, a second transistor T1, a third transistor T2, a fourth transistor T3, a fifth transistor T4, a sixth transistor T5, a seventh transistor T6, an eighth transistor T7, a ninth transistor T8, a tenth transistor T10, and an eleventh transistor T11, and the connection relationship between the transistors is not described herein again, where a source 7 of the fifth transistor T4 is electrically connected to the clock signal line, and a drain 8 of the fifth transistor T4 is electrically connected to the gate line G.
Of course, the gate driving circuit in fig. 2 is only one possible embodiment provided by the present invention, and it should be noted that the magnitude of the current of the signal line 1 in the present invention is obtained through a simulation test, for example, signal lines 1 such as VGL, BW, VGH, PVDD and the like through the simulation test are large current signal lines 1, and the clock signal line is a small current signal line 1. It is understood that the current of the first signal line 11 is larger than the current of the second signal line 12, the first signal line 11 may be a dc signal and the second signal line 12 may be a pulse signal, or the line width of the first signal line 11 is larger than the line width of the second signal line 12, or the impedance of the first signal line 11 is smaller than the impedance of the second signal line 12.
Fig. 3 is a layout view of the region M in fig. 1, and of course, only one driving transistor TFT is schematically shown in fig. 3, which may be the fifth transistor T4 in fig. 2, and other transistors are not shown in fig. 3. In fig. 3, the non-display area BB includes a first area 3 and a second area 4, the first area 3 is located on a side close to the display area AA, the second area 4 is located on a side of the first area 3 away from the display area AA, a second signal line 12 for a small current is disposed in the second area 4, and fig. 3 shows that the second signal line 12 is located in the first metal layer and the first signal line 11 is located on a side of the first metal layer close to the substrate. Here, the first region 3 and the second region 4 both extend along the second direction Y, in the first direction X, the first region 3 is closer to the display region AA, and the second region 4 is slightly farther from the display region AA, it should be noted that when the non-display region BB is laid on the board, the driving transistor is usually placed in the first region 3 or the second region 4 according to actual needs, and the signal line 1 may be laid in the first region or the second region 4, which is not limited herein.
Fig. 3 only schematically shows the number of the first signal lines 11 and the second signal lines 12, wherein in a direction perpendicular to the plane of the substrate 10, the first signal lines 11 overlap the first region 3, and two first signal lines 11 overlap the driving transistors TFT, or the first signal lines 11 do not overlap the driving transistors TFT but are closer to the driving transistors TFT, which is not specifically limited herein, and of course, only one first signal line 11 may be disposed to overlap the first region 3, or three or more first signal lines 11 may be disposed to overlap the first region 3.
Formula of heat generated according to current Q = I 2 Rt shows that the larger the current flowing through the signal, the more heat the signal line 1 generates, on the premise that the resistance of the signal line 1 and the current flowing time are not changed. The mobility of the transistor semiconductor 6 is related to the temperature of the semiconductor, the higher the temperature, the higher the mobility; the lower the temperature is, the lower the mobility is, and in the invention, the original high-current first signal line 11 in the gate driving circuit is overlapped with the first region 3, so that heat generated by the high-current first signal line 11 can be utilized to act on the semiconductor 6 of the driving transistor TFT, and the mobility of the semiconductor 6 is improved, so as to improve the driving capability of the gate line driving transistor, and optionally, the driving capability of the transistor connected with the gate line G is improved.
Compared with the prior art, the display panel has at least the following technical effects:
on one hand, the heat generated by the original high-current first signal wire 11 in the grid driving circuit is used as a heat source, a heating electrode does not need to be additionally arranged, and the manufacturing process is not increased;
on the other hand, the first signal line 11 with a large current in the gate driving circuit is overlapped with the first region 3, so that heat generated by the first signal line 11 can be utilized to act on the semiconductor 6 of the driving transistor TFT, and the mobility of the semiconductor 6 is improved, so as to improve the driving capability of the gate line driving transistor, and the driving capability of the transistor connected with the gate line G can be improved.
In some alternative embodiments, referring to fig. 4, 5, 6, 7 and 8, fig. 4 isbase:Sub>A sectional view taken alongbase:Sub>A-base:Sub>A ' in fig. 3, fig. 5 isbase:Sub>A further partial enlarged view taken along area M in fig. 1, fig. 6 isbase:Sub>A sectional view taken along B-B ' in fig. 5, fig. 7 isbase:Sub>A further partial enlarged view taken along area M in fig. 1, and fig. 8 isbase:Sub>A sectional view taken along C-C ' in fig. 7.
Referring to fig. 4, 6 and 8, the display panel includes an array substrate, where the array substrate includes a substrate 10, a first metal layer M1 located on a side of the substrate 10 close to a light-emitting surface of the display panel, an active layer AL located on a side of the first metal layer M1 far from the substrate 10, and a second metal layer M2 located on a side of the active layer AL far from the substrate 10;
the first metal layer M1 comprises the gate 5 of the drive transistor TFT, the active layer AL comprises the semiconductor 6 of the drive transistor TFT, and the second metal layer M2 comprises the source 7 of the drive transistor TFT and the drain 8 of the drive transistor TFT;
the display panel further comprises a third metal layer M3 and a fourth metal layer M4, the fourth metal layer M4 is positioned on one side of the first metal layer M1 close to the substrate base plate 10, and the third metal layer M3 is positioned on one side of the second metal layer M2 far away from the substrate base plate 10;
fig. 3 and 4 show that the first signal line 11 is located in the fourth metal layer M4, fig. 5 and 6 show that the first signal line 11 is located in the third metal layer M3, and fig. 7 and 8 show that the two first signal lines 11, one is located in the third metal layer M3 and the other is located in the fourth metal layer M4.
Insulating layers are disposed among the first metal layer M1, the second metal layer M2, and the third metal layer M3, and the insulating layers are not pattern-filled in the drawing.
In fig. 3 and 4, the first signal line 11 with large current is disposed below the driving transistor TFT and on the fourth metal layer M4, where the fourth metal layer M4 may be a metal layer used for making a light shielding layer in the display panel, in fig. 5 and 6, the first signal line 11 with large current is disposed on a side of the driving transistor TFT away from the substrate 10, the third metal layer M3 may be a metal layer used for disposing a touch signal line corresponding to a touch electrode in the display panel, in fig. 7 and 8, one of the first signal lines 11 with large current is disposed on a side of the driving transistor TFT away from the substrate 10, that is, on the third metal layer M3, and the other first signal line 11 with large current is disposed on a side of the driving transistor TFT close to the substrate 10, that is, on the fourth metal layer M4.
Certainly, the heat generated by the original high-current first signal wire 11 in the gate driving circuit is used as a heat source, a heating electrode does not need to be additionally arranged, and the manufacturing process is not increased; and overlap the first signal line 11 of the heavy current in the gate driver circuit with the first area 3, can utilize the heat that the first signal line 11 produces like this, act on semiconductor 6 of the driving transistor TFT, improve the mobility of the semiconductor 6, in order to promote the driving ability of the driving transistor of the grating.
In addition, in the embodiment, the first signal line 11 with a large current and the original metal film layer in the display panel are disposed on the same layer, so that the first signal line 11 and the original metal film layer in the display panel can be manufactured by the same process without increasing a process, which is beneficial to simplifying the process.
In some alternative embodiments, with continued reference to fig. 3 to 8, at least two first signal lines 11 overlap the drive transistors TFT in a direction perpendicular to the plane of the base substrate 10, wherein,
all the first signal lines 11 are located in the third metal layer M3, or all the first signal lines 11 are located in the fourth metal layer M4, or at least one of the first signal lines 11 is located in the third metal layer M3, and at least one of the first signal lines 11 is located in the fourth metal layer M4.
Referring to fig. 3 to 8, only two first signal lines 11 are shown overlapping the driving transistors TFT in a direction perpendicular to the plane of the base substrate 10; of course, the number of the first signal lines 11 overlapping the driving transistors TFT may be three or more, and is not particularly limited herein.
At least two first signal lines 11 are overlapped with the driving transistor TFT, so that heat can be supplied to the semiconductor 6 of the driving transistor TFT more quickly, and the driving capability of the driving transistor TFT is further improved; in addition, the plurality of first signal lines 11 supply heat to the semiconductor 6 of the driving transistor TFT as a heat source, and thus the amount of heat supplied is large, further improving the driving capability of the driving transistor TFT.
All the first signal lines 11 are shown in fig. 5 and 6 to be located in the third metal layer M3; all the first signal lines 11 are shown in fig. 3 and 4 to be located in the fourth metal layer M4; fig. 7 and 8 show that one of the first signal lines 11 is located in the third metal layer M3, and the other first signal line 11 is located in the fourth metal layer M4.
In fig. 3 and 4, the first signal line 11 for large current is disposed on the side of the driving transistor TFT close to the substrate 10, that is, on the fourth metal layer M4, where the fourth metal layer M4 may be a metal layer used for making a light shielding layer in the display panel, in fig. 5 and 6, the first signal line 11 for large current is disposed on the side of the driving transistor TFT far from the substrate 10, the third metal layer M3 may be a metal layer used for disposing a touch signal line corresponding to a touch electrode in the display panel, in fig. 7 and 8, one of the first signal lines 11 for large current is disposed on the side of the driving transistor TFT far from the substrate 10, that is, on the third metal layer M3, and the other first signal line 11 for large current is disposed on the side of the driving transistor TFT close to the substrate 10, that is, on the fourth metal layer M4.
In this embodiment, the first signal line 11 with a large current and the original metal film layer in the display panel are disposed on the same layer, and the first signal line 11 and the original metal film layer in the display panel can be manufactured by the same process without increasing a process, which is beneficial to simplifying the process.
In addition, referring to fig. 2, the clock signal line (second signal line 12) and the gate 5 of the driving transistor TFT form a capacitor, and in the structure shown in fig. 3, when the first signal line 11 with a large current is disposed on the side of the driving transistor TFT close to the substrate 10, that is, the first signal line 11 is disposed on the fourth metal layer M4, the capacitance value of the bootstrap capacitor becomes large, and the bootstrap becomes easy. Meanwhile, since this bootstrap capacitance becomes large, the coupling effect is reduced, and thus the leakage of the driving transistor TFT can be reduced.
In addition, since the first signal line 11 overlaps the driving transistor TFT, the space occupied by the first signal line 11 in the first direction X can be reduced, which is advantageous for implementing a narrow bezel.
In some alternative embodiments, referring to fig. 9, fig. 9 is a partial enlarged view of a region M in fig. 1, the driving transistor TFT includes at least two driving transistor subsections 15 connected in parallel, and the driving transistor subsections 15 are arranged along a second direction Y, and the first direction X intersects with the second direction Y.
Fig. 9 shows that the driving transistor TFT has only two driving transistor sub-sections 15 connected in parallel, but may have three or more driving transistor sub-sections 15, which is not particularly limited herein. Fig. 9 shows that two first signal lines 11 overlap with the driving transistor sub-section 15, and the first signal lines 11 are located on the side of the driving transistor sub-section 15 close to the substrate 10, so that heat can be uniformly supplied to the semiconductor 6 of the driving transistor TFT, the mobility of the semiconductor 6 is promoted, and the driving force of the driving transistor TFT is increased.
Of course, since the first signal line 11 overlaps the driving transistor TFT, the space occupied by the first signal line 11 in the first direction X can be reduced, which is beneficial to realizing a narrow frame.
In some alternative embodiments, with continued reference to fig. 9, a drive transistor sub-section 15 includes a semiconductor 61, a gate 51, a source 71, and a drain 81, with the gate 51, source 71, and drain 81 of adjacent drive transistor sub-sections 15 all connected in parallel.
As can be seen from fig. 9, the gate electrodes 51, the source electrodes 71 and the drain electrodes 81 of two adjacent driving transistor subsections 15 are connected in parallel, and the driving function of the driving transistor TFT is ensured.
In some alternative embodiments, with continued reference to fig. 9, the first signal lines 11 overlap the drive transistor subsections 15 in a direction perpendicular to the plane of the substrate base.
In fig. 9, the two first signal lines 11 respectively overlap the two driving transistor subsections 15, so that heating is more uniform, heat can be uniformly supplied to the semiconductor 61 of the driving transistor TFT, mobility of the semiconductor 61 is promoted, and driving force of the driving transistor TFT is improved.
In some alternative embodiments, referring to fig. 10, fig. 10 is a further partial enlarged view of a region M in fig. 1, and the first signal line 11 is located between adjacent driving transistor subsections 15 in fig. 10.
Referring to fig. 10, the driving transistor TFT is divided into two driving transistor subsections 15 connected in parallel in fig. 10, and the gate electrode 51, the source electrode 71 and the drain electrode 81 of the two adjacent driving transistor subsections 15 are all connected in parallel, but the driving transistor TFT may be divided into three or more driving transistor subsections 15 connected in parallel, and the first signal line 11 may be disposed between the driving transistor subsections 15, and the number of the driving transistor subsections 15 is not specifically limited.
The first signal line 11 is located on the side of the drive transistor sub-section 15 close to the base substrate 10 in fig. 10.
In this embodiment, the first signal line 11 is disposed between the driving transistor subsections 15, so that the first signal line 11 is used to provide heat to the semiconductor 61 of two adjacent driving transistor subsections 15, and the heating is more uniform, which is more beneficial to improve the driving force of the driving transistor TFT.
Meanwhile, since the first signal lines 11 are disposed between the driving transistor subsections 15, the space occupied by the first signal lines 11 in the first direction X can be reduced, which is advantageous for realizing a narrow bezel.
In some alternative embodiments, referring to fig. 11 and 12, fig. 11 is a further enlarged view of a portion of region M of fig. 1, and fig. 12 is a cross-sectional view taken along line D-D' of fig. 11.
The display panel comprises an array substrate, wherein the array substrate comprises a substrate 10, a first metal layer M1 positioned on one side of the substrate 10 close to the light-emitting surface of the display panel, an active layer AL positioned on one side of the first metal layer M1 far away from the substrate 10, and a second metal layer M2 positioned on one side of the active layer AL far away from the substrate 10;
the first metal layer M1 includes a gate electrode 51, the active layer AL includes a semiconductor 61, and the second metal layer M2 includes a source electrode 71 and a drain electrode 81;
the first signal line 11 is located on the first metal layer M1, the array substrate further includes a bridging metal 16, the bridging metal 16 is located on the second metal layer M2, and the bridging metal 16 is electrically connected to the gate 51 through a via.
In fig. 12, an insulating layer is provided between the first metal layer M1, the active layer AL, and the second metal layer M2, and the insulating layer is not pattern-filled in the drawing. In fig. 11, the driving transistor TFT is divided into two driving transistor subsections 15 connected in parallel, and the gate electrode 51, the source electrode 71 and the drain electrode 81 of the two adjacent driving transistor subsections 15 are all connected in parallel, but the driving transistor TFT may be divided into three or more driving transistor subsections 15 connected in parallel, and the first signal line 11 may be disposed between the driving transistor subsections 15, and the number of the driving transistor subsections 15 is not particularly limited.
In the present embodiment, the first signal line 11 is disposed on the first metal layer M1, and the gate 5 is also disposed on the first metal layer M1, so that the driving transistor subsections 15 are connected in parallel, so that a bridging metal 16 may be disposed on the second metal layer M2, and two ends of the bridging metal 16 are electrically connected to the driving transistor subsections 15 through vias, respectively, so that the driving transistor subsections 15 are connected in parallel; in this embodiment, the first signal line 11 is disposed on the first metal layer M1, and the array substrate does not need to dispose the first signal line 11 with more metal layers, so that the display panel can be thinned, and the manufacturing process is simplified.
Meanwhile, since the first signal lines 11 are disposed between the driving transistor subsections 15, the space occupied by the first signal lines 11 in the first direction X can be reduced, which is advantageous for realizing a narrow bezel.
In some alternative embodiments, referring to fig. 13, fig. 13 is a further partial enlarged view of a region M in fig. 1, and in fig. 13, the first signal line 11 and the driving transistor TFT have a space therebetween, which is greater than 0 and equal to or less than 15 μ M.
Fig. 13 only schematically shows the number of the first signal lines 11 and the second signal lines 12, wherein the first signal lines 11 overlap the first region 3 in a direction perpendicular to a plane where the light emitting surface of the display panel is located, and two first signal lines 11 do not overlap the driving transistors TFT, and the first signal lines 11 have a space from the driving transistors TFT, but only two or more first signal lines 11 may be provided to overlap the first region 3. Note that the driving transistor TFT in fig. 13 is not electrically connected to the first signal line 11 or the second signal line 12, but the first signal line 11 or the second signal line 12 may be electrically connected to other transistors in the gate driver circuit, which are not shown here. Of course, this embodiment is also applicable to the case where the driving transistor TFT is divided into a plurality of driving transistor sub-sections 15, as long as the pitch between the first signal line 11 and the driving transistor sub-sections 15 is greater than 0 and equal to or less than 15 μm.
When the first signal line 11 is not overlapped with the driving transistor TFT, it is required that the distance between the first signal line 11 and the driving transistor TFT is relatively short, and when the distance between the first signal line 11 and the driving transistor TFT is relatively long, the heat of the first signal line 11 cannot play a role in improving the mobility of the driving transistor TFT semiconductor 6, and it can be understood that the closer the distance between the first signal line 11 and the driving transistor TFT is, the more the heat of the first signal line 11 can improve the mobility of the driving transistor TFT semiconductor 6, thereby improving the driving force of the driving transistor TFT.
It can be understood that, the interval between the first signal line 11 and the driving transistor TFT is greater than 0 and less than or equal to 15 μ M, which can better improve the mobility of the driving transistor TFT semiconductor 6 and thus improve the driving force of the driving transistor TFT, it should be noted that, when the first signal line 11 and the gate 5 are both located in the first metal layer M1, the interval between the first signal line 11 and the driving transistor TFT cannot be equal to 0, and when the interval is equal to 0, the first signal line 11 and the gate 5 are connected in series, which affects signal transmission.
It should be noted that the driving transistor TFT in this embodiment may be divided into a plurality of driving transistor subsections (not shown in the figure) connected in parallel, and in this case, the first signal line 11 may be located on both sides of the driving transistor subsections or between the driving transistor subsections as long as the distance between the first signal line 11 and the driving transistor subsections is greater than 0 and less than or equal to 15 μm.
In some alternative embodiments, with continuing reference to fig. 13 and with further reference to fig. 14, 15 and 16, fig. 14 is a cross-sectional view taken along line E-E 'of fig. 13, fig. 15 is a further enlarged view of region M of fig. 1, and fig. 16 is a cross-sectional view taken along line F-F' of fig. 15.
The display panel further comprises a first metal layer M1 positioned on one side of the substrate base plate 10 close to the light-emitting surface of the display panel, an active layer AL positioned on one side of the first metal layer M1 far away from the substrate base plate 10, and a second metal layer M2 positioned on one side of the active layer AL far away from the substrate base plate 10;
the first metal layer M1 comprises a gate 5, the active layer AL comprises a semiconductor 6, and the second metal layer M2 comprises a source 7 and a drain 8;
the first signal line 11 is located in the first metal layer M1, or the first signal line 11 is located in the second metal layer M2.
Insulating layers are disposed between the first metal layer M1, the active layer AL, and the second metal layer M2, and the insulating layers are not pattern-filled in the drawing.
Fig. 13 and 14 show that the first signal line 11 is located on the first metal layer M1, and fig. 15 and 16 show that the first signal line 11 is located on the second metal layer M2, in this embodiment, the first signal line 11 is disposed on the first metal layer M1 or the second metal layer M2, and the array substrate does not need to be provided with more metal layers to dispose the first signal line 11, so that the display panel can be thinned, and the manufacturing process is simplified.
Of course, in the structures of fig. 13 to 16, the distance between the first signal line 11 and the driving transistor TFT is short, and the heat of the first signal line 11 can increase the mobility of the driving transistor TFT semiconductor 6, thereby increasing the driving force of the driving transistor TFT.
In some alternative embodiments, with continued reference to fig. 3-16, the potential transmitted by the first signal line 11 is a fixed potential.
It can be understood that, since the current of the first signal line 11 is larger than the current of the second signal line 12, when the mobility of the semiconductor 6 of the driving transistor TFT is improved by the heat of the first signal line 11, the potential transmitted by the first signal line 11 is a fixed potential, and at this time, the potential is stable, and the heat generated by the first signal line 11 is also stable, so that the mobility of the semiconductor 6 of the driving transistor TFT can be stably improved, thereby improving the driving force of the driving transistor TFT.
In some alternative embodiments, referring to fig. 17, fig. 17 is a further partial enlarged view of the region M in fig. 1, the shift register VSR further includes a first transistor TK, and the first signal line 11 is electrically connected to a source 712 of the first transistor.
It is understood that the first transistor TK in the present embodiment may be the tenth transistor T9 in fig. 2 or the eleventh transistor T10, the first signal line 11 is the fixed potential signal line VGL, and the second signal line 12 is the Reset signal line Reset or Goff, which is not particularly limited herein.
In fig. 17, the first signal line 11 is located in the first region 3, the first signal line 11 is located in the second metal layer, the first transistor TK includes a gate 512, a semiconductor 612, a source 712, and a drain 812, and the first signal line 11 is electrically connected to the source 712 of the first transistor TK, so that when the first transistor TK also needs to have improved driving capability, the first signal line 11 can be used to provide heat for the semiconductor 612 of the first transistor TK, which is more uniform in heating, and is more beneficial to improve the driving force of the first transistor TK.
In some alternative embodiments, the first transistor TK may include a plurality of first transistor subsections (not shown in the drawings) connected in parallel, the first signal line 11 is electrically connected to the sources of the first transistor subsections, and the first signal line 11 is disposed between adjacent first transistor subsections, so that the space occupied by the first signal line 11 in the first direction X can be reduced, which is advantageous for realizing a narrow bezel.
In some alternative embodiments, referring to FIG. 18, FIG. 18 is a further enlarged partial view of region M of FIG. 1. In fig. 18, the non-display area BB further includes a second area 4, the second area 4 is located on a side of the first area 3 away from the display area AA, and the second signal line 12 at least partially overlaps the second area 4 in a direction perpendicular to a plane of the substrate base.
It is understood that the shift register VSR further includes a first transistor TK, the first transistor TK in this embodiment may be a tenth transistor T9 or an eleventh transistor T10 in fig. 2, the first signal line 11 is a fixed potential signal line VGL, and the second signal line 12 is a Reset signal line Reset or Goff, which is not limited herein. The first transistor TK comprises a gate 512, a semiconductor 612, a source 712, and a drain 812, which provides heat to the semiconductor 612 of the first transistor TK using the first signal line 11, which provides more uniform heating and facilitates the enhancement of the first transistor TK.
In fig. 18, a first signal line 11 and a second signal line 12 are each provided in the first metal layer M1, the first signal line 11 is electrically connected to a source 712 of the first transistor TK through a via hole, and the second signal line 12 is electrically connected to a drain 812 of the first transistor TK through a via hole. It should be noted that, if the first signal line 11 and the second signal line 12 are both disposed in the second region 4, the line-changing via holes thereof are closer, and the electric field intensity thereof is larger. If the via holes connected in a top layer bridging manner are adopted, the current in the box is easily generated between the via holes, and electrochemical corrosion is caused. Since the first signal line 11 is located in the first region 3 and the second signal line 12 is located in the second region 4 in this embodiment, preferably, the first signal line 11 is located on a side of the first transistor TK away from the second signal line 12, a via hole through which the first signal line 11 is electrically connected to the source 712 of the first transistor TK and a via hole through which the second signal line 12 is electrically connected to the drain 812 of the first transistor TK are distant, so that the electric field intensity is low, and in-box current is not easily generated, preventing electrochemical corrosion.
Based on the same inventive concept, referring to fig. 19, fig. 19 is a schematic plan structure diagram of a display device provided by the present invention. The invention provides a display device which comprises the display panel of any one of the embodiments. The embodiment of fig. 19 only uses a mobile phone as an example to describe the display device 200, and it should be understood that the display device 200 provided in the embodiment of the present invention may be other display devices 200 having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device 200 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel 100 in each embodiment described above, and this embodiment is not described herein again.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
the display panel comprises a display area and a non-display area at least partially surrounding the display area, wherein the non-display area comprises a grid driving circuit, the grid driving circuit comprises a plurality of signal lines and a plurality of cascaded shift registers, each shift register comprises a driving transistor, the signal lines are electrically connected with the shift registers, and the driving transistors are positioned in a first area, close to the display area, of the non-display area; the signal lines include a first signal line and a second signal line extending in a first direction, and a current of the first signal line is larger than a current of the second signal line; the display panel comprises a substrate base plate, in the direction perpendicular to the plane of the substrate base plate, a first signal line is at least partially overlapped with a first area, the mobility of a semiconductor of a driving transistor is related to temperature, the higher the mobility of the semiconductor, the higher the current of the first signal line, and heat is generated in the current transmission process.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (13)
1. A display panel is characterized by comprising a display area and a non-display area at least partially surrounding the display area, wherein the non-display area comprises a grid driving circuit, the grid driving circuit comprises a plurality of signal lines and a plurality of cascaded shifting registers, the signal lines are electrically connected with the shifting registers, the shifting registers comprise driving transistors, and the driving transistors are positioned in a first area, close to the display area, of the non-display area;
the signal lines include a first signal line and a second signal line extending in a first direction, and a current of the first signal line is larger than a current of the second signal line;
the display panel comprises a substrate base plate, and the first signal line and the first area are at least partially overlapped in a direction perpendicular to the plane of the substrate base plate;
the display panel further comprises a first metal layer positioned on one side, close to the light-emitting surface of the display panel, of the substrate base plate, an active layer positioned on one side, far away from the substrate base plate, of the first metal layer, and a second metal layer positioned on one side, far away from the substrate base plate, of the active layer;
the first metal layer comprises a gate of the driving transistor, the active layer comprises a semiconductor of the driving transistor, and the second metal layer comprises a source of the driving transistor and a drain of the driving transistor;
the display panel further comprises an array substrate; the array substrate comprises a third metal layer and a fourth metal layer, the fourth metal layer is positioned on one side of the first metal layer close to the substrate, and the third metal layer is positioned on one side of the second metal layer far away from the substrate;
the first signal line is located on the third metal layer and/or the fourth metal layer.
2. The display panel according to claim 1, wherein at least two of the first signal lines overlap the driving transistor in a direction perpendicular to a plane in which the substrate base plate is located, wherein,
all the first signal lines are located in the third metal layer, or all the first signal lines are located in the fourth metal layer, or at least one of the first signal lines is located in the third metal layer, and at least one of the first signal lines is located in the fourth metal layer.
3. The display panel according to claim 1, wherein the driving transistor comprises at least two driving transistor subsections connected in parallel, and the driving transistor subsections are arranged in a second direction, the first direction crossing the second direction.
4. The display panel of claim 3, wherein the drive transistor subsections comprise semiconductors, gates, sources, and drains, and the gates, sources, and drains of adjacent drive transistor subsections are all connected in parallel.
5. The display panel according to claim 3, wherein the first signal line overlaps with the driving transistor sub-section in a direction perpendicular to a plane of the substrate base plate.
6. The display panel according to claim 4, wherein the first signal line is located between adjacent ones of the driving transistor subsections.
7. The display panel of claim 6, wherein the display panel further comprises a first metal layer on a side of a substrate adjacent to the light-emitting surface of the display panel, the active layer on a side of the first metal layer away from the substrate, and a second metal layer on a side of the active layer away from the substrate;
the first metal layer includes the gate, the active layer includes the semiconductor, and the second metal layer includes the source and the drain;
the first signal line is located on the first metal layer, the array substrate further comprises bridging metal, the bridging metal is located on the second metal layer, and the bridging metal is electrically connected with the grid electrode through a through hole.
8. The display panel according to claim 1, wherein the first signal line and the driving transistor have a space therebetween, and wherein the space is greater than 0 and equal to or less than 15 μm.
9. The display panel according to claim 8, wherein the display panel further comprises a first metal layer on a side of a substrate base plate close to the light-emitting surface of the display panel, the active layer on a side of the first metal layer away from the substrate base plate, and a second metal layer on a side of the active layer away from the substrate base plate;
the first metal layer includes the gate, the active layer includes the semiconductor, and the second metal layer includes the source and the drain;
the first signal line is located on the first metal layer, or the first signal line is located on the second metal layer.
10. The display panel according to claim 1, wherein a potential transmitted by the first signal line is a fixed potential.
11. The display panel according to claim 1, wherein the shift register further comprises a first transistor, and wherein the first signal line is electrically connected to a source of the first transistor.
12. The display panel according to claim 1, wherein the non-display region further comprises a second region located on a side of the first region away from the display region, and wherein the second signal line at least partially overlaps the second region in a direction perpendicular to a plane of the substrate base.
13. A display device comprising the display panel according to any one of claims 1 to 12.
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| CN115206997A (en) * | 2022-07-01 | 2022-10-18 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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