CN116799002B - Display panel and display device - Google Patents
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Abstract
The invention discloses a display panel and a display device, wherein the display panel is provided with a display area and a non-display area surrounding the display area; the display area comprises a plurality of display sub-pixels, the display sub-pixels comprise a first transistor and a first light-emitting layer which are electrically connected, the non-display area comprises a plurality of static electricity protection circuit units, and each static electricity protection circuit unit comprises at least one second transistor; the first transistor comprises a first active layer, the second transistor comprises a second active layer, and the mobility of the second active layer is larger than that of the first active layer, so that the size of the second transistor is reduced to realize miniaturization, the occupied space of the electrostatic protection circuit unit is reduced, and the frame is narrowed.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
At present, in order to realize a display function, a plurality of signal lines, such as grid lines, data lines and the like, are distributed on a display panel, and in order to increase the transmission capacity of the signal lines and avoid the influence of static charges on signal transmission, a static protection circuit for releasing the static charges on the signal lines is generally arranged in a frame area of the display panel; however, the arrangement of the electrostatic protection circuit occupies a considerable portion of the display panel, and the frame specification compression refinement conflicts with the space occupied by the electrostatic protection circuit, so that a narrow frame cannot be obtained.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which can solve the technical problem that the frame specification compression refinement in the existing display panel and display device conflicts with the space occupied by an electrostatic protection circuit.
The invention provides a display panel, which is provided with a display area and a non-display area surrounding the display area; the display area comprises a plurality of display sub-pixels, the display sub-pixels comprise a first transistor and a first light-emitting layer which are electrically connected, the non-display area comprises a plurality of static electricity protection circuit units, and each static electricity protection circuit unit comprises at least one second transistor;
wherein the first transistor includes a first active layer, and the second transistor includes a second active layer having a mobility greater than that of the first active layer.
According to the display panel provided by the invention, the non-display area comprises a virtual area which is arranged close to the display area, the virtual area comprises a plurality of virtual sub-pixels, and the static electricity protection circuit unit is positioned at one side of the virtual sub-pixels away from the display area; the virtual sub-pixel comprises a third transistor and a second light emitting layer, and the third transistor is not connected with the second light emitting layer.
According to the display panel provided by the invention, the non-display area comprises a virtual area arranged close to the display area, the virtual area comprises a plurality of virtual sub-pixels, and the electrostatic protection circuit unit is arranged in the virtual sub-pixels; the virtual sub-pixel comprises the second transistor and a second light-emitting layer positioned on one side of the static electricity protection circuit unit, and the second light-emitting layer is not connected with the second transistor.
According to the display panel provided by the invention, the electrostatic protection circuit unit comprises a first module, wherein the first module comprises at least two second transistors connected in series;
the first module has a first end electrically connected to a first common voltage line and a second end electrically connected to a signal line, the first common voltage line being a high-level common voltage line.
According to the display panel provided by the invention, the first module comprises a first sub-transistor and a second sub-transistor which are connected in series;
the first grid electrode of the first sub-transistor, the second grid electrode of the second sub-transistor and the second source electrode of the second sub-transistor are connected with the signal line, the first source electrode of the first sub-transistor is connected with the second drain electrode of the second sub-transistor, and the first drain electrode of the first sub-transistor is connected with the first common voltage line.
According to the display panel provided by the invention, the electrostatic protection circuit unit further comprises a second module connected with the first module, and the second module comprises at least two second transistors connected in series;
the second module has a third terminal connected to the first terminal and the signal line and a fourth terminal electrically connected to a second common voltage line, which is a low-level common voltage line.
According to the display panel provided by the invention, the second module comprises a third sub-transistor and a fourth sub-transistor which are connected in series;
the third gate of the third sub-transistor, the fourth gate of the fourth sub-transistor, and the fourth source of the fourth sub-transistor are connected to the second common voltage line, and the third source of the third sub-transistor is connected to the second source of the second sub-transistor.
According to the display panel provided by the invention, the first common voltage line and the second common voltage line are transversely arranged, and the first sub-transistor, the second sub-transistor, the third sub-transistor and the fourth sub-transistor are positioned between the first common voltage line and the second common voltage line and are sequentially arranged along the direction close to the second common voltage line.
According to the display panel provided by the invention, for the plurality of second transistors in the electrostatic protection circuit unit, the mobility of the second active layer of the second transistor close to the second end is greater than or equal to the mobility of the second active layer of the second transistor far from the second end.
According to the display panel provided by the invention, the mobility of the second transistor is greater than 100.
The invention provides a display device which comprises the display panel.
The beneficial effects are that: in the display panel and the display device provided by the embodiment of the invention, the display area comprises a plurality of display sub-pixels, the display sub-pixels comprise a first transistor and a first light-emitting layer which are electrically connected, the non-display area comprises a plurality of static protection circuit units, and each static protection circuit unit comprises at least one second transistor; the mobility of the second active layer of the second transistor is larger than that of the first active layer of the first transistor, so that the size of the second transistor is reduced to realize miniaturization, and the occupied space of the static electricity protection circuit unit is reduced, thereby being beneficial to narrowing the frame.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view taken along line A-A of FIG. 1;
FIG. 3 is a front-to-back comparison of the first transistor miniaturization;
FIG. 4 is a schematic plan view of a display panel of the prior art and a display panel of FIG. 1;
FIG. 5 is a schematic plan view of a display panel according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view taken along line B-B of FIG. 5;
FIG. 7 is a schematic plan view of a portion of a display panel of the prior art and the display panel of FIG. 5;
fig. 8 is a schematic circuit diagram of an electrostatic protection circuit unit according to an embodiment of the present invention;
fig. 9 is a schematic layout structure of a display panel according to an embodiment of the present invention.
Reference numerals illustrate:
AA. A display area; NA, non-display area; NA1, virtual area; NA2, electrostatic protection area;
t1, a first sub-transistor; t2, a second sub-transistor; t3, third sub-transistor; t4, a fourth sub-transistor;
1. displaying the sub-pixels; 11. a first transistor; 111. a first active layer; 12. a first light emitting layer; 13. an organic planarization layer; 14. a first anode; 15. a pixel definition layer; 16. an inorganic layer; 2. an electrostatic protection circuit unit; 21. a second transistor; 211. a second active layer; 3. virtual subpixels; 31. a third transistor; 32. a second light emitting layer; 33. a second anode; 22. a first module; 23. a second module; 4. a substrate; 5. a light shielding layer; 6. a buffer layer; 7. connecting wires; 8. a signal line; 81. a data line; 91. a first common voltage line; 92. and a second common voltage line.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In the description of the present invention, it should be understood that the terms "length," "width," "thickness," "upper," "lower," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween.
The embodiment of the invention provides a display panel and a display device, wherein the display panel comprises a display area and a non-display area surrounding the display area; the display area comprises a plurality of display sub-pixels, the display sub-pixels comprise a first transistor and a first light-emitting layer which are electrically connected, the non-display area comprises a plurality of static electricity protection circuit units, and each static electricity protection circuit unit comprises at least one second transistor; the mobility of the second active layer of the second transistor is larger than that of the first active layer of the first transistor, so that the size of the second transistor is reduced to realize miniaturization, and the occupied space of the static electricity protection circuit unit is reduced, thereby being beneficial to narrowing the frame.
The following examples will be described in detail, and it should be noted that the order of description of the following examples is not to be construed as a limitation on the preferred order of the examples.
Referring to fig. 1 and 2, fig. 1 is a schematic plan view of a display panel according to an embodiment of the invention, and fig. 2 is a schematic sectional view along A-A in fig. 1. The embodiment of the invention provides a display panel, which is provided with a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a plurality of display sub-pixels 1, the display sub-pixels 1 include a first transistor 11 and a first light emitting layer 12 electrically connected, the non-display area NA includes a plurality of electrostatic protection circuit units 2, and each of the electrostatic protection circuit units 2 includes at least one second transistor 21; wherein the first transistor 11 includes a first active layer 111, the second transistor 21 includes a second active layer 211, and the mobility of the second active layer 211 is greater than the mobility of the first active layer 111.
It should be noted that, the switching characteristic of the transistor with high mobility is significantly better than the switching characteristic with low mobility, that is, the switching characteristic of the second transistor 21 is significantly better than the switching characteristic of the first transistor 11, so that the second transistor 21 can be made smaller and thinner, thereby being beneficial to reducing the occupied area or volume of the second transistor 21 in the non-display area NA, and further being beneficial to reducing the occupied area or volume of the electrostatic protection circuit unit 2 formed by the second transistor 21 in the non-display area NA, and being beneficial to realizing a narrow frame. For example, referring to fig. 3, fig. 3 is a front-to-back comparison diagram of the miniaturization of the first transistor, wherein (a) in fig. 3 shows the second transistor 21 using a low mobility material in the prior art, and (b) in fig. 3 shows the second transistor 21 using a high mobility material in the embodiment of the present invention, and it is obvious that the size of the second transistor 21 in (b) is significantly smaller than the size of the second transistor 21 in (a). Where G in fig. 3 represents the gate of the second transistor 21, S represents the source of the second transistor 21, and D represents the drain of the second transistor 21.
In the embodiment of the present invention, the ratio between the mobility of the second active layer 211 and the mobility of the first active layer 111 is greater than 2. Specifically, the mobility of the second active layer 211 is greater than 100, and setting the mobility of the second transistor 21 within this range is advantageous in ensuring that the electrostatic protection circuit unit 2 has a sufficiently small footprint or volume.
Alternatively, the material of the second transistor 21 includes a high mobility material including, but not limited to, metal oxide, low temperature polysilicon, and the like.
Alternatively, the material of the first active layer 111 in the first transistor 11 may include amorphous silicon. When the display panel is a liquid crystal display panel, the first transistor 11 in the display area AA is generally used for turning on the corresponding pixel, and the requirement on the magnitude of the turning-on current of the first transistor 11 is low, so that the first transistor 11 can be made of an amorphous silicon material with low mobility, and in the manufacturing process, the amorphous silicon material in the display area AA is not required to be converted into a polysilicon material through crystallization treatment, so that the crosstalk phenomenon caused by large leakage current can be avoided, and adverse effects on the display effect can be avoided.
The display panel may be one of an organic light emitting display panel and a liquid crystal display panel, and the embodiment of the invention is described by taking the display panel as an organic light emitting display panel as an example. Since the organic light emitting display panel is located in the first light emitting layer 12 of the display area AA and is generally prepared by using an inkjet printing process, in consideration of the requirement of uniformity of the inkjet printing atmosphere, in order to ensure/satisfy the uniformity of the film formation and the in-plane uniformity of the rows/columns of sub-pixels at the edge of the display area AA, to reduce the risk of Mura, it is generally required to provide a bank layer of rows/columns at the position of the non-display area NA near the display area AA, and in actual printing, ink is sprayed into the openings on the bank to form the virtual sub-pixels 3, where the virtual sub-pixels 3 do not perform pixel display.
Specifically, the non-display area NA includes a virtual area NA1 disposed near the display area AA, the virtual area NA1 includes a plurality of virtual sub-pixels 3, and the electrostatic protection circuit unit 2 is located at a side of the virtual sub-pixels 3 away from the display area AA; wherein the dummy sub-pixel 3 includes a third transistor 31 and a second light emitting layer 32, and the third transistor 31 is not connected to the second light emitting layer 32. In general, the virtual subpixel 3 has a structure substantially similar to that of the display subpixel 1, and does not participate in display. Specific ways in which the virtual sub-pixel 3 does not participate in the display include, but are not limited to, the following ways: the dummy area NA1 is not provided with an anode, or the anode is not electrically connected to the driving transistor below, or the driving transistor is not normally connected to the signal line 8, etc., which is not limited in the embodiment of the present invention.
It should be noted that, in order to clearly illustrate the technical solution provided by the embodiments of the present invention, an area where the electrostatic protection circuit unit 2 is located in the non-display area NA is referred to as an electrostatic protection area NA2, and in the prior art, the electrostatic protection area NA2 is disposed at a side of the virtual area NA1 away from the display area AA, and a frame of the display panel includes the virtual area NA1 and the electrostatic protection area NA2. In the embodiment of the invention, the size of the electrostatic protection area NA2 is reduced due to the reduction of the occupied area or volume of the electrostatic protection unit in the non-display area NA, so that the frame of the display panel is narrowed. Referring to fig. 4, fig. 4 is a schematic plan view of a display panel in the prior art compared to a partial plan view of the display panel in fig. 1, wherein (a) in fig. 4 shows a partial plan view of the display panel in the prior art, and (b) in fig. 4 shows a partial plan view of the display panel in an embodiment of the present invention, and it is obvious that a frame of the display panel in (b) is narrowed by a distance d1 compared to a frame of the display panel in (a).
Further, as shown in fig. 5-6, fig. 5 is another schematic plan view of the display panel according to the embodiment of the present invention, and fig. 6 is a schematic sectional view along B-B in fig. 5. The non-display area NA includes a virtual area NA1 disposed near the display area AA, the virtual area NA1 includes a plurality of virtual sub-pixels 3, and the electrostatic protection circuit unit 2 is built in the virtual sub-pixels 3. The reason for this is that the electrostatic protection circuit unit 2 may be incorporated into the original area of the virtual area NA1 after the shrinking, so that the virtual area NA1 has not only the effect of reducing the risk of the difference of Mura of the original virtual sub-pixel 3, but also the effect of electrostatic protection, that is, the electrostatic protection area NA2 may be omitted, or the virtual area NA1 may serve as the electrostatic protection area NA2, so that the frame of the display panel is further narrowed, which is beneficial to realizing a full screen. In short, the effect on process uniformity is minimized while increasing the functionality of the virtual area NA 1. Referring to fig. 7, fig. 7 is a schematic partial plan view of the display panel in the prior art compared to the display panel in fig. 5, wherein (a) in fig. 7 shows a schematic partial plan view of the display panel in the prior art, and (b) in fig. 7 shows a schematic partial plan view of the display panel in the embodiment of the present invention, and it is obvious that the frame of the display panel in (b) has a narrower distance d2 compared to the frame of the display panel in (a), wherein d2 is greater than d1.
In the first case, the second transistor 21 of the electrostatic protection circuit unit 2 is located at a side of the third transistor 31 of the dummy subpixel 3 away from the display area AA. In the second case, as shown in fig. 6, the second transistor 21 of the electrostatic protection circuit unit 2 serves as the third transistor 31 of the virtual subpixel 3, specifically, the virtual subpixel 3 includes the second transistor 21 and a second light emitting layer 32 located on one side of the electrostatic protection circuit unit 2, and the second light emitting layer 32 is not connected to the second transistor 21, which is beneficial to reducing the number of transistors disposed in the virtual area NA1, and further narrowing the frame. The second case will be described with emphasis.
Specifically, as shown in fig. 6, the first transistor 11 includes the first active layer 111, a first gate electrode, a gate insulating layer, a first source electrode, and a first drain electrode, and the second transistor 21 includes the second active layer 211, a second gate electrode, a gate insulating layer, a second source electrode, and a second drain electrode. Each functional film layer of the first transistor 11 is arranged in the same layer as the corresponding functional film layer of the second transistor 21. The first transistor 11 may be a bottom gate type thin film transistor or a top gate type thin film transistor, and the embodiment of the present invention will be described by taking the first transistor 11 and the second transistor 21 as top gate type thin film transistors as an example.
As will be described in detail below in terms of the film structure of the display panel, the display panel further includes a substrate, a light shielding layer 5, a buffer layer 6, an interlayer dielectric layer, an organic planarization layer 13, a connection trace 7, a first anode 14, a second anode 33, and a pixel defining layer 15.
Specifically, the light shielding layer 5 is located on the substrate and is located in the display area AA, the buffer layer 6 covers the light shielding layer 5, and the interlayer dielectric layer covers the first gate electrode, the second gate electrode, the gate insulating layer, the first active layer 111, the second active layer 211 and the buffer layer 6; the inorganic layer 16 covers the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode; the first connection trace 7 and the second connection trace 7 are located on the inorganic layer 16, the connection trace 7 and the first anode 14 are located in the display area AA, and the second anode 33 is located in the virtual area NA1; the organic planarization layer 13 covers the connection trace 7; the pixel defining layer 15, the first anode 14 and the second anode 33 are located on the organic planarization layer 13, the first anode 14 is electrically connected to the connection trace 7 through a via penetrating the organic planarization layer 13, and the connection trace 7 is electrically connected to the first drain through a via penetrating the inorganic layer 16; the organic planarization layer 13 and the inorganic layer 16 are not provided with a via hole in the virtual area NA1 such that the second anode 33 is not connected to the second drain electrode; the pixel defining layer 15 extends from the display area AA to the virtual area NA1, the first light emitting layer 12 is located in an opening of the display area AA where the pixel defining layer 15 is formed, and the second light emitting layer 32 is located in an opening of the virtual area NA1 where the pixel defining layer 15 is formed. Since this is a prior art, the details are not described here.
It will be appreciated that the electrostatic protection unit is formed by a base film layer of the thin film transistor array layer, and the thickness of the organic planarization layer 13 is relatively large, so that only the lower pattern and the topography of the display panel are affected, and the lower metal pattern has relatively small influence on the topography, so that the design of the film patterns such as the pixel definition layer 15 and the second anode 33 on the upper portion thereof is unchanged and still keeps consistent with the display area AA, thereby ensuring the uniformity of inkjet printing and exerting the function of the existing virtual area NA 1.
Further, referring to fig. 8, fig. 8 is a schematic circuit diagram of the electrostatic protection circuit unit according to an embodiment of the present invention. In the embodiment of the present invention, the electrostatic protection circuit unit 2 includes a first module 22, and the first module 22 includes at least two second transistors 21 connected in series; the first module 22 has a first terminal electrically connected to the first common voltage line 91 and a second terminal electrically connected to the signal line 8, and the first common voltage line 91 is a high-level common voltage line VGH-ESD. Specifically, the electrostatic protection circuit unit 2 is configured to discharge electrostatic charges on the signal line 8, and the signal line 8 may include traces such as a data line 81 and a scan line.
Specifically, the first module 22 includes a first sub-transistor T1 and a second sub-transistor T2 connected in series; the first gate of the first sub-transistor T1, the second gate of the second sub-transistor T2, and the second source of the second sub-transistor T2 are connected to the signal line 8, the first source of the first sub-transistor T1 is connected to the second drain of the second sub-transistor T2, and the first drain of the first sub-transistor T1 is connected to the first common voltage line 91.
It can be appreciated that, taking the first sub-transistor T1 and the second sub-transistor T2 as N-type thin film transistors as an example, when a large current passes through the signal line 8 to accumulate more static charges, when the voltage of the signal line 8 increases to be greater than the high-level common voltage line, the first gate of the first sub-transistor T1 and the second gate of the second sub-transistor T2 are turned on, the static charges accumulated on the signal line 8 are released to the high-level common voltage line, so that the static charges accumulated on the signal line 8 are rapidly released, and the problem that the display panel cannot display normally due to static breakdown caused by excessive local static charge accumulation is avoided.
Further, in the embodiment of the present invention, the electrostatic protection circuit unit 2 further includes a second module 23 connected to the first module 22, and the second module 23 includes at least two second transistors 21 connected in series; the second module 23 has a third terminal connected to the first terminal and the signal line 8 and a fourth terminal electrically connected to a second common voltage line 92, and the second common voltage line 92 is a low-level common voltage line VGL-ESD.
Specifically, the second module 23 includes a third sub-transistor T3 and a fourth sub-transistor T4 connected in series; the third gate of the third sub-transistor T3, the fourth gate of the fourth sub-transistor T4, and the fourth source of the fourth sub-transistor T4 are connected to the second common voltage line 92, and the third source of the third sub-transistor T3 is connected to the second source of the second sub-transistor T2.
It should be noted that the types of the third sub-transistor T3 and the fourth sub-transistor T4 may be the same as the types of the first sub-transistor T1 and the second sub-transistor T2, i.e., P-type transistors or N-type transistors. The number of the second transistors 21 in the first module 22 is not limited to 2, and the number of the second transistors 21 in the second module 23 is not limited to 2.
In one embodiment, the second active layers 211 of all the second transistors 21 in the electrostatic protection unit are made of a high mobility material; in another embodiment, the second active layer 211 of one or more groups of the second transistors 21, which are closer to the protected signal object, may be selected to use a high mobility material, while the second active layers 211 of the other second transistors 21, which are farther from the protected signal object, may use a relatively lower mobility material or a conventional mobility material. It should be noted that the protected signal is a signal on the signal line 8, a connection between the signal line 8 and the electrostatic protection unit is a signal input end, and the above description about the distance refers to a distance between the transistor and the signal input end.
Specifically, for the plurality of the second transistors 21 in the electrostatic protection circuit unit 2, the mobility of the second active layer 211 of the second transistor 21 near the second end is greater than or equal to the mobility of the second active layer 211 of the second transistor 21 far from the second end, so that the electrostatic protection circuit unit 2 can not only play a role in protecting a large current, but also reduce the influence of leakage on a normal display signal during normal operation.
Optionally, in the actual manufacturing process, a patterning process or a selective area Laser technology may be used, for example, a novel semiconductor material is used, or crystallization of the selective area Laser on a substrate such as an LTPS material is enhanced, so as to realize that the second transistor 21 at the near signal end is a high mobility device, and the second transistor 21 at the far signal end is a Hybrid structure of a large-size anti-leakage device with conventional mobility, thereby improving the characteristics.
Specifically, referring to fig. 9, fig. 9 is a schematic layout structure of a display panel according to an embodiment of the invention. The first common voltage line 91 and the second common voltage line 92 are arranged laterally, and the first sub-transistor T1, the second sub-transistor T2, the third sub-transistor T3 and the fourth sub-transistor T4 are located between the first common voltage line 91 and the second common voltage line 92 and are arranged sequentially along a direction approaching the second common voltage line 92, respectively. The electrostatic protection circuit unit 2 is electrically connected to the data line 81, specifically, the second source of the second sub-transistor T2 and the third drain of the third sub-transistor T3 are electrically connected to the data line 81, and the connection position is the signal input end of the electrostatic protection circuit unit 2.
Referring to the above description, how the lyout structure of the electrostatic protection circuit unit 2 is arranged only affects the lower tft array layer and the design, and does not affect the pattern of the pixel definition layer 15 and the second anode 33, etc. at the upper portion thereof, so that the lyout structure of the electrostatic protection circuit unit 2 can be rearranged according to the actual situation to complete the lyout space fusion.
Correspondingly, the embodiment of the invention also provides a display device. The display device includes the organic light emitting display panel described above. The display device provided in the embodiment of the invention may be at least one of a smart phone (smart phone), a tablet computer (tablet personal computer), a mobile phone (mobile phone), a video phone, an electronic book reader (e-book reader), a laptop (laptop PC), a netbook computer (netbook), a workstation (workstation), a server, a personal digital assistant (personal digital assistant), a portable media player (portable multimedia player), an MP3 player, a mobile medical machine, a camera, a game machine, a digital camera, a car navigator, an electronic billboard, an automatic teller machine, a smart bracelet, a smart watch, a Virtual Reality (VR) device, or a mobile device (web device). The above embodiments have been described in detail for the display panel, and therefore, in the embodiments of the present invention, the display panel is not described in detail.
The beneficial effects are that: in the display panel and the display device provided by the embodiment of the invention, the display area comprises a plurality of display sub-pixels, the display sub-pixels comprise a first transistor and a first light-emitting layer which are electrically connected, the non-display area comprises a plurality of static protection circuit units, and each static protection circuit unit comprises at least one second transistor; the mobility of the second active layer of the second transistor is larger than that of the first active layer of the first transistor, so that the size of the second transistor is reduced to realize miniaturization, and the occupied space of the static electricity protection circuit unit is reduced, thereby being beneficial to narrowing the frame.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The display panel and the display device provided by the embodiments of the present invention are described in detail, and specific examples are applied to illustrate the principles and the embodiments of the present invention, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present invention; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (7)
1. A display panel characterized by having a display area and a non-display area surrounding the display area; the display area comprises a plurality of display sub-pixels, the display sub-pixels comprise a first transistor and a first light-emitting layer which are electrically connected, the non-display area comprises a plurality of static electricity protection circuit units, and each static electricity protection circuit unit comprises at least one second transistor;
wherein the first transistor includes a first active layer, the second transistor includes a second active layer, and mobility of the second active layer is greater than mobility of the first active layer;
the electrostatic protection circuit unit comprises a first module, wherein the first module comprises at least two second transistors connected in series; the first module has a first end electrically connected to a first common voltage line and a second end electrically connected to a signal line, the first common voltage line being a high-level common voltage line; for a plurality of the second transistors in the electrostatic protection circuit unit, mobility of the second active layer of the second transistor near the second terminal is greater than mobility of the second active layer of the second transistor far from the second terminal; wherein the material of the second active layer of the second transistor near the second end is oxide or polysilicon;
the first module comprises a first sub-transistor and a second sub-transistor which are connected in series; the first grid electrode of the first sub-transistor, the second grid electrode of the second sub-transistor and the second source electrode of the second sub-transistor are connected with the signal line, the first source electrode of the first sub-transistor is connected with the second drain electrode of the second sub-transistor, and the first drain electrode of the first sub-transistor is connected with the first common voltage line.
2. The display panel according to claim 1, wherein the non-display region includes a virtual region disposed near the display region, the virtual region including a plurality of virtual sub-pixels, the electrostatic protection circuit unit being located at a side of the virtual sub-pixels away from the display region; the virtual sub-pixel comprises a third transistor and a second light emitting layer, and the third transistor is not connected with the second light emitting layer.
3. The display panel according to claim 1, wherein the non-display region includes a virtual region disposed near the display region, the virtual region including a plurality of virtual sub-pixels, the electrostatic protection circuit unit being built-in within the virtual sub-pixels; the virtual sub-pixel comprises the second transistor and a second light-emitting layer positioned on one side of the static electricity protection circuit unit, and the second light-emitting layer is not connected with the second transistor.
4. The display panel according to claim 1, wherein the electrostatic protection circuit unit further comprises a second module connected to the first module, the second module comprising at least two of the second transistors connected in series;
the second module has a third terminal connected to the first terminal and the signal line and a fourth terminal electrically connected to a second common voltage line, which is a low-level common voltage line.
5. The display panel of claim 4, wherein the second module comprises a third sub-transistor and a fourth sub-transistor connected in series;
the third gate of the third sub-transistor, the fourth gate of the fourth sub-transistor, and the fourth source of the fourth sub-transistor are connected to the second common voltage line, and the third source of the third sub-transistor is connected to the second source of the second sub-transistor.
6. The display panel according to claim 5, wherein the first common voltage line and the second common voltage line are arranged laterally, and the first sub-transistor, the second sub-transistor, the third sub-transistor, and the fourth sub-transistor are located between the first common voltage line and the second common voltage line and are arranged in order in a direction close to the second common voltage line.
7. A display device comprising the display panel of any one of claims 1-6.
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