CN113079631A - Surface chip mounting stress buffering structure and process - Google Patents
Surface chip mounting stress buffering structure and process Download PDFInfo
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- CN113079631A CN113079631A CN202110307906.8A CN202110307906A CN113079631A CN 113079631 A CN113079631 A CN 113079631A CN 202110307906 A CN202110307906 A CN 202110307906A CN 113079631 A CN113079631 A CN 113079631A
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- wafer
- solder balls
- substrate
- sizes
- steel mesh
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
- H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
Abstract
The invention provides a surface chip mounting stress buffering process, which comprises the following steps: step S1, manufacturing a plurality of pads with different sizes on the surface of the wafer, and then manufacturing a solder mask on the surface of the wafer, wherein the solder mask is provided with openings with corresponding sizes corresponding to the pads; step S2, providing a steel mesh, and making holes with different opening diameters corresponding to the sizes of the solder balls on the steel mesh; solder balls are planted on the surface of the wafer according to the sequence from large to small through the steel mesh, so that the solder balls with different sizes are distributed on the surface of the wafer; and step S3, soldering the solder balls and the bonding pads on the wafer by reflow soldering, cleaning the soldering flux, and cutting the wafer to obtain single chips. The invention uses the welding balls with different sizes as supports, provides a curved surface welding surface adaptive to the base for the large-size chip, and can adapt to the bases with different curvatures; meanwhile, the solder balls with different sizes can meet the requirements of transmitting different currents or signals.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a surface chip mounting stress buffering process.
Background
Along with the popularization of artificial wearable products, more and more chips can all accomplish in the wearable terminal through the flexible PCB board, but because some extreme actions of human structure and human motion need be considered to wearable terminal, often can protect the chip when designing the terminal to prevent in the use because the product appears the solder joint along with the bending of human local position and drops scheduling problem.
For some special wearable articles, the flexible PCB is located on a certain curved surface of a human body, so that the size, the thickness and the like of the terminal can be influenced if a hard plane carrying disc is forcibly made, and the size of the chip is increased along with the gradual increase of the functions of the terminal, so that the chip is more disadvantageously welded.
Meanwhile, for some functional chips, the problem that the surface bonding pads need to transmit different sizes of solder balls due to inconsistent transmission current or circuit matching is caused, and the requirement cannot be met by the conventional mode of interconnecting the solder balls with single diameter.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a surface chip mounting stress buffer structure and a surface chip mounting stress buffer process, which can adapt to bases with different curvatures; meanwhile, the solder balls with different sizes can meet the requirements of transmitting different currents or signals.
In a first aspect, an embodiment of the present invention provides a surface die attach stress buffer structure, including: the method comprises the following steps that a substrate formed by wafer segmentation is used, wherein the surface of the substrate is provided with bonding pads with at least two sizes, and each bonding pad is connected with at least two welding balls with different sizes corresponding to the sizes of the bonding pads; the surface of each solder ball departing from the substrate corresponds to the curved surface on the base.
Furthermore, the size of the bonding pad positioned in the central area of the substrate is the smallest, the size of the bonding pad is gradually increased from the central area of the substrate to the edge area of the substrate, and the size of the bonding pad positioned in the edge area of the substrate is the largest; accordingly, the solder ball size at the central region of the substrate is the smallest, the solder ball size is gradually increased from the central region of the substrate to the edge region of the substrate, and the solder ball size at the edge region of the substrate is the largest.
In a second aspect, an embodiment of the present invention provides a surface chip mounting stress buffering process, including the following steps:
step S1, manufacturing a plurality of pads with different sizes on the surface of the wafer, and then manufacturing a solder mask on the surface of the wafer, wherein the solder mask is provided with openings with corresponding sizes corresponding to the pads;
step S2, providing a steel mesh, and making holes with different opening diameters corresponding to the sizes of the solder balls on the steel mesh; solder balls are planted on the surface of the wafer according to the sequence from large to small through the steel mesh, so that the solder balls with different sizes are distributed on the surface of the wafer;
and step S3, soldering the solder balls and the bonding pads on the wafer by reflow soldering, cleaning the soldering flux, and cutting the wafer to obtain single chips.
Further, step S2 specifically includes:
step S201, providing a steel mesh, and making holes with different opening diameters corresponding to the sizes of the solder balls on the steel mesh;
step S202, selecting the welded balls with different sizes to correspond to the steel mesh openings with corresponding sizes;
step S203, spraying soldering flux on the surface of the wafer, and planting solder balls with the maximum size on the surface of the wafer through a steel mesh;
step S204, cleaning the solder balls on the surface of the wafer, wherein the solder balls cannot leak into the openings of the steel mesh;
and continuously planting solder balls on the surface of the wafer in the order from large to small through the steel mesh.
Furthermore, the solder ball is a solder ball.
Preferably, the largest size solder ball or the largest and next largest size solder balls are copper core solder balls.
The invention has the advantages that: the invention uses the welding balls with different sizes as supports, provides a curved surface welding surface adaptive to the base for the large-size chip, and can adapt to the bases with different curvatures; meanwhile, the solder balls with different sizes can meet the requirements of transmitting different currents or signals.
Drawings
Fig. 1a is a schematic diagram of a chip structure in an embodiment of the invention.
FIG. 1b is a schematic diagram of a steel mesh structure in an embodiment of the present invention.
FIG. 1c is a schematic diagram of the steel mesh openings corresponding to the solder balls with different sizes according to the embodiment of the present invention.
Fig. 1d is a schematic diagram of the embodiment of the present invention, in which the solder balls with the largest size are planted on the wafer surface through the steel mesh.
FIG. 1e is a schematic diagram of an embodiment of the present invention for cleaning solder balls that cannot leak into the openings of the steel mesh.
Fig. 1f to 1h are schematic diagrams illustrating the sequential implantation of solder balls on the wafer surface by the steel mesh.
FIG. 1i is a schematic diagram illustrating solder ball and pad on a wafer by reflow soldering according to an embodiment of the present invention.
Fig. 1j is a schematic diagram of a first application of the chip in the embodiment of the present invention.
Fig. 1k is a schematic diagram of a chip with cu-core solder balls according to an embodiment of the present invention.
FIG. 1l is a diagram illustrating a second application of the chip according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
First, an embodiment of the present invention provides a surface die attach stress buffering structure 1, as shown in fig. 1, including a substrate 101 'formed by dividing a wafer 101, where the surface of the substrate 101' is provided with pads 102 of at least two sizes, and each pad 102 is connected with solder balls 103 of at least two different sizes corresponding to the sizes of the pads 102; the surface of each solder ball 103 departing from the substrate 101' corresponds to the curved surface on the base 2; a base 2 as shown in figure 1 l;
in one embodiment, the size of the pad 102 located in the central region of the substrate 101 'is smallest, the size of the pad 102 increases from the central region of the substrate 101' to the edge region of the substrate 101 ', and the size of the pad 102 located in the edge region of the substrate 101' is largest; accordingly, the size of the solder ball 103 located in the central region of the substrate 101 'is the smallest, the size of the solder ball 103 gradually increases from the central region of the substrate 101' to the edge region of the substrate 101 ', and the size of the solder ball 103 located in the edge region of the substrate 101' is the largest; to be able to adapt to the curvature shown in fig. 1 l; the base 2 may be a PCB with curvature, or a flexible PCB in a bent state, or a ceramic substrate with curvature, etc.;
secondly, an embodiment of the present invention further provides a surface chip mounting stress buffering process, including the following steps:
step S1, manufacturing a plurality of pads 102 with different sizes on the surface of the wafer 101, and then manufacturing a solder mask on the surface of the wafer, wherein openings with corresponding sizes are arranged on the solder mask corresponding to the pads 102;
in the step, firstly, a seed layer is manufactured on the surface of a wafer 101, then, bonding pads 102 with different sizes are manufactured through photoetching and electroplating processes, and the photoresist and the seed layer are removed; then, a solder mask is manufactured on the surface of the wafer, and openings with corresponding sizes are arranged on the solder mask corresponding to the pads 102;
step S2, providing a steel net 104, and forming openings 105 with different opening diameters corresponding to the sizes of the solder balls on the steel net 104; solder balls are planted on the surface of the wafer 101 through the steel mesh 104 according to the sequence from large to small, so that the solder balls 103 with different sizes are distributed on the surface of the wafer 101; specifically, the method comprises the following steps:
as shown in fig. 1b, in step S201, a steel mesh 104 is provided, and openings 105 with different opening diameters corresponding to the sizes of the solder balls are formed on the steel mesh 104; the diameter of the steel mesh opening 105 is between 100 and 1000 μm;
as shown in fig. 1c, in step S202, the solder balls 103 with different sizes are selected to correspond to the steel mesh openings 105 with corresponding sizes; the solder ball 103 in this embodiment is a solder ball;
as shown in fig. 1d, step S203, spraying flux on the surface of the wafer 101, and planting solder balls 103 with the largest size on the surface of the wafer 101 through the steel mesh 104;
as shown in fig. 1e, in step S204, the solder balls on the surface of the wafer 101 that cannot leak into the openings of the steel mesh are cleaned;
as shown in fig. 1f to 1h, solder balls 103 are sequentially implanted on the surface of the wafer 101 sequentially from large to small through a steel mesh 104;
step S3, solder balls 103 are soldered with the soldering pads on the wafer 101 by reflow soldering, soldering flux is cleaned, and the wafer is cut into single chips;
as shown in fig. 1i, the copper mesh 104 is removed, the solder balls 103 are soldered to the pads on the wafer 101 by reflow soldering, the flux is cleaned, and then the wafer 101 is cut;
the obtained chips with the solder balls with different sizes have two typical applications;
as shown in fig. 1j, the solder balls with different sizes of the chip can meet the requirement of transmitting different currents or signals; when the chip is welded with the base 2, the solder ball 103 on the chip can be placed in a plane fixture (a glue film with holes) firstly during reflow soldering, the substrate 101' of the chip can be kept approximately parallel to the base 2 when the solder ball is melted, and the welding surfaces of the solder ball 103 and the base 2 after welding are in the same plane;
in such an application, the largest size solder ball 103 or the largest and next largest size solder balls 103 can be the copper core solder ball 103' to provide support during reflow soldering; as shown in FIG. 1 k;
secondly, as shown in fig. ll, the solder balls with different sizes of the chip are exactly matched with the curvature of the base 2, so that the chip can be attached to the surface of the base 2 with the curvature;
of course, in other embodiments, the arrangement of the solder balls 103 with different sizes on the substrate 101' may be different from that in fig. 1l according to the actual situation on the surface of the base 2.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (6)
1. A surface chip mounting stress buffering structure (1), comprising: the method comprises the steps that a substrate (101 ') formed by dividing a wafer (101) is used, at least two sizes of bonding pads (102) are arranged on the surface of the substrate (101'), and at least two different sizes of welding balls (103) corresponding to the sizes of the bonding pads (102) are connected to the bonding pads (102); the surface of each solder ball (103) departing from the substrate (101') corresponds to the curved surface on the base (2).
2. Surface die attach stress buffering structure (1) according to claim 1,
the size of the pad (102) positioned in the central area of the substrate (101 ') is minimum, the size of the pad (102) is gradually increased from the central area of the substrate (101') to the edge area of the substrate (101 '), and the size of the pad (102) positioned in the edge area of the substrate (101') is maximum; accordingly, the size of the solder ball (103) located in the central region of the substrate (101 ') is smallest, the size of the solder ball (103) increases gradually from the central region of the substrate (101') to the edge region of the substrate (101 '), and the size of the solder ball (103) located in the edge region of the substrate (101') is largest.
3. A surface chip mounting stress buffering process is characterized by comprising the following steps:
step S1, manufacturing a plurality of pads (102) with different sizes on the surface of a wafer (101), and then manufacturing a solder mask on the surface of the wafer, wherein openings with corresponding sizes are arranged on the solder mask corresponding to the pads (102);
step S2, providing a steel mesh (104), and making openings (105) with different opening diameters corresponding to the sizes of the solder balls on the steel mesh (104); solder balls are planted on the surface of the wafer (101) through the steel mesh (104) according to the sequence from large to small, so that the solder balls (103) with different sizes are distributed on the surface of the wafer (101);
and step S3, the solder balls (103) are soldered with the bonding pads on the wafer (101) by reflow soldering, the soldering flux is cleaned, and the wafer is cut into single chips.
4. The surface die attach stress buffering process of claim 3,
step S2 specifically includes:
step S201, providing a steel mesh (104), and manufacturing holes (105) with different opening diameters corresponding to the sizes of the solder balls on the steel mesh (104);
step S202, selecting the solder balls (103) with different sizes to correspond to the steel mesh openings (105) with corresponding sizes;
step S203, spraying soldering flux on the surface of the wafer (101), and planting solder balls (103) with the maximum size on the surface of the wafer (101) through a steel mesh (104);
step S204, cleaning the solder balls which cannot leak into the holes of the steel mesh on the surface of the wafer (101);
and continuously planting the solder balls (103) on the surface of the wafer (101) in the order from large to small through the steel mesh (104).
5. The surface die attach stress buffering process of claim 3 or 4,
the solder balls (103) are solder balls.
6. The surface die attach stress buffering process of claim 5,
the solder ball (103) with the largest size or the solder ball (103) with the largest and the next largest sizes adopts a copper core solder ball (103').
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110307906.8A CN113079631A (en) | 2021-03-23 | 2021-03-23 | Surface chip mounting stress buffering structure and process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110307906.8A CN113079631A (en) | 2021-03-23 | 2021-03-23 | Surface chip mounting stress buffering structure and process |
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| CN113079631A true CN113079631A (en) | 2021-07-06 |
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| CN202110307906.8A Pending CN113079631A (en) | 2021-03-23 | 2021-03-23 | Surface chip mounting stress buffering structure and process |
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| CN104157624A (en) * | 2013-05-14 | 2014-11-19 | 肖步文 | Bump chip and manufacturing technology thereof |
| CN107591383A (en) * | 2017-09-15 | 2018-01-16 | 中国电子科技集团公司第五十八研究所 | The detachable curved surface encapsulated structure of BGA device |
| CN109309069A (en) * | 2018-09-19 | 2019-02-05 | 深圳市心版图科技有限公司 | Welded ball array encapsulates chip and its welding method |
| CN111755339A (en) * | 2020-06-30 | 2020-10-09 | 青岛歌尔微电子研究院有限公司 | Solder paste ball-planting method based on deformable substrate |
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2021
- 2021-03-23 CN CN202110307906.8A patent/CN113079631A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1945802A (en) * | 2006-10-20 | 2007-04-11 | 华为技术有限公司 | Method, circuit board and tool for improving welding spot reliability of ball grating array package device |
| CN102543920A (en) * | 2010-12-21 | 2012-07-04 | 中芯国际集成电路制造(北京)有限公司 | Chip size packaging method and packaging structure |
| CN102569234A (en) * | 2010-12-21 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Ball grid array encapsulating structure and encapsulation method |
| US20120309187A1 (en) * | 2011-05-30 | 2012-12-06 | International Business Machines Corporation | Conformal Coining of Solder Joints in Electronic Packages |
| CN104157624A (en) * | 2013-05-14 | 2014-11-19 | 肖步文 | Bump chip and manufacturing technology thereof |
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