CN113079071A - Method for detecting digital signal in real time by unidirectional wiring - Google Patents

Method for detecting digital signal in real time by unidirectional wiring Download PDF

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Publication number
CN113079071A
CN113079071A CN202010008839.5A CN202010008839A CN113079071A CN 113079071 A CN113079071 A CN 113079071A CN 202010008839 A CN202010008839 A CN 202010008839A CN 113079071 A CN113079071 A CN 113079071A
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signal
duty ratio
line
1out
current
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CN113079071B (en
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李胜
黄敏
方刚
卢进军
刘滔
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Goodwe Jiangsu Power Supply Technology Co ltd
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Goodwe Jiangsu Power Supply Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40026—Details regarding a bus guardian
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The invention relates to a method for real-time detection of digital signals by unidirectional wiring.A duty ratio control signal line of at least one unidirectional wiring is configured between system modules, the period T and the frequency F of a pulse width modulation signal are set according to signal transmission delay time T, and then corresponding duty ratio signal data { d is configured for each digital signal in transmitted n digital signals1％、d2％、d3％、…dn‑1％、dnPercent, finally comparing the duty ratio signal data output by the output end with the duty ratio signal data received by the receiving end to obtain the current signal line state; the Pulse Width Modulation (PWM) signal is added in the digital signal communication process, so that the delay problem of signal transmission can be solved; the fault conditions of open circuit, short circuit, interference and the like of the current line can be detected in one period, the line sensing effect same as that of sending heartbeat data packets is realized, and the fault conditions of open circuit, short circuit, interference and the like of the current line can be detected in one periodThe current state of the line is internally reflected, and the load of a processor and a system is obviously reduced.

Description

Method for detecting digital signal in real time by unidirectional wiring
Technical Field
The invention belongs to the technical field of power conversion, and particularly relates to a method for detecting a digital signal in real time by unidirectional wiring.
Background
The modular system arrangement of the photovoltaic inverter requires that digital signal communication among all system modules in the photovoltaic inverter meets the requirements of high reliability, low delay and the like. Common communication modes of the system module include a CAN bus (Controller Area Network) mode and an RS-485 bus mode.
The traditional CAN bus and RS-485 bus modes and other standard communication protocol modes are relatively mature and reliable. However, the common baud rate of the CAN bus is 500kbps, and the common baud rate of the RS-485 bus is generally no more than 115200bps, and based on the consideration of ensuring the communication stability and reducing the packet loss rate in the communication process, it is difficult to reduce the communication delay by further increasing the baud rate, so that it is difficult to see that the conventional communication protocol mode is difficult to adapt to the low-delay transmission environment of the present day.
On the other hand, in the prior art, in order to sense the connection and disconnection of the lines, heartbeat data packets are transmitted between the client and the two ends of the server at regular time so as to inform the opposite side of the current state. Therefore, under the transmission condition with higher requirement for low delay, the more heartbeat data packets need to be transmitted in a unit time correspondingly to meet the requirement for low delay transmission, however, the more the number of packets sent increases more burden to the system processor, so the traditional communication protocol method is difficult to meet the system requirement in the low delay transmission environment.
Therefore, in order to meet the requirement of low-delay transmission, a communication method based on logic level signals is proposed in the prior art, that is, the logic level signals are routed in one direction and are represented by the potential difference between the level signals and the ground wire, so that the communication method has no delay problem. However, since the heartbeat data packet cannot be sent, effective state information of the current signal line, such as open circuit, short circuit, interference and the like, cannot be determined in an effective manner, and real-time detection of the line cannot be realized; even, when an abnormal state occurs, the signal line may transmit an error signal, and thus, a communication manner of the unidirectional routing logic level signal has a great risk of transmission such as line failure and signal safety.
An easily conceivable scheme for solving the technical problems of the unidirectional wiring communication mode is to adopt a bidirectional wiring logic level signal communication mode, which can be understood as adding a signal line for loop detection in the unidirectional wiring logic level signal line, so that the technical problem that the current state of the signal line cannot be presented in real time is solved. But simultaneously, adopt two-way line and increase the mode that the return circuit detected, can be in vain increase a large amount of redundant pencil in the system to, for realizing above-mentioned return circuit detection function, must occupy the input/output resource of system again in a large number, the wiring degree of difficulty is big, and the testing process is complicated, consequently, two-way line logic level signal's mode also can only be applicable to the wiring space surplus in practical application, the unrestricted condition of system read-write resource and memory space, its limitation is great.
In view of the above, the prior art should be improved to solve the technical problems.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects of the prior art, and provide a method for detecting digital signals in real time by one-way routing, which can meet the requirement of low-delay communication among all component modules of a photovoltaic inverter and can reduce the wiring complexity of a signal transmission system.
In order to solve the above technical problem, the present invention provides a method for detecting a digital signal in real time by using a unidirectional wire, wherein the detection method comprises: step S1 of configuring at least one duty ratio control signal line of one-way routing between the input and output isolation circuits of the system module; a step S2 of setting the period T and the frequency F of the pwm signal based on the signal transmission delay time T; configuring corresponding duty ratio signal data { d ] for each digital signal in the transferred n digital signals1％、d2％、d3％、…dn-1％、dnStep S3 of% }, in which the range d of the duty ratio signal datan% ofIn the range of 0 to 100; and step S4, comparing the duty ratio signal data outputted from the output terminal with the duty ratio signal data received by the receiving terminal to obtain the current signal line state.
Preferably, in the step S2, the signal transmission delay time T is set, the range of the period T of the pwm signal is T ≦ 0.5T, and the range of the frequency F of the pwm signal is F ≧ 2/T.
Still preferably, in step S4, in the current line, the duty ratio data output by the output terminal is set to d for the m-th digital signalmAnd percent, if the duty ratio data received by the receiving end is 0 percent or 100 percent, the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as a fault state.
Still preferably, in step S3, the method further includes configuring different frequencies { (F) for the input and output of the plurality of component modules and/or the plurality of component modules of the system respectively1in，F1out)、(F2in，F2out)、(F3in，F3out)…(Fn-1in，Fn-1out)、(Fnin，Fnout) And configuring a corresponding duty ratio signal { (d)1in％，d1out％)、(d2in％，d2out％)、(d3in％，d4out％)…(dn-1in％，dn-1out％)、(dnin％，dnout%) } wherein, in the current line, for the m-th digital signal output from the first module to the second module, if the frequency of the duty ratio signal received by the receiving ends of the first module and the second module is not F1outNor is F2inF of (A)mIf the current receiving end receives the signal with the duty ratio, the signal with the duty ratio is a non-effective duty ratio signal, and the line state is marked as an input/output end fault state.
Further preferably, in step S4, the output function y of the duty ratio signal received by the receiving end of the second modulemSatisfy ym＝y1out&y2inThen, when 0 < T% T1out≤d1out*T1outWhen y is1outWhen d is equal to 11out*T1out＜t％T1out≤T1outWhen y is1out0, where T is the current time, T1out＝1/F1out(ii) a When 0 < T% T2in≤d2in*T2inWhen y is2in1 is ═ 1; when d is1out*T2in＜t％T2in≤T2inWhen y is2in0, where T is the current time, T2in＝1/F2in。
Still preferably, the method further includes a step of configuring a plurality of signal lines for each component module, and then in step S3, the corresponding duty ratio signal data { D } is configured for each signal line1％、D2％、D3％、…Dn-1％、Dn% } and configuring the corresponding phase angle r1、r2、r3…rn-1、rnThen, in step S4, it is determined whether the high level signal interval of the duty ratio signal received by the receiving end is within the preset range for any of the first signal line and the second signal line, and when the duty ratio signal D received by the receiving end is within the preset rangexAnd the duty ratio D of the first signal line1And a second signal line duty ratio D2If any of the signals is not equal, the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as a fault state.
Further preferably, in step S4, the first signal line and the second signal line of any module are set to have an output signal high level section range of (r)a，ra+2*pi*Da%) and the high level interval of the output signal of the second signal line is in the range of (r)b，rb+2*pi*Db%) is in the range, then, when r isa＜rbAnd (r)a+2*pi*Da％)≤(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)b，ra+2*pi*Da%) in which Dm％＜Da%, and Dm％＜DbPercent, judging that the current line is in a fault state; when r isa＜rbAnd (r)a+2*pi*Da％)＞(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)b，rb+2*pi*Db%) in which Dm％＜Da%, and Dm％＝DbPercent, the first signal line is judged to be short-circuited at this time; when r isa＞rbAnd (r)a+2*pi*Da％)≤(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)a，ra+2*pi*Da%) in which Dm％＝Da%, and Dm％＜DbPercent, the second signal line is judged to be short-circuited at the moment; when r isa＞rbAnd (r)a+2*pi*Da％)＞(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)a，rb+2*pi*Db%) in which Dm％＜Da%, and Dm％＜DbPercent; when r isa＞(rb+2*pi*Db%) or rb＞(ra+2*pi*Da%) and if the current line is short-circuited, the current duty ratio signal DmThe line status is marked as fault status, with% 0.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages:
1. in the digital signal communication process, a Pulse Width Modulation (PWM) signal is added, and the problem of signal transmission delay can be solved as a unidirectional wiring logic level signal. Meanwhile, the PWM signal is a signal transmitted from the output end to the receiving end in a one-way mode, and the PWM signal output by the output end is compared with the PWM signal received by the receiving end, so that the fault conditions of open circuit, short circuit, interference and the like of the current line can be detected in one period, the line sensing function same as that of sending a heartbeat data packet is realized, the current state of the line can be reflected in one period, and the loads of a processor and a system are obviously reduced;
2. different pulse width modulation signal transmission frequencies are configured among the component modules of the photovoltaic inverter and/or the input end and the output end of each component module, or different pulse width modulation signal frequencies are distributed according to the module types, and corresponding duty ratio signals are configured, so that when the PWM signal lines with different frequencies are mutually short-circuited, due to the frequency difference among the component modules, the frequency of the PWM signal received by the receiving end of the component module is different from the PWM frequencies of the input end and/or the output end of the two component modules when the PWM signal lines with different frequencies are reflected on the pulse width modulation signal, at the moment, the short-circuit fault state of the current line input and output signal can be quickly reflected in a certain period, and the real-time detection of the signal line state is realized;
3. configuring the same frequency and a plurality of signal lines for outputting for each component module of the photovoltaic inverter, wherein each signal line has different phase angles, generating a phase difference after the superposition of PWM signals between any two signal lines, and reacting to the abnormality of the PWM signals in a period according to the interval in which the level of the duty ratio signal received by a receiving end is positioned and comparing the phase angle of the output signals of the two modules with the high level interval so as to realize the real-time detection of the states of the signal lines;
4. in actual application, only the frequency parameters among the communication modules need to be defined, and the frequency parameters are not limited by the conditions of the standard protocol of bus transmission, so that the occupation of system resources is obviously reduced, the reliability of the system is effectively improved, the detection is carried out on the line and data signals, the signal line is prevented from transmitting error signals when abnormal conditions occur, and the safety of the system is improved.
Drawings
Fig. 1 is a flowchart illustrating a flow of a method for real-time detecting a digital signal by a unidirectional trace according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating three cases of the waveform amplitude of the digital semaphore PWM square wave signal received by the receiving end in the first embodiment of the present invention;
fig. 3 is a schematic diagram illustrating the waveform amplitude of the digital signal quantity PWM square wave signal received by the receiving end in the second embodiment of the present invention.
Detailed Description
An embodiment of a method for real-time detecting digital signals by unidirectional routing according to the present invention will be described below with reference to the accompanying drawings. Those of ordinary skill in the art will recognize that the described embodiments can be modified in various different ways, without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are illustrative in nature and not intended to limit the scope of the claims. Furthermore, in the present description, the drawings are not to scale and like reference numerals refer to like parts.
It should be noted that, in the embodiments of the present invention, the expressions "first" and "second" are used to distinguish two entities with the same name but different names or different parameters, and it is understood that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and the descriptions thereof in the following embodiments are omitted.
In the embodiment of the invention, a method for detecting a digital signal in real time by unidirectional routing is provided, which is applied between each component module of a photovoltaic inverter, but in other embodiments, the digital signal method can also be applied between various other communication modules or communication components.
Fig. 1 is a flowchart illustrating a flow of a method for detecting a digital signal in real time by using a unidirectional trace according to an embodiment of the present invention. As shown in fig. 1, the method for detecting digital signals in real time by using unidirectional traces according to the embodiment of the present invention includes the following steps: step S1 of configuring the duty ratio control signal line of the unidirectional wiring between the input and output isolation circuits of the system module; a step S2 of setting the period T and the frequency F of the pwm signal based on the signal transmission delay time T; configuring corresponding duty ratio signal data { d ] for each digital signal in the transferred n digital signals1％、d2％、d3％、…dn-1％、dnStep S3 of% }, in which the range d of the duty ratio signal datan% of 0 to 100; and step S4, comparing the duty ratio signal data outputted from the output terminal with the duty ratio signal data received by the receiving terminal to obtain the current signal line state.
Specifically, in step S1, the system operation configuration of the digital signal detection method described in this embodiment only needs to be configured between the input terminal and the output terminal of each component module connected to each other. For example, between a first module and a second module which are connected in a communication manner, the output end of a first module processor is communicated with the input end of a second module processor, the input end of the first module processor is communicated with the output end of the second module processor, and then, an input/output isolation circuit is configured on a path connecting the input/output end of the first module processor and the output/input end of the second module processor, and a corresponding pulse width modulation signal line is configured, that is, each branch path only needs to be configured with a unidirectional pulse width modulation signal line. The pulse width modulation signal line transmits an adjustable duty cycle square wave control signal (hereinafter referred to as PWM).
In step S2, the delay T of transmission is determined according to the signal delay requirement of the current transmission, and in an ideal model, the period T of the filtering requirement PWM should be just equal to 0.5T, i.e. the half-way transmission time under the requirement of the delay T. In general, the period T of the filtering requirement PWM is set to be less than 0.5T, i.e. the period T of the PWM signal ranges from T to 0.5T, and correspondingly, the frequency F of the PWM signal should be the reciprocal of the period T, and the frequency F of the PWM signal ranges from F to 2/T.
In step S3, it is determined how many digital signals the single PWM signal line is used to transmit according to the accuracy of outputting or detecting PWM and the actual requirement of digital signal transmission, and a duty ratio is allocated to each digital signal to be transmitted. For example, if two digital semaphores are communicated, the corresponding duty cycle is assigned { d }1％、d2Percent is replaced; as another example, if three digital semaphores are communicated, then the corresponding duty cycle is assigned { d }1％、d2％、d3％}。
In practical applications, it is usually necessary to implement low-delay communication among a plurality of component modules in a photovoltaic inverter, and accordingly, configuring different frequencies { (F) between a plurality of component modules and/or between the input and the output of a plurality of component modules of a system respectively1in，F1out)、(F2in，F2out)、(F3in，F3out)…(Fn-1in，Fn-1out)、(Fnin，Fnout) And correspondingly configuring the duty ratio signal { (d)1in％，d1out％)、(d2in％，d2out％)、(d3in％，d4out％)…(dn-1in％，dn-1out％)、(dnin％，dnout%) } wherein, in the current line, for the m-th digital signal output from the first module to the second module, if the frequency of the duty ratio signal received by the receiving ends of the first module and the second module is not equal to F, the frequency of the duty ratio signal is not equal to F1outIs not equal to F2inF of (A)mIf the current receiving end receives the signal with the duty ratio, the signal with the duty ratio is a non-effective duty ratio signal, and the line state is marked as an input/output end fault state.
Furthermore, each component module can be configured with a plurality of signal lines for output, and each signal line is configured with a corresponding phase angle { r }1、r2、r3…rn-1、rnAnd duty cycle signal data D1％、D2％、D3％、…Dn-1％、DnPercent, for any first signal line and any second signal line of any component, setting the high level interval range of the output signal of the first signal line to be (r)a，ra+2*pi*Da%) and the high level interval of the output signal of the second signal line is in the range of (r)b，rb+2*pi*Db%) is in the range, then, when r isa＜rbAnd (r)a+2*pi*Da％)≤(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)b，ra+2*pi*Da%) in the range ofIn (D)m％＜Da%, and Dm％＜DbPercent, judging that the current line is in a fault state; when r isa＜rbAnd (r)a+2*pi*Da％)＞(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)b，rb+2*pi*Db%) in which Dm％＜Da%, and Dm％＝Db% due to Dm％＝DbPercent, then judge the first signal line short circuit at this moment; when r isa＞rbAnd (r)a+2*pi*Da％)≤(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)a，ra+2*pi*Da%) in which Dm％＝Da%, and Dm％＜Db% due to Dm％＝DaPercent, then judge the second signal line short circuit at this moment; when r isa＞rbAnd (r)a+2*pi*Da％)＞(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)a，rb+2*pi*Db%) in which Dm％＜Da%, and Dm％＜DbPercent; when r isa＞(rb+2*pi*Db%) or rb＞(ra+2*pi*Da%) and if the current line is short-circuited, the current duty ratio signal DmThe line status is marked as fault status, with% 0.
Example one
In this embodiment, an example of transferring one digital semaphore is taken. Allocating duty ratio d to the digital semaphore1％，d1% should be within the range of 0% to 100%.
Fig. 2 is a schematic diagram illustrating three cases of the waveform amplitude of the digital semaphore PWM square wave signal received by the receiving end in the first embodiment of the present invention; then, as shown in fig. 2, in the current line, if the duty ratio of the duty ratio square wave signal outputted from the output terminal is d1And% in the normal line, the waveform of the duty square wave signal received by the receiving end should be as shown in the first waveform 11, that is, the duty square wave signal output by the output end and the duty square wave signal received by the receiving end should be consistent. With continued reference to fig. 2, in the second waveform 12, when the duty ratio square wave signal received by the receiving end is 0%, i.e. the signal is normally low, the signal line of the receiving end is short-circuited to ground, and in the third waveform 13, when the duty ratio square wave signal received by the receiving end is 100%, i.e. the signal is normally high, the signal line of the receiving end is short-circuited to the power supply. In another case, the receiving end may receive the second waveform 12 and the third waveform 13, and the signal line of the receiving end is also pulled up and/or pulled down, and then the current line is also marked as a fault state, and the operation of the equipment is stopped and the equipment is repaired and maintained. The signal abnormality can be reflected and detected in real time through the waveform in one period of the PWM square wave signal, so that the current fault state of the signal wire can be effectively detected in real time.
Example two
In this embodiment, taking the example of transferring a digital semaphore from a first module to a second module, different frequencies (F) are respectively allocated to the input and output of the first module1in，F1out) The input and output of the second module are respectively configured with different frequencies (F)2in，F2out) And configuring the input end and the output end of the first module and the second module with the duty ratio signal data (d)1in％，d1out%) and (d)2in％，d2out%). Wherein d is1in％、d1out％、d2in% and d2out% should be within the range of 0% to 100%.
Fig. 3 is a schematic diagram illustrating the waveform amplitude of the digital signal quantity PWM square wave signal received by the receiving end in the second embodiment of the present invention. Referring to fig. 3, the digital signal M output by the first module has an output frequency F1outFrequency of input terminal is F1inThen the frequency F3 of M of the digital signal received by the receiving end of the second module is not equal to F1outIs not equal to F1inThen, at this time,the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as an input end and output end fault state.
Meanwhile, in the second embodiment, the digital semaphore PWM square wave signal received by the receiving end is output ymSatisfy ym＝y1out&y2inThen y is1outAnd y2inAre respectively piecewise functions and satisfy when 0 < T% T1out≤d1out*T1outWhen y is1outWhen d is equal to 11out*T1out＜t％T1out≤T1outWhen y is1out0, where T is the current time, T1out＝1/F1out(ii) a When 0 < T% T2in≤d2in*T2inWhen y is2in1 is ═ 1; when d is1out*T2in＜t％T2in≤T2inWhen y is2in0, where T is the current time, T2in＝1/F2in. When the line is abnormal, the output function is y1out&y2inAnd superposing the two functions, and displaying the superposed random waveform image of the two functions and the segmented function. The equipment needs to be stopped in time and maintained.
EXAMPLE III
In a third embodiment of the present invention, two signal lines are set for any component module, and are defined as a first signal line and a second signal line, and duty ratio data { D } respectively configured for the first signal line and the second signal line is set for any component module1％、D2% }, and the phase angles of the first signal line and the second signal line are set to { r } respectively1、r2Determining the high level interval range of the output signal of the first signal line to be (r)a，ra+2*pi*da%) and the high level interval of the output signal of the second signal line is in the range of (r)b，rb+2*pi*db%) is used. By determining the duty cycle received at the receiving endHigh level signal interval of the signal, and duty ratio signal D received by the receiving endxDuty ratio D with first module1And a second module duty cycle D2If any of the signals is not equal, the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as a fault state.
For example, the duty ratio D of the first signal line is set1% is 25%, phase angle r1Is 30 DEG, and the duty ratio D of the second signal line2% is 10%, phase angle r260 DEG, the high level section range of the output signal of the first signal line is in the range of (30 DEG, 120 DEG), the high level section range of the output signal of the second signal line is in the range of (60 DEG, 96 DEG), and r is in the range1＜r2And (r)a+2*pi*Da％)＞(rb+2*pi*Db%) and if the high level range of the output signal is (60 degrees, 96 degrees), the output state is normal, if the high level range of the output signal is not (60 degrees, 96 degrees), DmIs 10%, then Dm％＜Da%, and Dm％＝DbAnd percent, then the first signal line is marked as a short-circuit fault state at this time.
For another example, the duty ratio D of the first signal line is set1% is 25%, phase angle r1Is 30 DEG, and the duty ratio D of the second signal line2% is 40%, phase angle r260 DEG, the high level section range of the output signal of the first signal line is in the range of (30 DEG, 120 DEG), the high level section range of the output signal of the second signal line is in the range of (60 DEG, 204 DEG), and r is in the range1＜r2And (r)a+2*pi*Da％)＜(rb+2*pi*Db%) and if the high level range of the output signal is (60 degrees, 120 degrees), the output state is normal, if the high level range of the output signal is not (60 degrees, 120 degrees), DmIs 10%, then Dm％＜Da%, and Dm％＜DbAnd percent, marking the signal line as a short-circuit fault state at the moment.
Example four
In this embodiment of the present invention, the system is configured such that different frequencies are set between the plurality of component modules and between the output and input terminals of the plurality of component modules, and each or a part of the plurality of component modules is output using a plurality of signal lines.
Then, in this embodiment, for any of the first module and the second module, since the high-level widths are the same, the phase angle is at a certain time tnSimilarly, the high level sections overlap at this time, and due to different frequencies, the overlapping portion of the high level sections is partially gradually reduced and then gradually increased to overlap, and in this process, the overlapping portion of the high level sections may also be gradually reduced to disappear and then gradually increased to overlap. Accordingly, in this process, when the overlapping portion of the high level section is smaller than the error amount allowed by the normal waveform, the fault state of the current signal line can be detected. Further, since the duty ratio is varied, a certain error exists in the error determination of the overlapping portion of the high level section and the normal waveform, but the error is within an acceptable range and does not affect the determination result.
Compared with the prior art, the invention has the following beneficial technical effects due to the adoption of the technical scheme:
1. in the digital signal communication process, a Pulse Width Modulation (PWM) signal is added, and the problem of signal transmission delay can be solved as a unidirectional wiring logic level signal. Meanwhile, the PWM signal is a signal transmitted from the output end to the receiving end in a one-way mode, and the PWM signal output by the output end is compared with the PWM signal received by the receiving end, so that the fault conditions of open circuit, short circuit, interference and the like of the current line can be detected in one period, the line sensing function same as that of sending a heartbeat data packet is realized, the current state of the line can be reflected in one period, and the loads of a processor and a system are obviously reduced;
different pulse width modulation signal transmission frequencies are configured for the input end and the output end of each component module of the photovoltaic inverter, or different pulse width modulation signal frequencies are distributed according to the module types, when the PWM signal lines with different frequencies are mutually short-circuited, due to the frequency difference among the component modules, the frequency of the PWM signal reflected to the pulse width modulation signal and received by the receiving end of the component module is different from the PWM frequencies of the input end and/or the output end of the two component modules, at the moment, the short-circuit fault state of the input and output signal of the current line can be quickly reflected in a certain period, and the real-time detection of the state of the signal line is realized;
configuring the same frequency and a plurality of signal lines for outputting for each component module of the photovoltaic inverter, wherein each signal line has different phase angles, generating a phase difference after the superposition of PWM signals between any two signal lines, and reacting to the abnormality of the PWM signals in a period according to the interval in which the level of the duty ratio signal received by a receiving end is positioned and comparing the phase angle of the output signals of the two modules with the high level interval so as to realize the real-time detection of the states of the signal lines;
4. in actual application, only the frequency parameters among the communication modules need to be defined, and the frequency parameters are not limited by the conditions of the standard protocol of bus transmission, so that the occupation of system resources is obviously reduced, the reliability of the system is effectively improved, the detection is carried out on the line and data signals, the signal line is prevented from transmitting error signals when abnormal conditions occur, and the safety of the system is improved.
The present invention has been described in detail, and the embodiments are only used for understanding the method and the core idea of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the content of the present invention and to implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims (7)

1. A method for real-time detection of digital signals by unidirectional routing is characterized in that the detection method comprises the following steps:
step S1 of configuring at least one duty ratio control signal line of one-way routing between the input and output isolation circuits of the system module;
a step S2 of setting the period T and the frequency F of the pwm signal based on the signal transmission delay time T;
configuring corresponding duty ratio signal data { d ] for each digital signal in the transferred n digital signals1％、d2％、d3％、…dn-1％、dnStep S3 of% }, in which the range d of the duty ratio signal datan% in the range of 0 to 100;
and step S4, comparing the duty ratio signal data outputted from the output terminal with the duty ratio signal data received by the receiving terminal to obtain the current signal line state.
2. The method for real-time detecting digital signals by one-way routing according to claim 1, wherein in the step S2, the signal transmission delay time T is set, and the range of the period T of the pwm signal is T ≦ 0.5T, and the range of the frequency F of the pwm signal is F ≧ 2/T.
3. The method for real-time detecting digital signals by unidirectional routing according to claim 1, wherein in step S4, for the mth digital signal in the current line, the duty ratio data outputted by the output terminal is set to dmAnd percent, if the duty ratio data received by the receiving end is 0 percent or 100 percent, the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as a fault state.
4. The method for real-time detecting digital signals by unidirectional traces according to claim 1, wherein the step S3 further comprises configuring different frequencies { (F) for the input ends and the output ends of the plurality of component modules and/or the plurality of component modules of the system respectively1in，F1out)、(F2in，F2out)、(F3in，F3out)…(Fn-1in，Fn-1out)、(Fnin，Fnout) And configuring a corresponding duty ratio signal { (d)1in％，d1out％)、(d2in％，d2out％)、(d3in％，d4out％)…(dn-1in％，dn-1out％)、(dnin％，dnout%) } step S31, in which,
in the current line, for the mth digital signal output from the first module to the second module, if the frequency of the duty ratio signal received by the receiving end of the second module is not F1outNor is F2inF of (A)mIf the current receiving end receives the signal with the duty ratio, the signal with the duty ratio is a non-effective duty ratio signal, and the line state is marked as an input/output end fault state.
5. The method for real-time detecting digital signals by one-way traces according to claim 4, wherein in step S4, the output function y of the duty ratio signal received by the receiving end of the second module ismSatisfy ym＝y1out&y2inThen, the first step is executed,
when 0 < T% T1out≤d1out*T1outWhen y is1outWhen d is equal to 11out*T1out＜t％T1out≤T1outWhen y is1out0, where T is the current time, T1out＝1/F1out；
When 0 < T% T2in≤d2in*T2inWhen y is2in1 is ═ 1; when d is1out*T2in＜t％T2in≤T2inWhen y is2in0, where T is the current time, T2in＝1/F2in。
6. The method for real-time detection of digital signals through one-way routing according to claim 1 or 4, further comprising a step of configuring a plurality of signal lines for each module, and then configuring corresponding duty cycle signal data { D } for each signal line in step S31％、D2％、D3％、…Dn-1％、Dn% } and configuring the corresponding phase angle r1、r2、r3…rn-1、rnThen, in step S4, it is determined whether the high level signal interval of the duty ratio signal received by the receiving end is within the preset range for any of the first signal line and the second signal line, and when the duty ratio signal D received by the receiving end is within the preset rangexAnd the duty ratio D of the first signal line1And a second signal line duty ratio D2If any of the signals is not equal, the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as a fault state.
7. The method for real-time detecting digital signals by one-way traces according to claim 6, wherein in the step S4, for the first signal line and the second signal line of any module, the high level interval of the output signal of the first signal line is set to be in the range of (r)a，ra+2*pi*Da%) and the high level interval of the output signal of the second signal line is in the range of (r)b，rb+2*pi*Db%) is within the range, then,
when r isa＜rbAnd (r)a+2*pi*Da％)≤(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)b，ra+2*pi*Da%) in which Dm％＜Da%, and Dm％＜DbPercent, judging that the current line is in a fault state;
when r isa＜rbAnd (r)a+2*pi*Da％)＞(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)b，rb+2*pi*Db%) in which Dm％＜Da%, and Dm％＝DbPercent, the first signal line is judged to be short-circuited at this time;
when r isa＞rbAnd (r)a+2*pi*Da％)≤(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)a，ra+2*pi*Da%) in which Dm％＝Da%, and Dm％＜DbPercent, the second signal line is judged to be short-circuited at the moment;
when r isa＞rbAnd (r)a+2*pi*Da％)＞(rb+2*pi*Db%) if the high level interval range of the current duty ratio signal is not in (r)a，rb+2*pi*Db%) in which Dm％＜Da%, and Dm％＜Db％；
When r isa＞(rb+2*pi*Db%) or rb＞(ra+2*pi*Da%) and if the current line is short-circuited, the current duty ratio signal DmThe line status is marked as fault status, with% 0.
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