CN113079071B - Method for detecting digital signals in real time through unidirectional wiring - Google Patents
Method for detecting digital signals in real time through unidirectional wiring Download PDFInfo
- Publication number
- CN113079071B CN113079071B CN202010008839.5A CN202010008839A CN113079071B CN 113079071 B CN113079071 B CN 113079071B CN 202010008839 A CN202010008839 A CN 202010008839A CN 113079071 B CN113079071 B CN 113079071B
- Authority
- CN
- China
- Prior art keywords
- signal
- duty cycle
- 1out
- line
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000008054 signal transmission Effects 0.000 claims abstract description 13
- 238000011897 real-time detection Methods 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims description 4
- 230000006854 communication Effects 0.000 abstract description 22
- 238000004891 communication Methods 0.000 description 18
- 230000005540 biological transmission Effects 0.000 description 14
- 238000001514 detection method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40026—Details regarding a bus guardian
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
The invention relates to a unidirectionalA method for real-time detection of digital signals by wiring comprises configuring at least one duty ratio control signal line of unidirectional wiring between system modules, setting period T and frequency F of pulse width modulation signals according to signal transmission delay time T, and configuring corresponding duty ratio signal data { d ] for each digital signal in n transmitted digital signals 1 ％、d 2 ％、d 3 ％、…d n‑1 ％、d n The duty ratio signal data output by the output end and the duty ratio signal data received by the receiving end are compared at last to obtain the current signal line state; the Pulse Width Modulation (PWM) signal is added in the digital signal communication process, so that the problem of delay of signal transmission can be solved; the method can detect the fault conditions of open circuit, short circuit, interference and the like of the current line in one period, not only realizes the same line sensing function as that of sending the heartbeat data packet, but also can react to the current state of the line in one period, thereby remarkably reducing the load of a processor and a system.
Description
Technical Field
The invention belongs to the technical field of power conversion, and particularly relates to a method for detecting digital signals in real time by unidirectional wiring.
Background
The modularized system arrangement of the photovoltaic inverter requires the digital signal communication among all system modules in the photovoltaic inverter to meet the requirements of high reliability, low delay and the like. Common communication modes of the system module comprise a CAN bus (Controller Area Network, control local area network) mode and an RS-485 bus mode.
The traditional standard communication protocol modes such as a CAN bus mode and an RS-485 bus mode are mature and reliable. However, the common baud rate of the CAN bus is 500kbps, and the common baud rate of the rs-485 bus is generally not more than 115200bps, so it is difficult to reduce the communication delay by further increasing the baud rate based on the consideration of ensuring the communication stability and reducing the packet loss rate in the communication process, so it is easy to see that the conventional communication protocol mode is difficult to adapt to the present low-delay transmission environment.
On the other hand, in the prior art, the on-off of the line is perceived in the transmission process, and the heartbeat data packet is transmitted between the client and the two ends of the server at fixed time so as to inform the opposite party of the current state. Therefore, under the transmission condition that the low-delay requirement is higher, correspondingly, a larger number of heartbeat data packets need to be transmitted in a unit time to meet the requirement of low-delay transmission, however, a larger number of packets can add more burden to the system processor, so that the traditional communication protocol mode also has difficulty in meeting the system requirement of the low-delay transmission environment.
Therefore, in order to meet the low-delay transmission requirement, a communication method based on logic level signals is proposed in the prior art, that is, a unidirectional routing logic level signal is adopted and is embodied by a potential difference between the level signal and a ground line, so that the communication method has no delay problem. However, since the heartbeat data packet cannot be sent, effective state information such as open circuit, short circuit, interference and the like of the current signal line cannot be confirmed in an effective mode, and real-time detection of the line cannot be realized; even when an abnormal state occurs, the signal line transmits an error signal, so that the communication mode of the unidirectional routing logic level signal has great transmission risks such as line failure, signal safety and the like.
The technical problem that the technical problem existing in the unidirectional wiring communication mode is solved easily is that the bidirectional wiring logic level signal communication mode is adopted, and it can be understood that the signal wire for loop detection is added into the unidirectional wiring logic level signal wire, so that the technical problem that the current state of the signal wire cannot be presented in real time is solved. Meanwhile, a bidirectional wiring mode and a loop detection mode are adopted, an increased amount of redundant wiring harnesses can be used in the system, a large amount of input and output resources of the system are required to be occupied to realize the loop detection function, wiring difficulty is high, and a detection process is complex, so that the bidirectional wiring logic level signal mode is applicable to the situation that wiring space is surplus and system read-write resources and storage space are not limited in practical application, and the limitation is large.
In view of this, the prior art should be improved to solve the technical problems.
Disclosure of Invention
The invention aims to solve the technical problem of overcoming the defects of the prior art and providing a method for detecting digital signals in real time by unidirectional routing, which can meet the low-delay communication requirement between component modules of a photovoltaic inverter and can reduce the wiring complexity of a signal transmission system.
In order to solve the technical problems, the method for detecting the digital signal in real time by the unidirectional routing is characterized by comprising the following steps of: s1, configuring at least one duty ratio control signal line of one-way wiring between input and output isolation circuits of a system module; step S2, setting the period T and the frequency F of the pulse width modulation signal according to the signal transmission delay time T; configuring corresponding duty cycle signal data { d ] for each of the n digital signals transferred 1 ％、d 2 ％、d 3 ％、…d n-1 ％、d n A step S3 of% n % is in the range of 0 to 100; and S4, comparing the duty cycle signal data output by the output end with the duty cycle signal data received by the receiving end to acquire the current signal line state.
Preferably, in the step S2, a signal transmission delay time T is set, and a range of a period T of the pwm signal is t.ltoreq.0.5T, and a range of a frequency F of the pwm signal is f.ltoreq.2/T.
Still preferably, in the step S4, in the current line, the duty ratio data outputted from the output terminal is set to d for the mth digital signal m And if the duty cycle data received by the receiving end is 0% or 100%, the duty cycle signal received by the receiving end at present is a non-effective duty cycle signal, and the line state is marked as a fault state.
Still preferably, in the step S3, the method further includes configuring different frequencies { (F) for the input ends and the output ends of the plurality of component modules and/or the plurality of component modules of the system, respectively 1in ，F 1out )、(F 2in ，F 2out )、(F 3in ，F 3out )…(F n-1in ，F n-1out )、(F nin ，F nout ) And configuring a corresponding duty cycle signal { (d) 1in ％，d 1out ％)、(d 2in ％，d 2out ％)、(d 3in ％，d 4out ％)…(d n-1in ％，d n-1out ％)、(d nin ％，d nout A step S31 of%) }, wherein, in the current line, for the mth digital signal output from the first module to the second module, if the duty ratio signals received by the receiving ends of the first module and the second module have a frequency of not being F 1out Nor F 2in F of (2) m And the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as the fault state of the input and output ends.
Further preferably, in step S4, the output function y of the duty cycle signal received by the receiving end of the second module m Satisfy y m ＝y 1out &y 2in Then, when 0 < T% T 1out ≤d 1out *T 1out When y is 1out When d is =1 1out *T 1out ＜t％T 1out ≤T 1out When y is 1out =0, where T is the current time, T 1out ＝1/F 1out The method comprises the steps of carrying out a first treatment on the surface of the When 0 < T% T 2in ≤d 2in *T 2in When y is 2in =1; when d 1out *T 2in ＜t％T 2in ≤T 2in When y is 2in =0, where T is the current time, T 2in ＝1/F 2in 。
Still preferably, the method further comprises the step of configuring a plurality of signal lines for each component module, and in step S3, the corresponding duty cycle signal data { D } is configured for each signal line 1 ％、D 2 ％、D 3 ％、…D n-1 ％、D n % and configuring the corresponding phase angle { r } 1 、r 2 、r 3 …r n-1 、r n In step S4, for any of the first signal line and the second signal lineBetween the signal lines, it is determined whether a high level signal section of the duty ratio signal received by the receiving end is within a preset range, and when the duty ratio signal D received by the receiving end x Duty ratio D with first signal line 1 And a second signal line duty ratio D 2 If any one of the duty cycle signals received by the current receiving end is unequal, the duty cycle signal received by the current receiving end is an inactive duty cycle signal, and the line state is marked as a fault state.
Further preferably, in the step S4, for the first signal line and the second signal line of any module, an output signal high level section range of the first signal line is set to be (r a ，r a +2*pi*D a In the range of%), the output signal high level section of the second signal line is in the range of (r) b ，r b +2*pi*D b In%) of the above-mentioned values, then, when r a ＜r b And (r) a +2*pi*D a ％)≤(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) b ，r a +2*pi*D a In%, where D) m ％＜D a % and D m ％＜D b Judging that the current line is in a fault state; when r is a ＜r b And (r) a +2*pi*D a ％)＞(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) b ，r b +2*pi*D b In%, where D) m ％＜D a % and D m ％＝D b In% at this time, it is determined that the first signal line is short-circuited; when r is a ＞r b And (r) a +2*pi*D a ％)≤(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) a ，r a +2*pi*D a In%, where D) m ％＝D a % and D m ％＜D b In which case it is determined that the second signal line is shorted; when r is a ＞r b And (r) a +2*pi*D a ％)＞(r b +2*pi*D b In%) of the current duty cycle signal, if the current duty cycle signal is in the high level rangeThe range is not (r) a ，r b +2*pi*D b In%, where D) m ％＜D a % and D m ％＜D b The%; when r is a ＞(r b +2*pi*D b % or r) b ＞(r a +2*pi*D a %), if the current line is short-circuited, the current duty cycle signal D m The line status is marked as a fault status,% = 0.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages:
1. the Pulse Width Modulation (PWM) signal is added in the digital signal communication process, and the signal transmission delay problem can be solved as the unidirectional routing logic level signal. Meanwhile, the PWM signal is a signal transmitted from the output end to the receiving end in one direction, and the PWM signal output by the output end is compared with the PWM signal received by the receiving end, so that the fault conditions of open circuit, short circuit, interference and the like of the current line can be detected in one period, the same line sensing effect as that of sending a heartbeat data packet is realized, the current state of the line can be reacted in one period, and the load of a processor and a system is obviously reduced;
2. different pulse width modulation signal transmission frequencies are configured for each component module of the photovoltaic inverter and/or the input end and the output end of each component module, or different pulse width modulation signal frequencies are distributed according to the types of the modules, and corresponding duty ratio signals are configured, so that when PWM signal lines with different frequencies are in short circuit with each other, the frequency of the PWM signal received by the receiving end of the component module is different from the PWM frequency of the input end and/or the output end of the two component modules due to the frequency difference between the component modules, and then the short circuit fault state of the input and output signals of the current line can be rapidly reacted in a certain period, so that the real-time detection of the state of the signal lines is realized;
3. the method comprises the steps that the same frequency is configured for each component module of the photovoltaic inverter, a plurality of signal wires for output are configured, each signal wire has different phase angles, a phase difference is generated after PWM signals between any two signal wires are overlapped, and real-time detection of the state of the signal wires is realized according to the interval in which the level of a duty ratio signal received by a receiving end is located and according to the comparison of the magnitude and the high level interval of the phase angles of the output signals of the current two modules;
4. in practical application, only the frequency parameters among the communication modules are agreed, and the frequency parameters are not constrained by the conditions of the standard protocol of bus transmission, so that the occupation of system resources is obviously reduced, the reliability of the system is effectively improved, the detection is carried out on the line and the data signals, the transmission of error signals by the signal line is avoided when abnormal conditions occur, and the safety of the system is improved.
Drawings
FIG. 1 is a flow chart illustrating a method for detecting digital signals in real time with unidirectional routing according to one embodiment of the present invention;
fig. 2 is a schematic diagram showing three cases of waveform amplitudes of a digital semaphore PWM square wave signal received by a receiving end in the first embodiment of the invention;
fig. 3 is a schematic diagram showing waveform amplitude of a digital signal PWM square wave signal received by a receiving end in the second embodiment of the present invention.
Detailed Description
An embodiment of a method for detecting a digital signal in real time by a unidirectional track according to the present invention will be described below with reference to the accompanying drawings. Those skilled in the art will recognize that the described embodiments may be modified in various different ways without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive in scope. Furthermore, in the present specification, the drawings are not drawn to scale, and like reference numerals denote like parts.
It should be noted that, in the embodiments of the present invention, the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the expressions "first" and "second" are merely used for convenience of description, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
In this embodiment of the present invention, a method for detecting a digital signal in real time by unidirectional routing is provided, which is applied between each component module of a photovoltaic inverter, but in other embodiments, the digital signal method may be applied between various other communication modules or communication components.
Fig. 1 is a flowchart illustrating a method for detecting a digital signal in real time by using a unidirectional wire according to an embodiment of the present invention. As shown in fig. 1, the method for detecting a digital signal in real time by using a unidirectional trace according to the embodiment of the invention includes the following steps: s1, configuring a duty ratio control signal wire of a unidirectional wiring between input and output isolation circuits of a system module; step S2, setting the period T and the frequency F of the pulse width modulation signal according to the signal transmission delay time T; configuring corresponding duty cycle signal data { d ] for each of the n digital signals transferred 1 ％、d 2 ％、d 3 ％、…d n-1 ％、d n A step S3 of% n % is in the range of 0 to 100; and S4, comparing the duty cycle signal data output by the output end with the duty cycle signal data received by the receiving end to acquire the current signal line state.
Specifically, in step S1, the system of the digital signal detection method described in this embodiment is configured only by being configured between the input terminal and the output terminal of each of the mutually connected component modules. For example, between the first module and the second module which are communicatively connected, the output end of the first module processor is communicated with the input end of the second module processor, the input end of the first module processor is communicated with the output end of the second module processor, then, an input/output isolation circuit is configured on a path where the input/output end of the first module processor is connected with the output/input end of the second module processor, and a corresponding pulse width modulation signal line is configured, that is, only a unidirectional pulse width modulation signal line needs to be configured on each branch. The PWM signal line transmits an adjustable duty cycle wave control signal (hereinafter referred to as PWM).
In step S2, the delay T of the transmission is determined according to the signal delay requirement of the current transmission, and in an ideal model, the period T of the filtering requirement PWM should be exactly equal to 0.5T, i.e. half-way transmission time under the requirement of the delay T. In general, the period T of the filtering requirement PWM is set to be less than 0.5T, i.e., the range of the period T of the PWM signal is less than or equal to 0.5T, and correspondingly, the frequency F of the PWM signal is the inverse of the period T, and the range of the frequency F of the PWM signal is greater than or equal to 2/T.
In step S3, according to the accuracy of the output or detection PWM and the actual requirement of the digital signal transmission, it is determined how many digital signals the aforementioned single PWM signal line is used to transmit, and a duty ratio is allocated to each digital signal to be transmitted. For example, if two digital semaphores are transferred, the corresponding duty cycle { d) 1 ％、d 2 % of; as another example, if three digital semaphores are transferred, the corresponding allocated duty cycles { d } 1 ％、d 2 ％、d 3 ％}。
In practical use, the photovoltaic inverter generally needs to achieve low-delay communication among multiple assembly modules, and correspondingly, the photovoltaic inverter also comprises a control circuit for configuring different frequencies { (F) between multiple assembly modules of the system and/or input ends and output ends of the multiple assembly modules respectively 1in ，F 1out )、(F 2in ，F 2out )、(F 3in ，F 3out )…(F n-1in ，F n-1out )、(F nin ，F nout ) And corresponding respective configurations of duty cycle signals { (d) 1in ％，d 1out ％)、(d 2in ％，d 2out ％)、(d 3in ％，d 4out ％)…(d n-1in ％，d n-1out ％)、(d nin ％，d nout A step S31 of%) }, wherein, in the current line, for the mth digital signal output from the first module to the second module, if the frequency of the duty ratio signal received by the receiving ends of the first module and the second module is not equal to F 1out Nor is equal to F 2in F of (2) m And the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as the fault state of the input and output ends.
Further, each component module may also be configured with a plurality of signal lines for output, each signal line being configured with a corresponding phase angle { r } 1 、r 2 、r 3 …r n-1 、r n Sum duty cycle signal data { D } 1 ％、D 2 ％、D 3 ％、…D n-1 ％、D n In the case of% }, the output signal high level range of the first signal line is set to be (r) for any of the first signal line and the second signal line of any of the components a ，r a +2*pi*D a In the range of%), the output signal high level section of the second signal line is in the range of (r) b ，r b +2*pi*D b In%) of the above-mentioned values, then, when r a ＜r b And (r) a +2*pi*D a ％)≤(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) b ，r a +2*pi*D a In%, where D) m ％＜D a % and D m ％＜D b Judging that the current line is in a fault state; when r is a ＜r b And (r) a +2*pi*D a ％)＞(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) b ，r b +2*pi*D b In%, where D) m ％＜D a % and D m ％＝D b % due to D m ％＝D b In the case,%, it is determined that the first signal line is short-circuited; when r is a ＞r b And (r) a +2*pi*D a ％)≤(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) a ，r a +2*pi*D a In%, where D) m ％＝D a % and D m ％＜D b % due to D m ％＝D a In%, then the second signal is determinedA line short circuit; when r is a ＞r b And (r) a +2*pi*D a ％)＞(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) a ，r b +2*pi*D b In%, where D) m ％＜D a % and D m ％＜D b The%; when r is a ＞(r b +2*pi*D b % or r) b ＞(r a +2*pi*D a %), if the current line is short-circuited, the current duty cycle signal D m The line status is marked as a fault status,% = 0.
Example 1
In this embodiment, the transfer of a digital semaphore is taken as an example. Assigning a duty cycle d to the digital signal quantity 1 ％，d 1 % should be in the range of 0% to 100%.
Fig. 2 is a schematic diagram showing three cases of waveform amplitudes of a digital semaphore PWM square wave signal received by a receiving end in the first embodiment of the invention; in the current line, as shown in FIG. 2, if the duty cycle of the duty cycle square wave signal output by the output terminal is d 1 The waveform of the duty cycle square wave signal received by the receiving end should be as shown in the first waveform 11 under normal conditions of the line, that is, the duty cycle square wave signal output by the output end should be consistent with the duty cycle square wave signal received by the receiving end. With continued reference to fig. 2, in the second waveform 12, the duty cycle square wave signal received by the receiving end is 0%, i.e. the signal is very low, then the receiving end signal line is shorted to ground, and in the third waveform 13, the duty cycle square wave signal received by the receiving end is 100%, i.e. the signal is very high, then the receiving end signal line is shorted to the power supply. In another case, the receiving end may also receive the second waveform 12 and the third waveform 13, and the signal line of the receiving end is opened up and/or opened down, so that the current line is marked as a fault state at this time, and the operation of the device is stopped and overhauling and maintenance are performed. The signal abnormality can be reflected by the waveform in one period of the PWM square wave signal and detected in real time, so that the current fault state of the signal line can be effectively detected in real time.
Example two
In this embodiment, taking the example of transferring a digital signal from a first module to a second module, different frequencies (F 1in ，F 1out ) The input and output of the second module are respectively configured with different frequencies (F 2in ，F 2out ) And the input end and the output end of the first module and the second module are respectively configured with the duty ratio signal data (d 1in ％，d 1out % of) and (d) 2in ％，d 2out % of the total weight of the composition. Wherein d 1in ％、d 1out ％、d 2in % and d 2out % should be in the range of 0% to 100%.
Fig. 3 is a schematic diagram showing waveform amplitude of a digital signal PWM square wave signal received by a receiving end in the second embodiment of the present invention. Referring to FIG. 3, the digital signal M output by the first module has an output frequency F 1out The frequency of the input end is F 1in The frequency F3 of M of the digital signal received by the second module receiving end is not equal to F 1out Nor is equal to F 2in At this time, the duty cycle signal received by the current receiving terminal is a non-effective duty cycle signal, and the line state is marked as the fault state of the input and output terminals.
Meanwhile, in the second embodiment, the digital signal quantity PWM square wave signal output y received by the receiving end m Satisfy y m ＝y 1out &y 2in Then y 1out And y 2in Respectively a piecewise function and satisfies the condition that when 0 is less than T percent T 1out ≤d 1out *T 1out When y is 1out When d is =1 1out *T 1out ＜t％T 1out ≤T 1out When y is 1out =0, where T is the current time, T 1out ＝1/F 1out The method comprises the steps of carrying out a first treatment on the surface of the When 0 < T% T 2in ≤d 2in *T 2in When y is 2in =1; when d 1out *T 2in ＜t％T 2in ≤T 2in When y is 2in =0, where T is the current time, T 2in ＝1/F 2in . In the event of an abnormality in the line,the output function is y 1out &y 2in And the superposition of the two functions is displayed as a random waveform image compounded with the piecewise functions. The equipment operation needs to be stopped in time and overhauling and maintenance are carried out.
Example III
In the third embodiment of the present invention, two signal lines are set for any one of the component modules, and the two signal lines are defined as a first signal line and a second signal line, respectively, and the duty ratio data { D ] of the first signal line and the second signal line are respectively configured 1 ％、D 2 The phase angles of the first signal line and the second signal line are set to { r }, respectively 1 、r 2 Determining that the output signal of the first signal line has a high level interval in the range (r a ，r a +2*pi*d a In the range of%), the output signal high level section of the second signal line is in the range of (r) b ，r b +2*pi*d b % of the total weight of the composition). Then the high level signal interval of the duty cycle signal received by the receiving end is determined, and the duty cycle signal D is received when the receiving end receives x Duty cycle D with first module 1 And a second module duty cycle D 2 If any one of the duty cycle signals received by the current receiving end is unequal, the duty cycle signal received by the current receiving end is an inactive duty cycle signal, and the line state is marked as a fault state.
For example, the duty ratio D of the first signal line is set 1 % is 25%, phase angle r 1 At 30 DEG, the duty cycle D of the second signal line 2 % is 10%, phase angle r 2 60 DEG, the range of the high level interval of the output signal of the first signal line is within the range of (30 DEG, 120 DEG), and the range of the high level interval of the output signal of the second signal line is within the range of (60 DEG, 96 DEG), r 1 ＜r 2 And (r) a +2*pi*D a ％)＞(r b +2*pi*D b In%) of the output signal, if the high level interval of the output signal is (60 deg., 96 deg.), the output signal is in a normal output state, such as the output signalThe high level interval range is not within (60 DEG, 96 DEG), D m 10%, D m ％＜D a % and D m ％＝D b And%%, the first signal line is marked as a short-circuit fault state at this time.
For another example, the duty ratio D of the first signal line is set 1 % is 25%, phase angle r 1 At 30 DEG, the duty cycle D of the second signal line 2 % is 40%, phase angle r 2 60 DEG, the range of the high level interval of the output signal of the first signal line is within the range of (30 DEG, 120 DEG), and the range of the high level interval of the output signal of the second signal line is within the range of (60 DEG, 204 DEG), r 1 ＜r 2 And (r) a +2*pi*D a ％)＜(r b +2*pi*D b In%) and if the high level interval range of the output signal is (60 deg., 120 deg.), the output signal is in a normal output state at present, i.e., the high level interval range of the output signal is not (60 deg., 120 deg.), D m 10%, D m ％＜D a % and D m ％＜D b And%%, the signal line is marked as a short-circuit fault state at this time.
Example IV
In this embodiment of the present invention, the system is configured such that different frequencies are set between the plurality of component modules and between the output terminal and the input terminal of the plurality of component modules, and each or part of the plurality of component modules is output using a plurality of signal lines.
In this embodiment, then, the phase angle is at a certain time t due to the same high level width between any of the first and second modules n When the frequencies are different, the overlapping portions of the high-level intervals are partially gradually reduced and then gradually increased to overlap, and in this process, the overlapping portions of the high-level intervals may be gradually reduced to disappear and then gradually increased to overlap. Accordingly, in this process, when the overlapping portion of the high-level intervals is smaller than the allowable error amount of the normal waveform, the fault state of the current signal line can be detected. In addition, since the duty ratio is variedIf the error determination is not performed, the error determination is performed in the high-level section, and the error determination is performed in the normal waveform.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following beneficial technical effects:
1. the Pulse Width Modulation (PWM) signal is added in the digital signal communication process, and the signal transmission delay problem can be solved as the unidirectional routing logic level signal. Meanwhile, the PWM signal is a signal transmitted from the output end to the receiving end in one direction, and the PWM signal output by the output end is compared with the PWM signal received by the receiving end, so that the fault conditions of open circuit, short circuit, interference and the like of the current line can be detected in one period, the same line sensing effect as that of sending a heartbeat data packet is realized, the current state of the line can be reacted in one period, and the load of a processor and a system is obviously reduced;
different pulse width modulation signal transmission frequencies are configured for the input end and the output end of each component module of the photovoltaic inverter, or different pulse width modulation signal frequencies are distributed according to the types of the modules, when PWM signal lines with different frequencies are in short circuit with each other, the frequency of the PWM signal received by the receiving end of the component module is different from the PWM frequency of the input end and/or the output end of the two component modules in response to the pulse width modulation signal due to the frequency difference among the component modules, so that the short circuit fault state of the input and output signals of the current line can be rapidly reacted in a certain period at the moment, and the real-time detection of the state of the signal lines is realized;
the method comprises the steps that the same frequency is configured for each component module of the photovoltaic inverter, a plurality of signal wires for output are configured, each signal wire has different phase angles, a phase difference is generated after PWM signals between any two signal wires are overlapped, and real-time detection of the state of the signal wires is realized according to the interval in which the level of a duty ratio signal received by a receiving end is located and according to the comparison of the magnitude and the high level interval of the phase angles of the output signals of the current two modules;
4. in practical application, only the frequency parameters among the communication modules are agreed, and the frequency parameters are not constrained by the conditions of the standard protocol of bus transmission, so that the occupation of system resources is obviously reduced, the reliability of the system is effectively improved, the detection is carried out on the line and the data signals, the transmission of error signals by the signal line is avoided when abnormal conditions occur, and the safety of the system is improved.
The above detailed description of the present invention is provided to facilitate understanding of the method and its core concept, and is intended to enable those skilled in the art to understand the present invention and to implement it accordingly, and is not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (7)
1. The method for detecting the digital signal in real time by unidirectional wiring is characterized by comprising the following steps of:
s1, configuring at least one duty ratio control signal line of one-way wiring between input and output isolation circuits of a system module;
step S2, setting the period T and the frequency F of the pulse width modulation signal according to the signal transmission delay time T;
configuring corresponding duty cycle signal data { d ] for each of the n digital signals transferred 1 ％、d 2 ％、d 3 ％、…d n-1 ％、d n A step S3 of% n % is in the range of 0 to 100;
and S4, comparing the duty cycle signal data output by the output end with the duty cycle signal data received by the receiving end to acquire the current signal line state.
2. The method for detecting digital signals in real time by unidirectional routing according to claim 1, wherein in the step S2, a signal transmission delay time T is set, a period T of the pulse width modulation signal ranges from T to 0.5T, and a frequency F of the pulse width modulation signal ranges from F to 2/T.
3. The method for real-time detection of digital signals according to claim 1, wherein in step S4, in the current line, for the mth digital signal, the duty ratio data outputted from the output terminal is set to be d m And if the duty cycle data received by the receiving end is 0% or 100%, the duty cycle signal received by the receiving end at present is a non-effective duty cycle signal, and the line state is marked as a fault state.
4. The method for detecting digital signals in real time by unidirectional routing as claimed in claim 1, wherein in step S3, different frequencies { (F) are respectively configured for a plurality of component modules of the system and/or for input ends and output ends of the plurality of component modules 1in ，F 1out )、(F 2in ，F 2out )、(F 3in ，F 3out )…(F n-1in ，F n-1out )、(F nin ，F nout ) And configuring a corresponding duty cycle signal { (d) 1in ％，d 1out ％)、(d 2in ％，d 2out ％)、(d 3in ％，d 4out ％)…(d n-1in ％，d n-1out ％)、(d nin ％，d nout 31%), wherein,
in the current line, for the mth digital signal output from the first module to the second module, if the duty cycle signal received by the receiving end of the second module has a frequency of not less than F 1out Nor F 2in F of (2) m And the duty ratio signal received by the current receiving end is a non-effective duty ratio signal, and the line state is marked as the fault state of the input and output ends.
5. The method for real-time detection of digital signals with unidirectional wires as claimed in claim 4, wherein in step S4, the output function y of the duty cycle signal received by the receiving end of the second module m Satisfy y m ＝y 1out &y 2in Then, the first and second data are obtained,
when 0 < T% T 1out ≤d 1out *T 1out When y is 1out When d is =1 1out *T 1out ＜t％T 1out ≤T 1out When y is 1out =0, where T is the current time, T 1out ＝1/F 1out ；
When 0 < T% T 2in ≤d 2in *T 2in When y is 2in =1; when d 1out *T 2in ＜t％T 2in ≤T 2in When y is 2in =0, where T is the current time, T 2in ＝1/F 2in 。
6. The method for real-time detection of digital signals according to claim 1 or 4, further comprising configuring a plurality of signal lines for each component module, wherein in step S3, corresponding duty cycle signal data { D ] are configured for each signal line 1 ％、D 2 ％、D 3 ％、…D n-1 ％、D n % and configuring the corresponding phase angle { r } 1 、r 2 、r 3 …r n-1 、r n In step S4, it is determined whether the high level signal interval of the duty ratio signal received by the receiving end is within a preset range for any of the first signal line and the second signal line, and when the duty ratio signal D received by the receiving end is received x Duty ratio D with first signal line 1 And a second signal line duty ratio D 2 If any one of the duty cycle signals received by the current receiving end is unequal, the duty cycle signal received by the current receiving end is an inactive duty cycle signal, and the line state is marked as a fault state.
7. The method for real-time detection of digital signals according to claim 6, wherein in said step S4, for the first signal line and the second signal line of any module, the output signal high level range of said first signal line is set to be (r a ，r a +2*pi*D a In a range of%), the output signal of the second signal line is in a high level rangeIn the range (r) b ，r b +2*pi*D b In% of the total weight of the composition), then the first time period of the first time period,
when r is a ＜r b And (r) a +2*pi*D a ％)≤(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) b ，r a +2*pi*D a In%, where D) m ％＜D a % and D m ％＜D b Judging that the current line is in a fault state;
when r is a ＜r b And (r) a +2*pi*D a ％)＞(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) b ，r b +2*pi*D b In%, where D) m ％＜D a % and D m ％＝D b In% at this time, it is determined that the first signal line is short-circuited;
when r is a ＞r b And (r) a +2*pi*D a ％)≤(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) a ，r a +2*pi*D a In%, where D) m ％＝D a % and D m ％＜D b In which case it is determined that the second signal line is shorted;
when r is a ＞r b And (r) a +2*pi*D a ％)＞(r b +2*pi*D b In% of the duty cycle signal, if the high level interval range of the current duty cycle signal is not (r) a ，r b +2*pi*D b In%, where D) m ％＜D a % and D m ％＜D b ％；
When r is a ＞(r b +2*pi*D b % or r) b ＞(r a +2*pi*D a %), if the current line is short-circuited, the current duty cycle signal D m The line status is marked as a fault status,% = 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010008839.5A CN113079071B (en) | 2020-01-06 | 2020-01-06 | Method for detecting digital signals in real time through unidirectional wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010008839.5A CN113079071B (en) | 2020-01-06 | 2020-01-06 | Method for detecting digital signals in real time through unidirectional wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113079071A CN113079071A (en) | 2021-07-06 |
| CN113079071B true CN113079071B (en) | 2023-11-21 |
Family
ID=76608562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010008839.5A Active CN113079071B (en) | 2020-01-06 | 2020-01-06 | Method for detecting digital signals in real time through unidirectional wiring |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113079071B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116990725B (en) * | 2023-09-27 | 2023-12-12 | 成都电科星拓科技有限公司 | Cable in-place signal indication system and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003259623A (en) * | 2002-03-06 | 2003-09-12 | Denso Corp | Method of transmitting signal |
| JP3488153B2 (en) * | 1999-10-27 | 2004-01-19 | Ｎｅｃマイクロシステム株式会社 | Clock duty inspection circuit and microcomputer capable of clock duty inspection |
| CN110231535A (en) * | 2019-06-24 | 2019-09-13 | 爱驰汽车有限公司 | A kind of high-tension circuit method for detecting operation state and system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE60300748T2 (en) * | 2002-05-09 | 2006-05-11 | Kel Corp., Tama | Pulse transmission modulation and demodulation method |
-
2020
- 2020-01-06 CN CN202010008839.5A patent/CN113079071B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3488153B2 (en) * | 1999-10-27 | 2004-01-19 | Ｎｅｃマイクロシステム株式会社 | Clock duty inspection circuit and microcomputer capable of clock duty inspection |
| JP2003259623A (en) * | 2002-03-06 | 2003-09-12 | Denso Corp | Method of transmitting signal |
| CN110231535A (en) * | 2019-06-24 | 2019-09-13 | 爱驰汽车有限公司 | A kind of high-tension circuit method for detecting operation state and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113079071A (en) | 2021-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8566415B2 (en) | Safe torque off over network wiring | |
| EP3939203B1 (en) | Multiple phase pulse power in a network communications system | |
| US20210167813A1 (en) | Initialization and synchronization for pulse power in a network system | |
| US20160064938A1 (en) | Dynamically Configurable Power-Over-Ethernet Apparatus and Method | |
| EP2290838A1 (en) | Remote communication ethernet system and relay | |
| JP2017038364A (en) | Coupler for power line communication and power-over-ethernet | |
| CN109882439B (en) | Fan control system, method and server | |
| CN101160828A (en) | Intelligent platform management interface based management system and method thereof | |
| CN113079071B (en) | Method for detecting digital signals in real time through unidirectional wiring | |
| CN101616189A (en) | A kind of negotiation method of Ethernet port, device and the network equipment | |
| WO2013086720A1 (en) | Power supply method, current sharing module and power supply system | |
| WO2023125994A1 (en) | Foundation fieldbus redundancy method and apparatus | |
| CN112491678A (en) | Digital level transmission circuit and method | |
| CN113194048B (en) | Device for dynamically switching CPU and GPU topology and use method | |
| AU2018232916A1 (en) | Integrated network communications device | |
| CN1221079C (en) | Universal bi-directional digital signal electric separator | |
| CN116418888A (en) | Multi-protocol communication conversion system and device | |
| CN216489919U (en) | Equipment circuit, host circuit and unmanned equipment | |
| JP6019651B2 (en) | Power converter | |
| CN212627933U (en) | NCSI interface signal adapter and NCSI interface communication equipment | |
| US11936485B2 (en) | Power status telemetry for powered devices in a system with power over ethernet | |
| JP7072672B2 (en) | Network system, power supply and power receiving equipment | |
| CN208834153U (en) | A kind of control system circuit for multi-machine collaborative harmonic treating apparatus | |
| CN208638366U (en) | A kind of parallel connection communication system | |
| CN203788309U (en) | Coaxial interconnected switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |