CN210724841U - Digital output interface circuit - Google Patents

Digital output interface circuit Download PDF

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Publication number
CN210724841U
CN210724841U CN201922447004.5U CN201922447004U CN210724841U CN 210724841 U CN210724841 U CN 210724841U CN 201922447004 U CN201922447004 U CN 201922447004U CN 210724841 U CN210724841 U CN 210724841U
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China
Prior art keywords
latch
input
output
relay
unit
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Expired - Fee Related
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CN201922447004.5U
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Chinese (zh)
Inventor
单文盛
王晟磊
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Hunan Normal University
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Hunan Normal University
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Priority to CN201922447004.5U priority Critical patent/CN210724841U/en
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Abstract

The utility model relates to a signal transmission field especially relates to a digital output interface circuit, including the input interface, first latch, the second latch, 8 opto-coupler unit, 8 switch tubes, 8 relay unit, output interface and power input part, the input of first latch is connected on the input interface, the input of opto-coupler unit is connected with an output of first latch, the open control end of switch tube is connected on the output of opto-coupler unit, the output of switch tube is connected on the input of relay unit, the output of relay unit is connected on an input and the output interface of second latch, the output of second latch is connected on the input interface, power input part is used for the power supply. This application adopts the circuit design mode of latch cooperation opto-coupler and triode, but the signal fluctuation of furthest reduction output data, with the output lock on the data level that has established.

Description

Digital output interface circuit
[ technical field ] A method for producing a semiconductor device
The application relates to the field of signal transmission, in particular to a digital output interface circuit.
[ background of the invention ]
Based on the international standard PROFIBUS field bus technology, the field bus is a field bus with a multi-master-slave structure and has the following characteristics: (1) predictable real-time: the PROFIBUS technology adopts a master-slave polling mode, and slave stations cannot actively send data, so that collision can be completely avoided, the maximum waiting time of each station can be predicted, and the PROFIBUS technology has extremely high real-time performance. (2) And high reliability: the predictable real-time property ensures the reliability, and in addition, the PROFIBUS technology is a communication mode based on reliable connection, and is combined with a master station active request mode, errors occurring at any stage can be transmitted within a determined time through diagnosis, and the reliability is higher. For the output module, an error processing strategy is also provided, so that when the module is electrified and initialized and communication is interrupted or in error, the module outputs the default output value set during configuration, and the safety of the whole system is ensured. (3) And high speed: the baud rate support of the system is from 9600 to 12M, and the requirement on the speed can be completely met. (4) Ease of use: the physical layer of the PROFIBUS bus protocol adopts 485 buses as transmission media, only has two lines, the longest length of each section of line can reach 300 meters under the speed of 10M, if a lower baud rate is adopted, the distance can be lengthened, and a powerful configuration tool is added, so that the connection of the whole system becomes very simple, in addition, the module supports the baud rate self-adaption function, the baud rate can be dynamically changed, and the use is very convenient. (5) Flexibility: the system adopts a variable configuration mode, can be large or small in scale, and can meet the requirements of various systems.
PROFIBUS fieldbus technology is typically equipped with LINK modules to work with I/O modules, which are divided into a number of types depending on their use and size. The conventional I/O module has a simple structure, output data is easy to generate signal fluctuation in the using process, and output control is easy to change under the influence of an input end, so that transmission errors are caused.
[ summary of the invention ]
Aiming at the problems that the output data of the I/O module in the prior art is easy to generate signal fluctuation in the using process and the output control is easy to change due to the influence of an input end, the digital output interface circuit adopts the form that a latch is matched with an optocoupler and a triode, can reduce the signal fluctuation of the output data to the maximum extent, and locks the output on the established data level.
The technical scheme adopted for solving the technical problem is as follows:
the utility model provides a digital output interface circuit, digital output interface circuit includes input interface, first latch, second latch, 8 opto-coupler units, 8 switch tubes, 8 relay units, output interface and power input part, the input of first latch is connected on input interface, the input of opto-coupler unit is connected with an output of first latch, the open control end of switch tube is connected on the output of opto-coupler unit, and the output of switch tube is connected on the input of relay unit, the output of relay unit is connected on an input and the output interface of second latch, the output of second latch is connected on input interface, and power input part is used for the power supply.
The first latch and the second latch adopt a latch with the model number of 74HC 573.
And a current-limiting resistor is connected between the input end of the optical coupling unit and one output end of the first latch in series, and the current-limiting resistor is a resistor with the resistance value of 1K omega.
The switch tube adopts a triode, the triode adopts an NPN type triode with the model number of BC817, the base electrode of the triode is connected to the output end of the optocoupler unit, and the collector electrode of the triode is connected to the input end of the relay unit.
The relay unit comprises a relay, a rectifier diode and a filter capacitor, wherein the anode of the rectifier diode is connected with the collector of the triode, the cathode of the rectifier diode is connected to the power supply unit, the first input end of the relay is also connected to the power supply unit, the second input end of the relay is connected to the anode of the rectifier diode, and the filter capacitor is connected to the two ends of the relay in parallel.
The 24V power interface of the input interface is connected with the power input part, and the 24V power interface is connected with a fuse F01 and a filter capacitor bank.
The beneficial effect of this application lies in, this application adopts the circuit design mode of latch cooperation opto-coupler and triode, but reduces voltage fluctuation in the transmission to the at utmost, reduces the production of transmission error.
The present invention will be further described with reference to the accompanying drawings and the detailed description.
[ description of the drawings ]
Fig. 1 is a circuit block diagram of the present application.
Fig. 2 is a schematic diagram of the present application (the fonts and labels in the drawings are too small to be clear, fig. 2 is shown in a multi-block sub-circuit diagram, and fig. 2 is shown only for the purpose of illustration in its entirety).
Fig. 3 is a schematic circuit diagram of a portion of an input interface unit according to the present application.
Fig. 4 is a schematic circuit diagram of a first latch unit according to the present application.
FIG. 5 is a schematic diagram of a second latch unit circuit according to the present application.
Fig. 6 is a schematic diagram of a circuit connection between the optocoupler unit and the transistor according to the present application.
Fig. 7 is a schematic circuit diagram of the relay unit of the present application.
Fig. 8 is a schematic circuit diagram of a portion of an output interface unit according to the present application.
Fig. 9 is a schematic circuit diagram of a power input portion of the present application.
Fig. 10 is a schematic circuit diagram of the power decoupling portion of the present application.
[ detailed description ] embodiments
The present embodiment is a preferred embodiment of the present application, and other embodiments having the same or similar principles and basic structures as the present embodiment are within the scope of the present application.
Please refer to fig. 1 to 10 in combination, the present application mainly includes an input interface, a first latch, a second latch, 8 optocoupler units, 8 switch tubes, 8 relay units, an output interface, and a power input portion, wherein an input end of the first latch is connected to the input interface, an input end of the optocoupler unit is connected to an output end of the first latch, a public control end of the switch tube is connected to an output end of the optocoupler unit, an output end of the switch tube is connected to an input end of the relay unit, an output end of the relay unit is connected to an input end and the output interface of the second latch, an output end of the second latch is connected to the input interface, and the power input portion is used for supplying power.
In this embodiment, an output end of the input interface is connected to a chip selection end (or referred to as an enable end) of the first latch, and outputs a chip selection signal to the first latch to control the first latch to operate, please refer to fig. 4 and 5, in this embodiment, P3.4 is a chip selection end (or referred to as an enable end) of the first latch, and the control signal is output, where P3.4 is 1 (i.e., a high level) output end (i.e., a Q end) signal output, and P3.4 is 0 (i.e., a low level) output end (i.e., a Q end) signal latch;
p3.3 is a chip select terminal (or called an enable terminal) of the second latch, and controls the diagnostic signal, the input terminal (i.e., the D terminal) of P3.3 ═ 0 (i.e., low level) inputs the diagnostic signal, and the input terminal (i.e., the Q terminal) is disconnected when P3.3 ═ 1 (i.e., high level) is high impedance.
In this embodiment, the input interface adopts a 48PIN interface for connecting the controller, the 24V power supply, the VCC power supply and the ground, and in this embodiment, the 24V power supply is input through the input interface to supply power to the present application.
In this embodiment, the first latch and the second latch are latches of type 74HC 573.
In this embodiment, the circuit structures of the 8 optical coupling units are the same, please refer to fig. 6, which illustrates an example of one optical coupling unit, and a current limiting resistor R3 is connected in series between an input end of the optical coupling unit U3 and an output end of the first latch, in this embodiment, the optical coupling unit U3 selects an optical coupler with a model of HMHA28, and the current limiting resistor R3 selects a resistor with a resistance value of 1K Ω.
In this embodiment, the switching tubes have the same circuit structure, and please refer to fig. 6, in which one of the switching tubes is taken as an example to describe the switching tube, the switching tube adopts a transistor Q1, the transistor Q1 adopts an NPN transistor with the model number BC817, a base of the transistor Q1 is connected to the output end of the optocoupler unit U3, and a collector of the transistor Q1 is connected to the input end of the relay unit.
In this embodiment, the circuit structures of the relay units are the same, please refer to fig. 7, in which a relay is taken as an example to explain the relay unit, the relay unit includes RLY1, a rectifier diode D2 and a filter capacitor C10, an anode of the rectifier diode D2 is connected to a collector of a transistor Q1, a cathode of the rectifier diode D2 is connected to the power supply unit, a first input end of the relay RLY1 is also connected to the power supply unit, a second input end of the relay RLY1 is connected to an anode of the rectifier diode D2, and the filter capacitor C10 is connected in parallel to two ends of the relay RLY 1.
In this embodiment, please refer to fig. 8, the output interface adopts a 24PIN interface, and the output ends of the 8 relay units are respectively connected with the output interface for signal output. Referring to fig. 9 and 10, a 24V power interface of the input interface is connected to the power input portion, a fuse F01 and a filter capacitor set are connected to the 24V power interface, and a decoupling capacitor set (decoupling capacitor is also called decoupling capacitor, and decoupling capacitor is connected between the positive and negative electrodes of the circuit, so as to prevent parasitic oscillation of the circuit caused by the positive feedback path formed by the power supply) is connected to the VDD power end of the input interface.
This application adopts the circuit design mode of latch cooperation opto-coupler and triode, but reduces voltage fluctuation in the transmission to the at utmost, reduces transmission error's production.
The above description is only for the purpose of illustrating the preferred embodiments of the present application and is not intended to limit the scope of the present application, which is within the scope of the present application, except that the same or similar principles and basic structures as the present application may be used.

Claims (6)

1. A digital output interface circuit, characterized by: digital output interface circuit includes input interface, first latch, second latch, 8 opto-coupler units, 8 switch tubes, 8 relay units, output interface and power input part, the input of first latch is connected on the input interface, the input of opto-coupler unit is connected with an output of first latch, the open control end of switch tube is connected on the output of opto-coupler unit, and the output of switch tube is connected on the input of relay units, the output of relay units is connected on an input and the output interface of second latch, the output of second latch is connected on the input interface, and power input part is used for the power supply.
2. A digital output interface circuit according to claim 1, wherein: the first latch and the second latch adopt a latch with the model number of 74HC 573.
3. A digital output interface circuit according to claim 1, wherein: and a current-limiting resistor is connected between the input end of the optical coupling unit and one output end of the first latch in series, and the current-limiting resistor is a resistor with the resistance value of 1K omega.
4. A digital output interface circuit according to claim 1, wherein: the switch tube adopts a triode, the triode adopts an NPN type triode with the model number of BC817, the base electrode of the triode is connected to the output end of the optocoupler unit, and the collector electrode of the triode is connected to the input end of the relay unit.
5. A digital output interface circuit according to claim 4, wherein: the relay unit comprises a relay, a rectifier diode and a filter capacitor, wherein the anode of the rectifier diode is connected with the collector of the triode, the cathode of the rectifier diode is connected to the power supply unit, the first input end of the relay is also connected to the power supply unit, the second input end of the relay is connected to the anode of the rectifier diode, and the filter capacitor is connected to the two ends of the relay in parallel.
6. A digital output interface circuit according to claim 1, wherein: and a 24V power supply interface of the input interface is connected with the power supply input part, and a fuse F01 and a filter capacitor bank are connected to the 24V power supply interface.
CN201922447004.5U 2019-12-30 2019-12-30 Digital output interface circuit Expired - Fee Related CN210724841U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201922447004.5U CN210724841U (en) 2019-12-30 2019-12-30 Digital output interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201922447004.5U CN210724841U (en) 2019-12-30 2019-12-30 Digital output interface circuit

Publications (1)

Publication Number Publication Date
CN210724841U true CN210724841U (en) 2020-06-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201922447004.5U Expired - Fee Related CN210724841U (en) 2019-12-30 2019-12-30 Digital output interface circuit

Country Status (1)

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CN (1) CN210724841U (en)

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Granted publication date: 20200609

Termination date: 20211230