CN113078121A - Chip package and manufacturing method thereof - Google Patents
Chip package and manufacturing method thereof Download PDFInfo
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- CN113078121A CN113078121A CN202110242914.9A CN202110242914A CN113078121A CN 113078121 A CN113078121 A CN 113078121A CN 202110242914 A CN202110242914 A CN 202110242914A CN 113078121 A CN113078121 A CN 113078121A
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- chip
- packaging body
- adhesive
- conductive substrate
- metal conductive
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000004806 packaging method and process Methods 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000007789 sealing Methods 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000853 adhesive Substances 0.000 claims description 31
- 230000001070 adhesive effect Effects 0.000 claims description 31
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- 239000002041 carbon nanotube Substances 0.000 claims description 7
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 7
- 229920002635 polyurethane Polymers 0.000 claims description 7
- 239000004814 polyurethane Substances 0.000 claims description 7
- 239000003292 glue Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000002035 prolonged effect Effects 0.000 abstract description 2
- 238000013008 moisture curing Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a chip package and a manufacturing method of the chip package, which relate to the technical field of semiconductors and comprise a lower package body, a conductive substrate, a chip, an upper package body and a metal conductive column, wherein the middle part of the lower package body is provided with a clamping groove, the conductive substrate is fixed in the clamping groove, the chip is fixed on the conductive substrate and is electrically connected with the conductive substrate through a bonding wire, jacks matched with the metal conductive column are arranged on the periphery of the conductive substrate, through holes are arranged on the upper package body corresponding to the jacks, the metal conductive column penetrates through the through holes, and when the upper package body is buckled on the lower package body, one end of the metal conductive column is inserted into the jacks. The chip packaging structure is simple, small in size, good in sealing performance and fast in heat dissipation, damage of external air and moisture to the chip can be effectively prevented, and the service life of the chip is prolonged; the process for packaging the chip by the packaging structure is simple, convenient and quick, the packaging difficulty is low, the efficiency is high, and the packaging quality is stable.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip package and a manufacturing method of the chip package.
Background
Chip acronyms IC, or microcircuit (microcircuit), microchip, chip/chip (chip), is a way in electronics to miniaturize circuits, including primarily semiconductor devices, as well as passive components, and the like, and is often fabricated on the surface of semiconductor wafers. The chip is one of the core components of the modern industrial industries such as computers and electronic products, and the packaging technology is a process technology for wrapping the internal chip to prevent the chip from contacting the outside and prevent the chip from being damaged by the outside. Impurities and undesirable gases in the air, and even water vapor, can corrode the precision circuitry on the chip, thereby causing degradation of electrical performance. The existing chip package has good sealing effect, but has poor heat dissipation performance, which is not beneficial to the delay of the service life of the chip; the manufacturing process of the packaging chip of the existing packaging structure is relatively complex, the packaging difficulty is high, and the processing efficiency and quality of chip packaging are seriously influenced.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a chip package and a method for manufacturing the chip package, which enable the chip package to have good sealing performance and heat dissipation, and have simple and convenient manufacturing process, low packaging difficulty, high efficiency, and stable chip packaging quality.
The invention solves the technical problems by the following technical means:
a chip package comprises a lower package body, a conductive substrate, a chip, an upper package body and a metal conductive column, wherein a clamping groove is formed in the middle of the lower package body, the conductive substrate is fixed in the clamping groove, the chip is fixed on the conductive substrate and is electrically connected with the conductive substrate through a bonding wire, jacks matched with the metal conductive column are formed in the periphery of the conductive substrate, through holes are formed in the upper package body corresponding to the jacks, the metal conductive column penetrates through the through holes, and when the upper package body is buckled on the lower package body, one end of the metal conductive column is inserted into the jacks; the lower packaging body is provided with a sealing groove all around, the periphery of the upper packaging body is provided with sealing protrusions matched with the sealing groove, the sealing protrusions are obliquely provided with a plurality of elastic locking plates, locking holes matched with the elastic locking plates are formed in the sealing groove, and the upper packaging body is tightly buckled on the lower packaging body through the matching effect of the elastic locking plates and the locking holes. The chip packaging structure is simple, small in size and good in sealing performance, and can effectively isolate the chip from the outside and prevent the chip from being damaged by the outside; and the chip is packaged simply, conveniently and quickly by the packaging structure, the working efficiency is high, and the packaging quality is stable.
Furthermore, a radiating fin is arranged on the surface, far away from the chip, of the conductive substrate, and a sealing sleeve matched with the radiating fin is arranged on the lower packaging body. The heat generated by the chip and the conductive substrate can be quickly and effectively dissipated through the design of the radiating fin, so that the chip is prevented from being damaged due to overheating.
Furthermore, the metal conductive column is a cylinder, the metal conductive column is composed of an upper column body and a lower column body which are integrally formed, the diameter of the upper column body is smaller than that of the lower column body, and the center lines of the upper column body and the lower column body are located on the same straight line. The design can disperse the resistance received by the metal conductive column in the process of inserting the metal conductive column into the jack to the upper packaging body, so that the metal conductive column is prevented from loosening due to overlarge stress and even moving towards the outer side of the upper packaging body, the metal conductive column can be ensured to be fully inserted into the jack and be in close contact with the conductive substrate, and the electrifying performance is ensured.
Furthermore, the surface of the lower column body is provided with micropores which are filled with carbon nano tubes. The filled carbon nano tube can reduce the friction force applied in the process that the metal conductive column is inserted into the jack, so that the packaging process is more labor-saving and stable, and the conductivity of the interface of the metal conductive column and the conductive substrate can be enhanced.
Further, the metal conductive column is made of copper or aluminum. The copper or the aluminum has low cost and stable conductive performance, and is suitable for being used as a conductive transmission material.
In addition, the invention also provides a manufacturing method of the chip package, which comprises the following steps:
s1, spraying an adhesive at the bottom of the middle clamping groove of the lower packaging body, and then bonding the conductive substrate in the clamping groove of the middle of the lower packaging body;
s2, drilling a micropore on the surface of the lower cylinder of the metal conductive column by using a nanosecond laser, filling the micropore with a carbon nano tube by using a physical vapor deposition technology, uniformly coating a layer of adhesive on the surface of the upper cylinder of the metal conductive column, and bonding the upper cylinder in a through hole on the upper packaging body;
s3, electrically connecting the chip and the conductive substrate through a bonding wire;
s4, injecting an adhesive into the sealing groove on the lower packaging body, and enabling the adhesive to uniformly submerge the depth of one fourth to one third of the sealing groove;
s5, buckling the upper packaging body on the lower packaging body to enable the upper packaging body and the lower packaging body to be tightly integrated through the matching action of the elastic locking plate and the locking hole;
and S6, after the adhesive is completely cured, cleaning the adhesive on the outer surfaces of the upper packaging body and the lower packaging body.
Furthermore, the adhesive is a moisture-curing polyurethane adhesive. The moisture-curing polyurethane adhesive can be fully reacted and cured with moisture on the surface of the packaging body, fully fills a gap between the sealing groove and the sealing bulge, and tightly bonds the sealing groove and the sealing bulge into a whole, so that the sealing effect on a chip and the stability of the packaging body can be further improved.
Further, before spraying the adhesive in S1, a baffle plate uniformly provided with mesh openings is placed at the bottom of the middle clamping groove of the lower packaging body, and then the adhesive is uniformly sprayed on the baffle plate, so that the adhesive forms dispersed adhesive dots at the bottom of the clamping groove. The glue points which are formed at the bottom of the clamping groove in a dispersing mode can be used for bonding and fixing the conductive substrate, the adhesive can be prevented from forming a glue layer in the clamping groove, and the influence of the glue layer on the heat dissipation of the chip and the conductive substrate is prevented.
The invention has the beneficial effects that: the chip packaging structure is simple, small in size, good in sealing performance and fast in heat dissipation, the chip can be effectively isolated from the outside, the damage of outside air and moisture to the chip is prevented, heat generated by the chip and the conductive substrate can be dissipated quickly, and the service life of the chip is prolonged; the manufacturing process of the chip packaged by the packaging structure is simple and convenient, the packaging difficulty is low, the efficiency is high, and the packaging quality of the chip is stable.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic structural diagram of a lower package of the present invention;
the packaging structure comprises a lower packaging body 1, a conductive substrate 2, a chip 3, an upper packaging body 4, a metal conductive column 5, an upper column body 51, a lower column body 52, a clamping groove 6, a bonding wire 7, a jack 8, a through hole 9, a sealing groove 10, a sealing bulge 11, an elastic locking plate 12, a locking hole 13, a radiating fin 14 and a sealing sleeve 15.
Detailed Description
The present invention will be described in detail with reference to examples below:
example one
As shown in fig. 1 and 2, a chip package includes a lower package body 1, a conductive substrate 2, a chip 3, an upper package body 4 and a metal conductive pillar 5, wherein a clamping groove 6 is formed in the middle of the lower package body 1, the conductive substrate 2 is fixed in the clamping groove 6, the chip 3 is fixed on the conductive substrate 2 and is electrically connected with the conductive substrate 2 through a bonding wire 7, jacks 8 matched with the metal conductive pillars 5 are formed around the conductive substrate 2, through holes 9 are formed in the upper package body 4 at positions corresponding to the jacks 8, the metal conductive pillar 5 penetrates through the through holes 9, and when the upper package body 4 is fastened to the lower package body 1, one end of the metal conductive pillar 5 is inserted into the jack 8; the lower packaging body 1 is equipped with seal groove 10 all around, go up packaging body 4 be equipped with all around with seal groove 10 assorted sealed arch 11, the slope is provided with a plurality of elastic locking plate 12 on sealed arch 11, be equipped with in the seal groove 10 with elastic locking plate 12 assorted lockhole 13, go up packaging body 4 through elastic locking plate 12 with lockhole 13's mating reaction lock closely on packaging body 1 down.
A radiating fin 14 is arranged on one surface of the conductive substrate 2 far away from the chip 3, and a sealing sleeve 15 matched with the radiating fin 14 is arranged on the lower packaging body 1.
The metal conductive column 5 is a cylinder, the metal conductive column 5 is composed of an upper column body 51 and a lower column body 52 which are integrally formed, the diameter of the upper column body 51 is smaller than that of the lower column body 52, and the center lines of the upper column body 51 and the lower column body 52 are located on a uniform straight line.
The surface of the lower column 52 is provided with micropores, which are filled with carbon nanotubes.
The metal conductive column 5 is made of copper.
The chip packaging structure of this embodiment is simple, small, the leakproofness is good, the heat dissipation is fast, can effectively completely cut off chip and external, prevents the harm of outside air, moisture to the chip to can give off the heat that chip and conductive substrate produced fast, improve the life of chip.
Example two
A method of manufacturing a chip package, comprising the steps of:
s1, placing a baffle plate with meshes uniformly arranged at the bottom of the clamping groove 6 in the middle of the lower packaging body 1, uniformly spraying a moisture-curing polyurethane adhesive on the baffle plate to form dispersed glue dots on the bottom of the clamping groove 6, and then bonding the conductive substrate 2 in the clamping groove 6 in the middle of the lower packaging body;
s2, drilling micropores on the surface of the lower cylinder 52 of the metal conductive post 5 by using a nanosecond laser, filling carbon nanotubes in the micropores by using a physical vapor deposition technology, uniformly coating a layer of moisture-curing polyurethane adhesive on the surface of the upper cylinder 51 of the metal conductive post 5, and then bonding the upper cylinder 51 in the through hole 9 on the upper packaging body 4;
s3, electrically connecting the chip 3 and the conductive substrate 2 through the bonding wire 7;
s4, injecting a moisture-curing polyurethane adhesive into the sealing groove 10 on the lower packaging body 1, and enabling the adhesive to be uniformly submerged in the depth of one fourth to one third of the sealing groove 10;
s5, buckling the upper packaging body 4 on the lower packaging body 1, so that the upper packaging body 4 and the lower packaging body 1 are tightly integrated through the matching action of the elastic locking plate 12 and the locking hole 13;
and S6, after the moisture-curing polyurethane adhesive is completely cured, cleaning the adhesive on the outer surfaces of the upper packaging body 4 and the lower packaging body 1.
The packaging process for the chip is simple, convenient and quick, the packaging difficulty is low, the efficiency is high, the packaging quality is stable, the heat dissipation performance is good, the packaging quality of the chip can be effectively improved, and the service life of the chip is ensured.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims. The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.
Claims (8)
1. A chip package is characterized by comprising a lower package body, a conductive substrate, a chip, an upper package body and a metal conductive column, wherein a clamping groove is formed in the middle of the lower package body, the conductive substrate is fixed in the clamping groove, the chip is fixed on the conductive substrate and is electrically connected with the conductive substrate through a bonding wire, jacks matched with the metal conductive column are formed in the periphery of the conductive substrate, through holes are formed in the upper package body corresponding to the jacks, the metal conductive column penetrates through the through holes, and when the upper package body is buckled on the lower package body, one end of the metal conductive column is inserted into the jacks;
the lower packaging body is provided with a sealing groove all around, the upper packaging body is provided with sealing protrusions matched with the sealing groove all around, a plurality of elastic locking plates are arranged on the sealing protrusions in an inclined mode, locking holes matched with the elastic locking plates are formed in the sealing groove, and the upper packaging body is tightly buckled on the lower packaging body through the matching effect of the elastic locking plates and the locking holes.
2. The chip package according to claim 1, wherein a heat sink is disposed on a surface of the conductive substrate away from the chip, and a sealing sleeve matched with the heat sink is disposed on the lower package body.
3. The chip package according to claim 2, wherein the metal conductive pillar is a cylinder, the metal conductive pillar is formed by an upper pillar and a lower pillar that are integrally formed, a diameter of the upper pillar is smaller than a diameter of the lower pillar, and center lines of the upper pillar and the lower pillar are located on a same straight line.
4. The chip package according to claim 3, wherein the lower pillar has micro holes on a surface thereof, and the micro holes are filled with carbon nanotubes.
5. The chip package according to any one of claims 1 to 4, wherein the material of the metal conductive pillar is copper or aluminum.
6. A method of manufacturing the chip package according to claim 5, comprising the steps of:
s1, spraying an adhesive at the bottom of the middle clamping groove of the lower packaging body, and then bonding the conductive substrate in the clamping groove of the middle of the lower packaging body;
s2, drilling a micropore on the surface of the lower cylinder of the metal conductive column by using a nanosecond laser, filling the micropore with a carbon nano tube by using a physical vapor deposition technology, uniformly coating a layer of adhesive on the surface of the upper cylinder of the metal conductive column, and bonding the upper cylinder in a through hole on the upper packaging body;
s3, electrically connecting the chip and the conductive substrate through a bonding wire;
s4, injecting an adhesive into the sealing groove on the lower packaging body, and enabling the adhesive to uniformly submerge the depth of one fourth to one third of the sealing groove;
s5, buckling the upper packaging body on the lower packaging body to enable the upper packaging body and the lower packaging body to be tightly integrated through the matching action of the elastic locking plate and the locking hole;
and S6, after the adhesive is completely cured, cleaning the adhesive on the outer surfaces of the upper packaging body and the lower packaging body.
7. The method of claim 6, wherein the adhesive is a moisture-curable polyurethane adhesive.
8. The method for manufacturing the chip package according to claim 7, wherein in step S1, before the adhesive is sprayed, a baffle plate with meshes uniformly formed thereon is placed at the bottom of the middle slot of the lower package body, and then the adhesive is uniformly sprayed on the baffle plate, so that the adhesive forms the dispersed glue dots at the bottom of the slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110242914.9A CN113078121A (en) | 2021-03-05 | 2021-03-05 | Chip package and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110242914.9A CN113078121A (en) | 2021-03-05 | 2021-03-05 | Chip package and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113078121A true CN113078121A (en) | 2021-07-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110242914.9A Withdrawn CN113078121A (en) | 2021-03-05 | 2021-03-05 | Chip package and manufacturing method thereof |
Country Status (1)
| Country | Link |
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| CN (1) | CN113078121A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114023656A (en) * | 2022-01-06 | 2022-02-08 | 浙江里阳半导体有限公司 | Method and apparatus for manufacturing semiconductor device |
-
2021
- 2021-03-05 CN CN202110242914.9A patent/CN113078121A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114023656A (en) * | 2022-01-06 | 2022-02-08 | 浙江里阳半导体有限公司 | Method and apparatus for manufacturing semiconductor device |
| CN114023656B (en) * | 2022-01-06 | 2022-06-03 | 浙江里阳半导体有限公司 | Method and apparatus for manufacturing semiconductor device |
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Application publication date: 20210706 |
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| WW01 | Invention patent application withdrawn after publication |