CN113067565A

CN113067565A - Anti-interference short-circuit protection circuit with adjustable blanking time for SiC MOSFET

Info

Publication number: CN113067565A
Application number: CN202110216369.6A
Authority: CN
Inventors: 程新红; 刘天天
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2021-02-26
Filing date: 2021-02-26
Publication date: 2021-07-02
Anticipated expiration: 2041-02-26
Also published as: CN113067565B

Abstract

The invention relates to an anti-interference short-circuit protection circuit with adjustable blanking time for a SiC MOSFET, which comprises: the Vds monitoring module is used for monitoring the source-drain voltage Vds of the SiC MOSFET; the Vds comparison module is used for comparing the monitored source-drain voltage Vds with a threshold value and outputting a logic signal, and further comprises: a register module for storing the logic signal; the clock generation module is connected with the register module and used for generating a required working clock signal of the register module; the blanking time configuration module is connected with the register module and is used for adjusting the effective digit and the working clock frequency of the register module; and the logic processing module is used for outputting a short-circuit protection signal when a short circuit occurs according to the logic signal stored in the register module. The invention can adjust blanking time and has stronger anti-interference capability.

Description

Anti-interference short-circuit protection circuit with adjustable blanking time for SiC MOSFET

Technical Field

The invention relates to the technical field of power electronics, in particular to an anti-interference short-circuit protection circuit with adjustable SiC MOSFET blanking time.

Background

Compared with the traditional Si-IGBT, the SiC-MOSFET has the advantages of high switching speed, high breakdown voltage, high temperature resistance, compact packaging, high current density and the like, and can be widely applied to the field of high-frequency and high-voltage power converters, such as electric automobiles, photovoltaic inversion, rail transit and the like. At the same time, the faster switching speed and greater current density of SiC MOSFETs result in short-circuit withstand times, typically below 3 μ s.

The short circuit condition of the SiC MOSFET is divided into two conditions, one is that the power loop is short-circuited before the SiC MOSFET is started, the current rapidly rises after the SiC MOSFET is started, and the source-drain voltage Vds keeps the bus voltage unchanged, and the condition is called hard-start short circuit. The other is that short circuit occurs in the on state after the SiC MOSFET is turned on, and at this time, the source-drain voltage Vds of the SiC MOSFET rapidly increases from the on voltage drop to the bus voltage, and the current also rapidly increases, which is called load short circuit. If no measures are taken to timely turn off the SiC MOSFET, the power consumption of the SiC MOSFET can be rapidly increased under the two short-circuit conditions until the SiC MOSFET is burnt out.

In order to effectively protect the SiC MOSFET from short circuits, it is necessary to quickly detect a short circuit condition and turn off the SiC MOSFET as soon as possible after the short circuit occurs. At present, for the short-circuit protection problem of SiC MOSFET, the commonly used desaat (desaturation) scheme of the conventional Si-IGBT is still widely used. The idea of the desaturation protection scheme is to monitor the source-drain voltage Vds of the SiC MOSFET, compare the source-drain voltage Vds with a reference voltage, and set the reference voltage to a value higher than the conduction voltage drop of the device; when the SiC MOSFET is normally turned on or conducting, the source-drain voltage Vds should be lower than the reference voltage, as shown in fig. 1. The basic working principle of the desaturation protection scheme is as follows: for the hard-on short condition (as shown in fig. 2), after the SiC MOSFET gate driving signal (V _ drive _ logic) is pulled high, a fixed blanking time is passed, and it is detected whether the source-drain voltage Vds drops below the threshold voltage. If the source-drain voltage Vds is reduced to be lower than the threshold voltage, judging that the SiC MOSFET is normally started; and if the source-drain voltage Vds is not reduced to the threshold voltage, judging that the SiC MOSFET generates a hard turn-on short circuit, and simultaneously feeding back a short circuit signal to the protection circuit to turn off the SiC MOSFET. For a load short condition (as shown in fig. 3), after the SiC MOSFET is turned on, it is monitored whether the source-drain voltage Vds is below the threshold voltage. If the source-drain voltage Vds is below the threshold voltage, judging that the SiC MOSFET works in a normal conducting state; if the source-drain voltage Vds exceeds the threshold voltage, the load short circuit of the SiC MOSFET is judged, and meanwhile, a short circuit signal is fed back to the protection circuit to turn off the SiC MOSFET.

The blanking time determines the detection delay of the desaturated short protection scheme for both short conditions. The time delay is too short, and the protection circuit is easy to trigger by mistake; the delay is too long to effectively protect the SiC MOSFET. The blanking time of current desaturation short circuit protection schemes is set by charging the capacitor to a threshold voltage with a current source, i.e., the blanking time is

Wherein C is_DESATTo blank the capacitance value, V_{DESAT_TH}To protect the threshold reference voltage, I_DESATTo charge the blanking capacitor with the current value, a conventional desaturation circuit is shown in fig. 4. There are several problems here: firstly, the blanking time is long, and the influence of current source errors and capacitance value errors is large, so that the blanking time is difficult to accurately set; secondly, a blanking capacitor outside the chip is needed, so that the desaturation protection scheme is difficult to integrate by a single chip, thirdly, the anti-interference capability is poor, and if the source-drain voltage Vds oscillates, misjudgment can be caused. Compared with the traditional Si-IGBT, the SiC MOSFET has high switching speed and obvious switching oscillation, so the desaturation scheme can not be completely suitable for the SiC MOSFET.

Disclosure of Invention

The invention aims to solve the technical problem of providing an anti-interference short-circuit protection circuit with adjustable blanking time of a SiC MOSFET, which can adjust the blanking time and has stronger anti-interference capability.

The technical scheme adopted by the invention for solving the technical problems is as follows: the utility model provides a to SiC MOSFET blanking time adjustable anti-interference short-circuit protection circuit, includes: the Vds monitoring module is used for monitoring the source-drain voltage Vds of the SiC MOSFET; the Vds comparison module is used for comparing the monitored source-drain voltage Vds with a threshold value and outputting a logic signal, and further comprises: a register module for storing the logic signal; the clock generation module is connected with the register module and used for generating a required working clock signal of the register module; the blanking time configuration module is connected with the register module and is used for adjusting the effective digit and the working clock frequency of the register module; and the logic processing module is used for outputting a short-circuit protection signal when a short circuit occurs according to the logic signal stored in the register module.

The Vds monitoring module comprises a fast recovery high-voltage diode and a current source, wherein the cathode of the fast recovery high-voltage diode is connected with the drain electrode of the SiC MOSFET to be monitored, and the anode of the fast recovery high-voltage diode is connected with the current source.

The Vds comparison module is a comparator, a first input end of the comparator is connected with an output end of the Vds monitoring module, a second input end of the comparator is connected with the threshold signal end, and an output end of the comparator is connected with the register module.

The register module adopts an N-bit serial shift register.

The clock generation module is realized by adopting an oscillator.

The logic processing module adopts a digital chip or a logic circuit to realize logic control.

Advantageous effects

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention realizes the adjustment of the blanking time by changing the register digit and the working clock frequency through the added blanking time configuration module, the register module and the clock generation module, and simultaneously, whether the SiC MOSFET is short-circuited is judged according to the monitoring result of the source-drain voltage Vds of n clock periods, so the influence of the oscillation of the source-drain voltage Vds on a protection circuit can be reduced.

Drawings

FIG. 1 is a diagram of a SiC MOSFET normal switching waveform;

FIG. 2 is a schematic diagram of a SiC MOSFET hard on short circuit condition;

FIG. 3 is a schematic diagram of a SiC MOSFET load short circuit condition;

FIG. 4 is a circuit diagram of a conventional DESAT protection circuit configuration;

FIG. 5 is a block diagram of the architecture of an embodiment of the present invention;

FIG. 6 is a circuit implementation diagram of an embodiment of the invention;

FIG. 7 is a diagram illustrating register data during normal switching according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating register data when a hard-on occurs at power-on in accordance with an embodiment of the present invention;

fig. 9 is a diagram illustrating register data when a load short occurs after the power-on according to the embodiment of the present invention.

Detailed Description

The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.

The embodiment of the invention relates to an anti-interference short-circuit protection circuit with adjustable blanking time for a SiC MOSFET (metal oxide semiconductor field effect transistor), which comprises a Vds monitoring module, a Vds comparison module, a register module and a logic processing module which are connected in sequence as shown in fig. 5. The register module is also connected with the clock generation module and the blanking time configuration module.

As shown in fig. 6, the Vds monitoring module is configured to monitor a source-drain voltage Vds of the SiC MOSFET, and may include a fast recovery high-voltage diode and a current source, where a cathode of the fast recovery high-voltage diode is connected to a drain of the SiC MOSFET to be monitored, and an anode of the fast recovery high-voltage diode is connected to the current source. The fast recovery high voltage diode can be formed by connecting a plurality of diodes in series and has reverse breakdown voltage higher than the rated voltage of the SiC MOSFET to be monitored.

The Vds comparison module is used for comparing the monitored source-drain voltage Vds with a threshold value and outputting a logic signal, and can be realized through a comparator, wherein the positive phase input end of the comparator is connected with the output end of the Vds monitoring module, the negative phase input end of the comparator is connected with the threshold value signal end, and the output end of the comparator is connected with the register module.

And the register module is used for storing the logic signal. The register module in the embodiment can adopt an 8-bit serial shift register, and when the effective digit of the 8-bit serial shift register is 8 bits, the register module can store the logic signal output by the Vds comparison module with 8 clock periods, so that when the source-drain voltage Vds oscillates, the short-circuit signal cannot be directly output, and the register module has strong anti-interference capability. In the initial state, the initial values of the register blocks in this embodiment are all 0.

And the clock generation module is used for generating a required working clock signal of the register module and can be realized by adopting an oscillator.

And the blanking time configuration module is used for adjusting the effective digit and the working clock frequency of the register module, and the blanking time can be adjusted by adjusting the effective digit and the working clock frequency of the register module. Blanking time t of short-circuit protection circuit of the present embodiment_blanking＝n×T_clkWhere n is the significand of the register block, T_clkIs the operating clock frequency of the register module.

And the logic processing module is used for outputting a short-circuit protection signal when a short circuit occurs according to the logic signal stored in the register module. The logic processing module can adopt a digital chip to realize logic control, and can also adopt a logic circuit to realize logic control, in the embodiment, an and gate is adopted, and the input end of the and gate is respectively connected with 8 output ends of the 8-bit serial shift register, so that the and gate can output a short-circuit protection signal only when n effective digits of the 8-bit serial shift register are all 1.

The operating principle of the invention is explained below in the context of a switching process of a SiC MOSFET. Firstly, a logic signal of a driving circuit is pulled high, the grid voltage of the SiC MOSFET is gradually increased, the source-drain voltage Vds is reduced, and the device starts to be started. The comparator receives monitored source-drain voltage Vds of the SiC MOSFET, and when the source-drain voltage Vds is higher than a threshold value, the output of the comparator is 1; when the source-drain voltage Vds is lower than the threshold, the comparator output is 0. After the logic signal of the driving circuit is pulled high, the output value of the comparator is read once every other clock cycle, and the data is transferred into a register for storage. After 8 clock cycles, if the register value is all 1, it indicates that the source-drain voltage Vds does not normally drop, a hard-on short circuit occurs, and a short circuit signal is output, as shown in fig. 8. After 8 clock cycles, if the register value is not all 1, indicating that Vds normally drops, the SiC MOSFET is normally turned on. Secondly, after the SiC MOSFET is normally started, the source-drain voltage Vds is reduced to a conduction voltage drop lower than the threshold value of the comparator, the output of the comparator is 0, the register reads all 0, and the SiC MOSFET is normally conducted; if the source-drain voltage Vds has a large on oscillation, the comparator outputs high and low levels alternately, and the register reads 010101, so that the register does not have all 1's, and therefore, a short-circuit signal is not output. If a load short circuit occurs in the SiC MOSFET during the turn-on process, the source-drain voltage Vds rises rapidly to the bus voltage, the comparator output is high, and after 8 clock cycles, the register reads all 1 s and outputs a short circuit signal, as shown in fig. 9. Therefore, the circuit can effectively detect the conditions of hard-on short circuit and load short circuit, and reduces the interference of the source-drain voltage Vds on oscillation to the short-circuit protection circuit. And finally, pulling down the logic signal of the driving circuit, closing the SiC MOSFET device, setting all registers to be 0, and finishing the protection process. Fig. 7, 8 and 9 respectively depict register data change waveforms in three cases of normal switching, hard-on short circuit and load short circuit.

By analyzing the switching process of the SiC MOSFET, the blanking time t of the short-circuit protection circuit can be seen_blanking＝8×T_clkIf the blanking time needs to be adjusted, the adjustment can be realized by changing the number of register bits and the frequency of the working clock. Meanwhile, whether the SiC MOSFET is short-circuited or not is judged according to the monitoring result of the source-drain voltage Vds of 8 clock periods, so that the influence of Vds oscillation on a protection circuit can be reduced.

The invention realizes the adjustment of the blanking time by changing the register digit and the working clock frequency through the added blanking time configuration module, the register module and the clock generation module, and simultaneously, whether the SiC MOSFET is short-circuited or not is judged according to the source-drain voltage Vds monitoring result of n clock periods, so the influence of the source-drain voltage Vds oscillation on the protection circuit can be reduced.

Claims

1. An anti-jamming short-circuit protection circuit with adjustable blanking time for SiC MOSFETs, comprising: the Vds monitoring module is used for monitoring the source-drain voltage Vds of the SiC MOSFET; the Vds comparison module is used for comparing the monitored source-drain voltage Vds with a threshold value and outputting a logic signal, and is characterized by further comprising: a register module for storing the logic signal; the clock generation module is connected with the register module and used for generating a required working clock signal of the register module; the blanking time configuration module is connected with the register module and is used for adjusting the effective digit and the working clock frequency of the register module; and the logic processing module is used for outputting a short-circuit protection signal when a short circuit occurs according to the logic signal stored in the register module.

2. The SiC MOSFET blanking time adjustable anti-jamming short-circuit protection circuit according to claim 1, wherein the Vds monitoring module comprises a fast recovery high voltage diode and a current source, wherein a cathode of the fast recovery high voltage diode is connected to a drain of the SiC MOSFET to be monitored, and an anode of the fast recovery high voltage diode is connected to the current source.

3. The SiC MOSFET blanking time adjustable anti-jamming short-circuit protection circuit according to claim 1, wherein the Vds comparison module is a comparator, a first input terminal of the comparator is connected to an output terminal of the Vds monitoring module, a second input terminal of the comparator is connected to the threshold signal terminal, and an output terminal of the comparator is connected to the register module.

4. The adjustable blanking time antijam short protection circuit for SiC MOSFETs of claim 1, wherein said register module employs an N-bit serial shift register.

5. The adjustable blanking time glitch resistant short-circuit protection circuit for SiC MOSFETs of claim 1 in which said clock generation module is implemented using an oscillator.

6. The SiC MOSFET blanking time adjustable anti-jamming short-circuit protection circuit of claim 1, wherein the logic processing module implements logic control using a digital chip or a logic circuit.