CN113054840A - Charge pump capable of reducing current mismatch - Google Patents
Charge pump capable of reducing current mismatch Download PDFInfo
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- CN113054840A CN113054840A CN202110342846.3A CN202110342846A CN113054840A CN 113054840 A CN113054840 A CN 113054840A CN 202110342846 A CN202110342846 A CN 202110342846A CN 113054840 A CN113054840 A CN 113054840A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
Abstract
The invention discloses a charge pump capable of reducing current mismatch, which comprises: the sink current module is used for generating sink current IN required by charging and discharging and generating reference current of source current IP under the control of reference current IBIAS; the source current module is used for generating a source current IP required by charging and discharging under the control of the reference current generated by the sink current module; the charge-discharge module is used for charging and discharging the oscillating capacitor C under the control of the logic circuit to obtain a variable voltage-controlled voltage VC so as to control the oscillation frequency; the isolation module is used for isolating the sink current IN required by charging and discharging and the reference current for generating the source current IP from the charging and discharging module and the source current module respectively and then outputting the isolated sink current IN and the reference current to ensure that the working state of the sink current module is stable; and the voltage stabilizing module is used for stabilizing the drain voltage of a mirror PMOS tube of the current-pulling module so as to assist in obtaining proportional current.
Description
Technical Field
The present invention relates to a charge pump, and more particularly, to a charge pump capable of reducing current mismatch.
Background
In the phase-locked loop circuit design, a charge pump is often used for charging and discharging a capacitor, so that a proper voltage is provided for a voltage-controlled oscillator to oscillate out a required frequency.
The classical circuit structure of the charge pump is shown IN fig. 1, and comprises a current sinking module 10, a current sourcing module 20 and a charging and discharging module 30, wherein the current sinking module 10 consists of NMOS mirror tubes NM0, NM1 and NM2, and is used for generating a current sinking IN required by charging and discharging and a reference current for generating a current sourcing IP; the current pulling module 20 consists of PMOS tubes PM1 and PM2 and is used for generating a current pulling IP required by charging and discharging; the charge and discharge module 30 is composed of controllable switches S1-S4 and an amplifier AMP1, and is used for charging and discharging an oscillation capacitor C (not shown) under the control of a logic circuit (not shown) to obtain a variable voltage-controlled voltage VC to control the oscillation frequency.
Its upper pull current IP flows through PM2, through switch S1 to the voltage controlled voltage VC node (VC connects the oscillating capacitor, not shown here), and its lower sink current IN flows from VC through switch S2 to NM2, the transient mismatch of IP and IN determining the magnitude of jitter. Let the current mismatch be given by:
mismatch＝(IP-IN)/Ibais
ibais the leftmost bias current. The voltage range of the voltage-controlled voltage VC is wide, and here, 0.2 to 0.8V is taken as an example, it is obvious that when VC is 0.2V, the operating state of the lower NM2 is rapidly deteriorated, which results in a current not being perfectly mirrored from NM0, and when VC is 0.8V, the operating state of the upper PM2 is rapidly deteriorated, which results in a current not being perfectly mirrored from PM 1. In the present invention, the power supply voltage VDD is 0.95V, 1.05V, and 1.15V, for example, under the following conditions: -40 ℃, 25 ℃, 125 ℃ process angle: FF (maximum), TT (average), SS (minimum), note: SS-0.95V-125 deg.C represents a supply voltage of 0.95V and a temperature of 125 deg.C at the SS process corner.
The simulation result is shown IN fig. 2, which shows the deviation of the source current of the upper PM2 and the sink current of the lower NM2 with the change of the voltage-controlled voltage VC, and it is obvious that the source current IP and the sink current IN have different changing trends within the range of the voltage-controlled voltage VC (e.g., 0.2 to 0.8V), and the current mismatch calculation results are tabulated under several typical process corners (corner), and the mismatch under several typical conditions of the structure of fig. 1 is shown IN table 1 below, and it can be seen that the mismatch reaches 23.1% under the limit condition.
TABLE 1 mismatch of classical structures under all conditions (mismatch)
Disclosure of Invention
To overcome the above-mentioned deficiencies of the prior art, it is an object of the present invention to provide a charge pump capable of reducing current mismatch, so as to improve the current mismatch of the charge pump.
To achieve the above and other objects, the present invention provides a charge pump capable of reducing current mismatch, comprising:
the current sinking module is used for generating a current sinking IN required by charging and discharging and generating a reference current of a source current IP;
the source current module is used for generating source current IP required by charging and discharging;
the charge-discharge module is used for charging and discharging the oscillating capacitor C under the control of the logic circuit to obtain a variable voltage-controlled voltage VC so as to control the oscillation frequency;
the isolation module is used for isolating and outputting the sink current IN required by charging and discharging and the reference current for generating the source current IP;
and the voltage stabilizing module is used for stabilizing the drain voltage of a mirror PMOS tube of the current-pulling module so as to assist in obtaining proportional current.
Preferably, the current sinking module comprises a first NMOS mirror image tube (NM0), a second NMOS mirror image tube (NM1), and a third NMOS mirror image tube (NM2), the external bias current (ibis) is connected to the drain of the first NMOS mirror image tube (NM0) and the gates of the first to third NMOS mirror image tubes (NM 0-NM 2), the sources of the first to third NMOS mirror image tubes (NM 0-NM 2) are grounded, and the drains of the second NMOS mirror image tube (NM1) and the third NMOS mirror image tube (NM2) are respectively connected to the isolation module.
Preferably, the isolation module comprises a first NMOS isolation tube (NM11) and a second NMOS isolation tube (NM22), a drain of the second NMOS mirroring tube (NM1) is connected to a source of the first NMOS isolation tube (NM11), and a drain of the third NMOS mirroring tube (NM2) is connected to a source of the second NMOS isolation tube (NM 22); the bias voltage VBN is connected to the grids of the first NMOS isolation tube (NM11) and the second NMOS isolation tube (NM22), the drain electrode of the first NMOS isolation tube (NM11) is connected to the voltage stabilizing module and the current source module, and the drain electrode of the second NMOS isolation tube (NM22) is connected to the charging and discharging module.
Preferably, the first NMOS isolation transistor (NM11) and the second NMOS isolation transistor (NM22) are introduced to improve the poor state of the second NMOS mirroring transistor (NM1) and the third NMOS mirroring transistor (NM2) under the lower voltage condition of the voltage-controlled voltage VC by providing the proper bias voltage to the bias Voltage (VBN) node.
Preferably, when the voltage-controlled voltage VC gradually increases, the drain terminal voltages of the first NMOS isolation transistor (NM11) and the second NMOS isolation transistor (NM22) are faster than the source terminal voltages, and the drain terminal voltages of the second NMOS mirror transistor (NM1) and the third NMOS mirror transistor (NM2) are less variable, so as to still work in a saturation region, so as to sacrifice the working states of the first NMOS isolation transistor (NM11) and the second NMOS isolation transistor (NM22) to protect the states of the second NMOS mirror transistor (NM1) and the third NMOS mirror transistor (NM 2).
Preferably, the voltage stabilizing module includes an operational amplifier (AMP2), a non-inverting input terminal of which is connected to the drain of the first NMOS isolation tube (NM11) and the source current module, an inverting input terminal of which is connected to the charge-discharge module, and an output terminal of which is connected to the source current module.
Preferably, the source current module comprises a first PMOS transistor (PM1) and a second PMOS transistor (PM2), a drain of the first PMOS transistor (PM1) is connected to a drain of the first NMOS isolation transistor (NM11) and a non-inverting input terminal of the operational amplifier (AMP2), and a drain of the second PMOS transistor (PM2) is connected to the charge-discharge module; the grid electrodes of the first PMOS transistor (PM1) and the second PMOS transistor (PM2) are connected with the output end of the operational amplifier (AMP2), and the source electrodes of the first PMOS transistor (PM1) and the second PMOS transistor (PM2) are connected with a power supply.
Preferably, the drain voltages of the first PMOS mirror tube (PM1) and the second PMOS mirror tube (PM2) are approximately equal through the operational amplifier (AMP2), so that the aim of consistent working states of the second PMOS mirror tube (PM2) and the first PMOS mirror tube (PM1) is fulfilled.
Preferably, the charge-discharge module comprises first to fourth controllable switches (S1-S4) and an amplifier (AMP1), the drain of the second NMOS isolation tube (NM22) is connected to one end of the second controllable switch (S2) and a fourth controllable switch (S4), the other end of the second controllable switch (S2), one end of the first controllable switch (S1) and the non-inverting input end of the amplifier (AMP1) form a voltage-controlled voltage VC node, the inverting input terminal of the amplifier (AMP1) is short-circuited with the output of the amplifier (AMP1) and is connected to the other terminal of the fourth controllable switch (S4), the inverting input terminal of the operational amplifier (AMP2) and one terminal of the third controllable switch (S3), the other end of the third controllable switch (S3) is connected with the other end of the first controllable switch (S1) and is connected to the drain electrode of the first PMOS transistor (PM 1).
Compared with the prior art, the charge pump capable of reducing current mismatch generates the sink current IN required by charging and discharging and the reference current for generating the source current IP through the sink current module, generates the source current IP required by charging and discharging through the source current module, obtains the variable voltage-controlled voltage VC by charging and discharging the oscillating capacitor C under the control of the logic circuit through the charging and discharging module to control the oscillating frequency, outputs the sink current IN required by charging and discharging and the reference current for generating the source current IP after isolating the sink current IN required by charging and discharging and the reference current for generating the source current IP through the isolating module, and stabilizes the drain voltage of the mirror image PMOS tube of the source current module to assist IN obtaining proportional current through the voltage stabilizing module, thereby achieving the purpose of improving the current mismatch of the charge pump.
Drawings
FIG. 1 is a block diagram of a conventional charge pump circuit;
FIG. 2 is a graph illustrating a simulation of mismatch between current IP and IN IN the prior art;
FIG. 3 is a circuit diagram of a first embodiment of a charge pump with reduced current mismatch according to the present invention;
FIG. 4 is a mismatch simulation curve of the source current IN and sink current IP IN accordance with the first embodiment of the present invention;
FIG. 5 is a circuit diagram of a second embodiment of a charge pump with reduced current mismatch according to the present invention;
fig. 6 is a mismatch simulation curve of the sink current IP and the source current IN according to the second embodiment of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 3 is a circuit diagram of a charge pump capable of reducing current mismatch according to a first embodiment of the present invention. As shown in fig. 3, in a first embodiment of the present invention, a charge pump capable of reducing current mismatch includes: the current sinking module 10, the current pulling module 20, the charging and discharging module 30, the isolation module 40 and the voltage stabilizing module 50.
The sink current module 10 is configured to generate a sink current IN required for charging and discharging and a reference current for generating a source current IP under the control of a reference current IBIAS; a source current module 20, configured to generate a source current IP required for charging and discharging under the control of the reference current generated by the sink current module 10; a charge and discharge module 30 for charging and discharging the oscillation capacitor C (not shown) under the control of a logic circuit (not shown) to obtain a variable voltage-controlled voltage VC to control the oscillation frequency; the isolation module 40 is used for isolating the sink current IN required by charging and discharging and the reference current for generating the source current IP from the charging and discharging module 30 and the source current module 20 respectively and then outputting the isolated current to ensure that the working state of the sink current module 10 is stable; the voltage stabilizing module 50 is used for stabilizing the drain voltages of the mirror PMOS transistors, namely the first to second PMOS transistors PM1 to PM2, of the current-drawing module 20 to assist in obtaining the proportional current.
In the first embodiment of the present invention, the sink current module 10 is composed of first to third NMOS mirroring transistors NM0, NM1 and NM2, the source current module 20 is composed of first to second PMOS transistors PM1 and PM2, the charge and discharge module 30 is composed of controllable switches S1 to S4 and an amplifier AMP1, the isolation module 40 is composed of first to second NMOS isolation transistors NM11 and NM22, and the voltage stabilization module 50 is composed of an operational amplifier AMP 2.
The external bias current IBAIS is connected to the drain of the first NMOS mirror tube NM0 and the gates of the first to third NMOS mirror tubes NM 0-NM 2, the sources of the first to third NMOS mirror tubes NM 0-NM 2 are grounded GND, the drain of the second NMOS mirror tube NM1 is connected to the source of the first NMOS isolation tube NM11, and the drain of the third NMOS mirror tube NM2 is connected to the source of the second NMOS isolation tube NM 22; the bias voltage VBN is connected to the grids of the first to second NMOS isolation tubes NM11 and NM22, the drain electrode of the first NMOS isolation tube NM11 is connected to the non-inverting input end of the operational amplifier AMP2 and the drain electrode of the first PMOS tube PM1, and the drain electrode of the second NMOS isolation tube NM22 is connected to one ends of the second controllable switch S2 and the fourth controllable switch S4; the other end of the second controllable switch S2, one end of the first controllable switch S1 and the non-inverting input end of the amplifier AMP1 form a voltage-controlled voltage VC node, the inverting input end of the amplifier AMP1 is connected with the other end of the fourth controllable switch S4, the inverting input end of the operational amplifier AMP2 and one end of the third controllable switch S3 after being short-circuited with the output of the amplifier AMP1, and the other end of the third controllable switch S3 and the other end of the first controllable switch S1 are connected to the drain electrode of the second PMOS transistor PM 2; the output of the operational amplifier AMP2 is connected to the gates of the first to second PMOS transistors PM1 to PM2, the sources of the first to second PMOS transistors PM1 to PM2 are connected to the power supply VDD, and implicitly, the positive power supply terminal and the negative power supply terminal of the amplifier AMP1 and the operational amplifier AMP2 are connected to the power supply VDD and the ground GND respectively.
As shown in fig. 3, the first to second NMOS isolation transistors NM11, NM22 are introduced to improve the bad state of the second to third NMOS mirror transistors NM1, NM2 under the condition that the voltage-controlled voltage VC is lower voltage, when the voltage-controlled voltage VC is gradually increased, the drain terminals of the first to second NMOS isolation transistors NM11, NM22 are faster than the source terminal voltage, and the drain terminal voltages of the second to third NMOS mirror transistors NM1, NM2 are less changed, so as to still operate in the saturation region, so as to sacrifice the operating state of the first to second NMOS isolation transistors NM11, NM22 to protect the states of the second to third NMOS mirror transistors NM1, NM2, thereby enabling the third NMOS mirror transistor NM2 to better mirror the state of the first NMOS mirror transistor NM 0.
In the first embodiment of the present invention, the operational amplifier AMP2 is introduced to the upper side of the charge pump, so that the voltages at the drain terminals of the first to second PMOS mirroring transistors PM1 and PM2 are approximately equal, thereby achieving the purpose of the consistency of the working states of the second PMOS mirroring transistor PM2 and the first PMOS mirroring transistor PM1, solving the problem of current mismatch of the second PMOS mirroring transistor PM2, and further reducing the mismatch by matching with the following first to second NMOS isolation transistors NM11 and NM 22.
As shown IN fig. 4, the first embodiment of the present invention is simulated, where VC is 0-0.8V, the current of the source current IP changes less than that IN fig. 2, and when VC is 0.2-0.8V, the current trend difference between the source current IP and the sink current IN of the present invention is smaller than that IN fig. 2, so as to improve the mismatch, as shown IN table 2, the maximum value of the mismatch of the improved circuit under all conditions is 3%, which is improved by 20% compared with the previous one.
Table 2 mismatch under all conditions (mismatch) of the first example after improvement
Fig. 5 is a circuit structure diagram of a second embodiment of the charge pump capable of reducing current mismatch according to the present invention, which is actually a mirror circuit of fig. 3, and is obtained by changing the left NMOS transistor of fig. 3 to a PMOS transistor and changing the PMOS transistor to an NMOS transistor, and correspondingly changing the connection relationship according to the device principle. As shown in fig. 5, in a second embodiment of the present invention, a charge pump capable of reducing current mismatch includes: the current sinking module 10, the current pulling module 20, the charging and discharging module 30, the isolation module 40 and the voltage stabilizing module 50.
A sink current module 10, configured to generate a sink current IN under control of the reference current generated by the source current module 20; the source current module 20 is used for generating a source current IP required by charging and discharging and generating a reference current of a sink current IN under the control of a reference current IBIAS; a charge and discharge module 30 for charging and discharging the oscillation capacitor C (not shown) under the control of a logic circuit (not shown) to obtain a variable voltage-controlled voltage VC to control the oscillation frequency; the isolation module 40 is used for isolating the source current IP required by charging and discharging and the reference current generating the sink current IN from the charging and discharging module 30 and the sink current module 10 respectively and then outputting the isolated source current IP and the reference current to ensure that the source current module 20 is stable IN working state; the voltage stabilizing module 50 is used for stabilizing drain voltages of the mirror NMOS transistors, i.e., the first to second NMOS transistors NM 1-NM 2, of the current sinking module 10 to assist in obtaining proportional currents.
In the second embodiment of the present invention, the sink current module 10 is composed of first to second NMOS mirroring transistors NM1 and NM2, the source current module 20 is composed of first to third PMOS transistors PM0, PM1 and PM2, the charge and discharge module 30 is composed of controllable switches S1 to S4 and an amplifier AMP1, the isolation module 40 is composed of first to second PMOS isolation transistors PM11 and PM22, and the voltage stabilization module 50 is composed of an operational amplifier AMP 2.
The external bias current IBAIS is connected to the drain electrode of the first PMOS mirror tube PM0 and the grid electrodes of the first to third PMOS mirror tubes PM0 to PM2, the source electrodes of the first to third PMOS mirror tubes PM0 to PM2 are connected with a power supply VDD, the drain electrode of the second PMOS mirror tube PM1 is connected with the source electrode of the first PMOS isolation tube PM11, and the drain electrode of the third PMOS mirror tube PM2 is connected with the source electrode of the second PMOS isolation tube PM 22; the bias voltage VBN is connected to the grids of the first PMOS isolation tube PM11, the second PMOS isolation tube PM22, the drain electrode of the first PMOS isolation tube PM11 is connected to the non-inverting input end of the operational amplifier AMP2 and the drain electrode of the first NMOS tube NM1, and the drain electrode of the second PMOS isolation tube PM22 is connected to one ends of the first controllable switch S1 and the third controllable switch S3; the other end of the first controllable switch S1, one end of the second controllable switch S2 and the non-inverting input end of the amplifier AMP1 form a voltage-controlled voltage VC node, the inverting input end of the amplifier AMP1 is connected with the other end of the third controllable switch S3, the inverting input end of the operational amplifier AMP2 and one end of the fourth controllable switch S4 after being short-circuited with the output of the amplifier AMP1, and the other end of the fourth controllable switch S4 and the other end of the second controllable switch S2 are connected to the drain electrode of the second NMOS transistor NM 2; the output of the operational amplifier AMP2 is connected to the gates of the first to second NMOS transistors NM 1-NM 2, the sources of the first to second NMOS transistors NM 1-NM 2 are connected to ground GND, and implicitly, the positive power supply terminal and the negative power supply terminal of the amplifier AMP1 and the operational amplifier AMP2 are connected to the power supply VDD and the ground GND, respectively.
As shown in fig. 5, by providing an appropriate bias voltage to the bias voltage VBN node, the first to second PMOS isolation transistors PM11 and PM22 are introduced to improve the situation that the states of the second to third PMOS mirror transistors PM1 and PM2 are not good under the condition that the voltage-controlled voltage VC is at a lower voltage, when the voltage-controlled voltage VC gradually rises, the drain terminals of the first to second PMOS isolation transistors PM11 and PM22 have a faster voltage than the source terminal voltage, and the drain terminals of the second to third PMOS mirror transistors PM1 and PM2 have a smaller voltage change, so as to still work in a saturation region, so as to sacrifice the working states of the first to second PMOS isolation transistors PM11 and PM22 to protect the states of the second to third PMOS mirror transistors PM1 and PM2, thereby enabling the third PMOS mirror transistor PM2 to better mirror the first PMOS mirror transistor PM 0.
In the second embodiment of the present invention, the operational amplifier AMP2 is introduced to the lower side of the charge pump, so that the voltages at the drain terminals of the first to second NMOS mirroring transistors NM1 and NM2 are approximately equal, thereby achieving the purpose of the consistent working state of the second NMOS mirroring transistor NM2 and the first NMOS mirroring transistor NM1, solving the problem of current mismatch of the second NMOS mirroring transistor NM2, and further reducing the mismatch by matching with the first to second PMOS isolation transistors PM11 and PM 22.
As shown IN fig. 6, the second embodiment is simulated, where VC is 0-0.8V, the current of the source current IP changes less than that IN fig. 2, and when VC is 0.2-0.8V, the current trend difference between the source current IP and the sink current IN of the present invention is smaller than that IN fig. 2, so as to improve the mismatch, as shown IN table 3, the maximum value of the mismatch of the improved circuit under all conditions is 3.1%, which is improved by 20% compared with the previous one.
Table 3 mismatch under all conditions for the second example after improvement (mismatch)
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A charge pump that reduces current mismatch, comprising:
the sink current module is used for generating sink current IN required by charging and discharging and generating reference current of source current IP under the control of reference current IBIAS;
the source current module is used for generating a source current IP required by charging and discharging under the control of the reference current generated by the sink current module;
the charge-discharge module is used for charging and discharging the oscillating capacitor C under the control of the logic circuit to obtain a variable voltage-controlled voltage VC so as to control the oscillation frequency;
the isolation module is used for isolating the sink current IN required by charging and discharging and the reference current for generating the source current IP from the charging and discharging module and the source current module respectively and then outputting the isolated sink current IN and the reference current to ensure that the working state of the sink current module is stable;
and the voltage stabilizing module is used for stabilizing the drain voltage of a mirror PMOS tube of the current-pulling module so as to assist in obtaining proportional current.
2. A charge pump for reducing current mismatch as recited in claim 1, wherein: the current sinking module comprises a first NMOS mirror image tube (NM0), a second NMOS mirror image tube (NM1) and a third NMOS mirror image tube (NM2), external bias current (IBAIS) is connected to the drain electrode of the first NMOS mirror image tube (NM0) and the grid electrodes of the first to third NMOS mirror image tubes (NM 0-NM 2), the source electrodes of the first to third NMOS mirror image tubes (NM 0-NM 2) are grounded, and the drain electrodes of the second NMOS mirror image tube (NM1) and the third NMOS mirror image tube (NM2) are respectively connected with the isolation module.
3. A charge pump for reducing current mismatch as recited in claim 2, wherein: the isolation module comprises a first NMOS isolation tube (NM11) and a second NMOS isolation tube (NM22), the drain electrode of the second NMOS mirror tube (NM1) is connected with the source electrode of the first NMOS isolation tube (NM11), and the drain electrode of the third NMOS mirror tube (NM2) is connected with the source electrode of the second NMOS isolation tube (NM 22); the bias voltage VBN is connected to the grids of the first NMOS isolation tube (NM11) and the second NMOS isolation tube (NM22), the drain electrode of the first NMOS isolation tube (NM11) is connected to the voltage stabilizing module and the current source module, and the drain electrode of the second NMOS isolation tube (NM22) is connected to the charging and discharging module.
4. A charge pump for reducing current mismatch as recited in claim 3, wherein: by providing a proper bias voltage for the bias Voltage (VBN) node, the first NMOS isolation tube (NM11) and the second NMOS isolation tube (NM22) are introduced to improve the condition that the states of the second NMOS mirror tube (NM1) and the third NMOS mirror tube (NM2) are poor under the condition that the voltage-controlled voltage VC is lower.
5. A charge pump for reducing current mismatch as recited in claim 4, wherein: when the voltage-controlled voltage VC is gradually increased, the drain terminal voltages of the first NMOS isolation tube (NM11) and the second NMOS isolation tube (NM22) are faster than the source terminal voltages, and the drain terminal voltages of the second NMOS mirror tube (NM1) and the third NMOS mirror tube (NM2) are less changed, so that the NMOS isolation tube still works in a saturation region, and the working states of the first NMOS isolation tube (NM11) and the second NMOS isolation tube (NM22) are sacrificed to protect the states of the second NMOS mirror tube (NM1) and the third NMOS mirror tube (NM 2).
6. A charge pump for reducing current mismatch as recited in claim 5, wherein: the voltage stabilizing module comprises an operational amplifier (AMP2), the non-inverting input end of the operational amplifier is connected with the drain electrode of the first NMOS isolation tube (NM11) and the source current module, the inverting input end of the operational amplifier is connected with the charge-discharge module, and the output end of the operational amplifier is connected with the source current module.
7. A charge pump for reducing current mismatch as recited in claim 6, wherein: the source current module comprises a first PMOS (P-channel metal oxide semiconductor) transistor (PM1) and a second PMOS transistor (PM2), the drain electrode of the first PMOS transistor (PM1) is connected with the drain electrode of the first NMOS isolation transistor (NM11) and the non-inverting input end of the operational amplifier (AMP2), and the drain electrode of the second PMOS transistor (PM2) is connected with the charge-discharge module; the grid electrodes of the first PMOS transistor (PM1) and the second PMOS transistor (PM2) are connected with the output end of the operational amplifier (AMP2), and the source electrodes of the first PMOS transistor (PM1) and the second PMOS transistor (PM2) are connected with a power supply.
8. A charge pump for reducing current mismatch as recited in claim 7, wherein: through the operational amplifier (AMP2), the voltages of the drain terminals of the first PMOS mirror tube (PM1) and the second PMOS mirror tube (PM2) are approximately equal, so that the aim of consistent working states of the second PMOS mirror tube (PM2) and the first PMOS mirror tube (PM1) is fulfilled.
9. A charge pump for reducing current mismatch as recited in claim 8, wherein: the charge-discharge module comprises first to fourth controllable switches (S1-S4) and an amplifier (AMP1), wherein the drain of the second NMOS isolation tube (NM22) is connected to one ends of the second controllable switch (S2) and the fourth controllable switch (S4), the other end of the second controllable switch (S2), one end of the first controllable switch (S1) and the non-inverting input end of the amplifier (AMP1) form a voltage-controlled voltage node VC, the inverting input end of the amplifier (AMP1) is connected with the output of the amplifier (AMP1) after being short-circuited, the other end of the fourth controllable switch (S4), the inverting input end of the operational amplifier (AMP2) and one end of the third controllable switch (S3), and the other end of the third controllable switch (S3) is connected with the other end of the first controllable switch (S1) and is connected to the drain of the PMOS of the first controllable switch (PM 1).
10. A charge pump that reduces current mismatch, comprising:
the current sinking module is used for generating a current sinking IN under the control of the reference current generated by the current sourcing module;
the source current module is used for generating a source current IP required by charging and discharging and generating a reference current of a sink current IN under the control of a reference current IBIAS;
the charge-discharge module is used for charging and discharging the oscillating capacitor C under the control of the logic circuit to obtain a variable voltage-controlled voltage VC so as to control the oscillation frequency;
the isolation module is used for isolating the source current IP required by charging and discharging and the reference current generating the sink current IN from the charging and discharging module and the sink current module respectively and then outputting the isolated source current IP and the reference current to ensure that the source current module is stable IN working state;
and the voltage stabilizing module is used for stabilizing the drain voltage of the mirror NMOS tube of the current sinking module so as to assist in obtaining proportional current.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Application publication date: 20210629 |