CN103166455A - Charge pump and phase-locked loop circuit - Google Patents
Charge pump and phase-locked loop circuit Download PDFInfo
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- CN103166455A CN103166455A CN2011104175590A CN201110417559A CN103166455A CN 103166455 A CN103166455 A CN 103166455A CN 2011104175590 A CN2011104175590 A CN 2011104175590A CN 201110417559 A CN201110417559 A CN 201110417559A CN 103166455 A CN103166455 A CN 103166455A
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Abstract
The invention relates to a charge pump and a phase-locked loop circuit. The charge pump comprises a first current source, a second current source, a first switch, a second switch, a third switch, a fourth switch and an operational amplifier. A first end of the first switch is connected with a first end of the third switch, and the first end of the first switch and the first end of the third switch are connected with the output end of the first current source. A second end of the first switch is connected with a first end of the second switch, and the second end of the first switch and the first end of the second switch are connected with the output end of the operational amplifier. A second end of the second switch is connected with a second end of the fourth switch, and the second end of the second switch and the second end of the fourth switch are connected with the output end of the second current source. A second end of the third switch is connected with a first end of the fourth switch, and the second end of the third switch and the first end of the fourth switch are connected with the obverse input end of the operational amplifier. The reverse input end of the operational amplifier is connected with the output end of the operational amplifier. The second current source is a self-adaptive and automatic biasing current source. An effective output voltage range of the charge pump is improved on the condition that output current is changeable or supply voltage is limited.
Description
Technical field
The present invention relates to circuit field, relate in particular to a kind of charge pump and phase-locked loop circuit.
Background technology
PLL(Phase-Locked Loop, phase-locked loop) be a kind of output phase to be compared with fixed phase, thereby obtain the system of stable output phase or output frequency.PLL is widely used in electronics and the communications field.
Extensively adopt charge pump phase lock loop in Modern Communication System.Fig. 1 is the structured flowchart of charge pump phase lock loop in prior art.As shown in Figure 1, charge pump phase lock loop of the prior art comprises phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider.Phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider are in sequential series, form loop.The output frequency of phase-locked loop can be expressed as f
out=Nf
ref, wherein N is the frequency dividing ratio of frequency divider, f
refInput reference frequency for phase frequency detector.Charge pump is between phase frequency detector and loop filter, is used for the output pulse signal of phase frequency detector is converted to the current impulse output of corresponding pulsewidth.Loop filter is converted to voltage with the output current of charge pump, and the filtering radio-frequency component, only DC component is exported to voltage controlled oscillator to control the output frequency of voltage controlled oscillator.
Divide from interface, be applied to charge pump in phase-locked loop and be divided into two kinds of single-ended charge pump and differential charge pumps.Generally, charge pump circuit is take single-ended structure as main, because when using single-ended charge pump, phase-locked loop does not need to increase extra loop filter, makes the phase-locked loop power consumption lower and can significantly reduce the area of whole phase-locked loop circuit.
Single-ended charge pump has various structures, and current steer type charge pump is exactly wherein a kind of.Current steer type charge pump belongs to the high speed charge pump, is usually used in the higher phase-locked loop frequency integrator of phase demodulation frequency, and it has the fireballing advantage of current switching.Fig. 2 is the structure chart of current steer type charge pump.As shown in Figure 2, this current steer type charge pump comprises current source I
UP, current source I
DN, switch UP, switch DN, switch Upn, switch DNn and operational amplifier.Wherein, switch UP, switch DN, switch Upn and switch DNn are used for controlling charge pump charging or discharge.Charge pump shown in Figure 2 has been introduced operational amplifier, can overcome the problem of distributing the charge pump output voltage shake that causes due to electric charge.When switch UP and switch DN turn-off, switch UPn and switch DNn conducting, the drain potential of switching tube is clamped down on fixing output voltage current potential by amplifier, is ground and can not draw high supply voltage or drag down, so the electric charge partition effect when having reduced switch opens.
Yet identical with other structure charge pump is, charge pump shown in Figure 2 also exists the contradictory problems of charging and discharging currents matching degree and effective output voltage range, namely in actual design, charge pump usually is difficult to accomplish simultaneously charging and discharging currents mismatch little (being that the charging and discharging currents matching degree is high) and effectively output voltage range is large.For example, accomplished reasonable charging and discharging currents matching degree, effective output voltage range of possible charge pump is just little.Otherwise if accomplished that effective output voltage range is large, the charging and discharging currents matching degree may be just low.That is to say, in existing charge pump, the charging and discharging currents mismatch that reduces charge pump exists choice with the effective output voltage range that improves charge pump, can not take into account simultaneously charging and discharging currents matching degree and effective output voltage range, when particularly or supply voltage variable when the output current that requires charge pump was limited, this contradiction was just further obvious.For example, in the charge pump design, there are two kinds of voltages, i.e. normal voltage and high voltage.For improving effective output voltage range of charge pump, generally adopt high voltage design.And when the supply voltage that requires charge pump is normal voltage, just effective output voltage range of charge pump can only be limited on certain level.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of charge pump and phase-locked loop circuit, can in the situation that output current is variable or supply voltage is limited, improve effective output voltage range of charge pump.
for solving the problems of the technologies described above, the present invention proposes a kind of charge pump, comprise the first current source, the second current source, the first switch (SW1), second switch (SW2), the 3rd switch (SW3), the 4th switch (SW4) and operational amplifier, the first end of described the first switch (SW1) is connected with the first end of described the 3rd switch (SW3) and also jointly connects the output of described the first current source, the second end of described the first switch (SW1) is connected with the first end of described second switch (SW2) and also jointly connects the output of described operational amplifier, the second end of described second switch (SW2) is connected with the second end of described the 4th switch (SW4) and also jointly connects the output of described the second current source, the second end of described the 3rd switch (SW3) is connected with the first end of described the 4th switch (SW4) and also jointly connects the input in the same way of described operational amplifier, the reverse input end of described operational amplifier is connected with the output of described operational amplifier, described the second current source is the self adaptation self-bias current source.
Further, above-mentioned charge pump also can have following characteristics, and described the second current source comprises variable resistor (R
V), the 5th NMOS pipe (M
5), the 6th NMOS pipe (M
6), the 7th NMOS pipe (M
7), the 8th NMOS pipe (M
8), the 9th NMOS pipe (M
9) and the tenth NMOS pipe (M
10), described variable resistor (R
V) the current input terminal of the first termination charge pump, described variable resistor (R
V) described the 5th NMOS pipe (M of the second termination
5) drain electrode; Described the 5th NMOS pipe (M
5) grid meet described variable resistor (R
V) first end, described the 5th NMOS pipe (M
5) source electrode meet described the 6th NMOS pipe (M
6) drain electrode; Described the 6th NMOS pipe (M
6) grid meet described variable resistor (R
V) the second end, described the 6th NMOS pipe (M
6) source ground; Described the 7th NMOS pipe (M
7) grid meet described the 5th NMOS pipe (M
5) grid, described the 7th NMOS pipe (M
7) drain electrode be the image current output, described the 7th NMOS pipe (M
7) source electrode meet described the 8th NMOS pipe (M
8) drain electrode; Described the 8th NMOS pipe (M
8) grid meet described the 6th NMOS pipe (M
6) grid, described the 8th NMOS pipe (M
8) source ground; Described the 9th NMOS pipe (M
9) drain electrode be the output of the second current source, described the 9th NMOS pipe (M
9) grid meet described the 7th NMOS pipe (M
7) grid, described the 9th NMOS pipe (M
9) source electrode meet described the tenth NMOS pipe (M
10) drain electrode; Described the tenth NMOS pipe (M
10) grid meet described the 8th NMOS pipe (M
8) grid, described the tenth NMOS pipe (M
10) source ground.
Further, above-mentioned charge pump also can have following characteristics, and described the first current source comprises a PMOS pipe (M
1), the 2nd PMOS pipe (M
2), the 3rd PMOS pipe (M
3) and the 4th PMOS pipe (M
4), a described PMOS pipe (M
1) drain electrode connect the input of described the first current source, a described PMOS pipe (M
1) source electrode meet described the 3rd PMOS pipe (M
3) drain electrode; Described the 3rd PMOS pipe (M
3) grid meet a described PMOS pipe (M
1) drain electrode, described the 3rd PMOS pipe (M
3) source electrode meet power supply Vdd; Described the 4th PMOS pipe (M
4) grid meet described the 3rd PMOS pipe (M
3) grid, described the 4th PMOS pipe (M
4) source electrode meet power supply Vdd, described the 4th PMOS pipe (M
4) drain electrode meet described the 2nd PMOS pipe (M
2) drain electrode; Described the 2nd PMOS pipe (M
2) grid meet a described PMOS pipe (M
1) grid, described the 2nd PMOS pipe (M
2) drain electrode be the output of the first current source.
Further, above-mentioned charge pump also can have following characteristics, also comprise N group cascade transistor array, N is natural number, wherein each group cascade transistor array comprises the first cascade PMOS pipe, the second cascade PMOS pipe, third level connection PMOS pipe, fourth stage connection PMOS pipe, level V connection NMOS pipe, the 6th cascade NMOS pipe, the 7th cascade NMOS pipe, the 8th cascade NMOS pipe, the 9th cascade NMOS pipe and the tenth cascade NMOS pipe, the grid of described the first cascade PMOS pipe and a described PMOS pipe (M
1) grid be connected, the drain electrode of described the first cascade PMOS pipe is managed (M with a described PMOS
1) drain electrode be connected, the source electrode of described the first cascade PMOS pipe is connected with the drain electrode of described third level connection PMOS pipe; The grid of described third level connection PMOS pipe and described the 3rd PMOS pipe (M
3) grid be connected, the source electrode of described third level connection PMOS pipe meets power supply Vdd; The grid of described the second cascade PMOS pipe and described the 2nd PMOS pipe (M
2) grid be connected, the drain electrode of described the second cascade PMOS pipe is managed (M with described the 2nd PMOS
2) drain electrode be connected, the source electrode of described the second cascade PMOS pipe is connected with the drain electrode of described fourth stage connection PMOS pipe; The grid of described fourth stage connection PMOS pipe and described the 4th PMOS pipe (M
4) grid be connected, the source electrode of described fourth stage connection PMOS pipe meets power supply Vdd; The grid of described level V connection NMOS pipe and described the 5th NMOS pipe (M
5) grid be connected, the drain electrode of described level V connection NMOS pipe is managed (M with described the 5th NMOS
5) drain electrode be connected, the source electrode of described level V connection NMOS pipe is connected with the drain electrode of described the 6th cascade NMOS pipe; The grid of described the 6th cascade NMOS pipe and described the 6th NMOS pipe (M
6) grid be connected, the source ground of described the 6th cascade NMOS pipe; The grid of described the 7th cascade NMOS pipe and described the 7th NMOS pipe (M
7) grid be connected, described the 7th cascade NMOS pipe drain electrode manage (M with described the 7th NMOS
7) drain electrode be connected, described the 7th cascade NMOS pipe source electrode be connected with the drain electrode of described the 8th cascade NMOS pipe; The grid of described the 8th cascade NMOS pipe and described the 8th NMOS pipe (M
8) grid be connected, the source ground of described the 8th cascade NMOS pipe; The grid of described the 9th cascade NMOS pipe and described the 9th NMOS pipe (M
9) grid be connected, the drain electrode of described the 9th cascade NMOS pipe is managed (M with described the 9th NMOS
9) drain electrode be connected, the source electrode of described the 9th cascade NMOS pipe is connected with the drain electrode of described the tenth cascade NMOS pipe; The grid of described the tenth cascade NMOS pipe and described the tenth NMOS pipe (M
10) grid be connected, the source ground of described the tenth cascade NMOS pipe.
Further, above-mentioned charge pump also can have following characteristics, also comprises N switch, and a described N switch is controlled respectively the opening and closing of described N group cascade transistor array.
Further, above-mentioned charge pump also can have following characteristics, and described the first current source also comprises the biasing automatic circuit.
Further, above-mentioned charge pump also can have following characteristics, and described biasing automatic circuit comprises operational amplifier, the described electric charge delivery side of pump of the input termination in the same way of described operational amplifier, and reverse input end connects reference voltage V
ref, the described PMOS pipe (M of output termination
1) grid.
for solving the problems of the technologies described above, the invention allows for a kind of phase-locked loop circuit, comprise phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider, wherein, described phase frequency detector, charge pump, loop filter, voltage controlled oscillator is in sequential series, described phase frequency detector connects the input of described phase-locked loop circuit, described voltage controlled oscillator connects described phase-locked loop circuit output, described frequency divider with the output frequency frequency division of described phase-locked loop circuit after the input phase frequency detector form loop, described charge pump comprises the first current source, the second current source, the first switch (SW1), second switch (SW2), the 3rd switch (SW3), the 4th switch (SW4) and operational amplifier, the first end of described the first switch (SW1) is connected with the first end of described the 3rd switch (SW3) and also jointly connects the output of described the first current source, the second end of described the first switch (SW1) is connected with the first end of described second switch (SW2) and also jointly connects the output of described operational amplifier, the second end of described second switch (SW2) is connected with the second end of described the 4th switch (SW4) and also jointly connects the output of described the second current source, the second end of described the 3rd switch (SW3) is connected with the first end of described the 4th switch (SW4) and also jointly connects the input in the same way of described operational amplifier, the reverse input end of described operational amplifier is connected with the output of described operational amplifier, the second current source of described charge pump is the self adaptation self-bias current source.
Further, above-mentioned phase-locked loop circuit also can have following characteristics, and the second current source of described charge pump comprises variable resistor (R
V), the 5th NMOS pipe (M
5), the 6th NMOS pipe (M
6), the 7th NMOS pipe (M
7), the 8th NMOS pipe (M
8), the 9th NMOS pipe (M
9) and the tenth NMOS pipe (M
10), described variable resistor (R
V) the current input terminal of the first termination charge pump, described variable resistor (R
V) described the 5th NMOS pipe (M of the second termination
5) drain electrode; Described the 5th NMOS pipe (M
5) grid meet described variable resistor (R
V) first end, described the 5th NMOS pipe (M
5) source electrode meet described the 6th NMOS pipe (M
6) drain electrode; Described the 6th NMOS pipe (M
6) grid meet described variable resistor (R
V) the second end, described the 6th NMOS pipe (M
6) source ground; Described the 7th NMOS pipe (M
7) grid meet described the 5th NMOS pipe (M
5) grid, described the 7th NMOS pipe (M
7) drain electrode be the image current output, described the 7th NMOS pipe (M
7) source electrode meet described the 8th NMOS pipe (M
8) drain electrode; Described the 8th NMOS pipe (M
8) grid meet described the 6th NMOS pipe (M
6) grid, described the 8th NMOS pipe (M
8) source ground; Described the 9th NMOS pipe (M
9) drain electrode be the output of the second current source, described the 9th NMOS pipe (M
9) grid meet described the 7th NMOS pipe (M
7) grid, described the 9th NMOS pipe (M
9) source electrode meet described the tenth NMOS pipe (M
10) drain electrode; Described the tenth NMOS pipe (M
10) grid meet described the 8th NMOS pipe (M
8) grid, described the tenth NMOS pipe (M
10) source ground.
Further, above-mentioned phase-locked loop circuit also can have following characteristics, and the first current source of described charge pump comprises a PMOS pipe (M
1), the 2nd PMOS pipe (M
2), the 3rd PMOS pipe (M
3) and the 4th PMOS pipe (M
4), a described PMOS pipe (M
1) drain electrode connect the input of described the first current source, a described PMOS pipe (M
1) source electrode meet described the 3rd PMOS pipe (M
3) drain electrode; Described the 3rd PMOS pipe (M
3) grid meet a described PMOS pipe (M
1) drain electrode, described the 3rd PMOS pipe (M
3) source electrode meet power supply Vdd; Described the 4th PMOS pipe (M
4) grid meet described the 3rd PMOS pipe (M
3) grid, described the 4th PMOS pipe (M
4) source electrode meet power supply Vdd, described the 4th PMOS pipe (M
4) drain electrode meet described the 2nd PMOS pipe (M
2) drain electrode; Described the 2nd PMOS pipe (M
2) grid meet a described PMOS pipe (M
1) grid, described the 2nd PMOS pipe (M
2) drain electrode be the output of the first current source.
Charge pump of the present invention can in the situation that output current is variable or supply voltage is limited, improve effective output voltage range of charge pump.Charge pump in phase-locked loop circuit of the present invention can improve effective output voltage range of charge pump in the situation that output current is variable or supply voltage is limited, has therefore enlarged the range of application of phase-locked loop circuit of the present invention.
Description of drawings
Fig. 1 is the structured flowchart of charge pump phase lock loop in prior art;
Fig. 2 is the structure chart of current steer type charge pump;
Fig. 3 is a kind of structure chart of charge pump in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, principle of the present invention and feature are described, example only is used for explaining the present invention, is not be used to limiting scope of the present invention.
As shown in Figure 3, in the present embodiment, charge pump comprises the first current source, the second current source, the first switch SW 1, second switch SW2, the 3rd switch SW 3, the 4th switch SW 4 and operational amplifier.The first end of the first switch SW 1 is connected with the first end of the 3rd switch SW 3 and also jointly connects the output of the first current source, the second end of the first switch SW 1 is connected with the first end of second switch SW2 and also jointly connects the output of operational amplifier, the second end of second switch SW2 is connected with the second end of the 4th switch SW 4 and also jointly connects the output of the second current source, the second end of the 3rd switch SW 3 is connected with the first end of the 4th switch SW 4 and also jointly connects the input in the same way of operational amplifier, and the reverse input end of operational amplifier is connected with the output of operational amplifier.Wherein, the second current source is the self adaptation self-bias current source.
As shown in Figure 3, in the present embodiment, the first current source comprises a PMOS pipe M
1, the 2nd PMOS pipe M
2, the 3rd PMOS pipe M
3With the 4th PMOS pipe M
4Its annexation is: a PMOS pipe M
1Drain electrode meet input (i.e. the 7th NMOS pipe M of the first current source
7Drain electrode), a PMOS pipe M
1Source electrode meet the 3rd PMOS pipe M
3Drain electrode; The 3rd PMOS pipe M
3Grid meet a PMOS pipe M
1Drain electrode, the 3rd PMOS pipe M
3Source electrode meet power supply Vdd; The 4th PMOS pipe M
4Grid meet the 3rd PMOS pipe M
3Grid, the 4th PMOS pipe M
4Source electrode meet power supply Vdd, the 4th PMOS pipe M
4Drain electrode meet the 2nd PMOS pipe M
2Drain electrode; The 2nd PMOS pipe M
2Grid meet a PMOS pipe M
1Grid, the 2nd PMOS pipe M
2Drain electrode be the output of the first current source.
As shown in Figure 3, in the present embodiment, the second current source comprises variable resistor R
V, the 5th NMOS pipe M
5, the 6th NMOS pipe M
6, the 7th NMOS pipe M
7, the 8th NMOS pipe M
8, the 9th NMOS pipe M
9With the tenth NMOS pipe M
10Its annexation is: variable resistor R
VThe current input terminal of the first termination charge pump, variable resistor R
VThe second termination the 5th NMOS pipe M
5Drain electrode; The 5th NMOS pipe M
5Grid meet variable resistor R
VFirst end, the 5th NMOS pipe M
5Source electrode meet the 6th NMOS pipe M
6Drain electrode; The 6th NMOS pipe M
6Grid meet variable resistor R
VThe second end, the 6th NMOS pipe M
6Source ground; The 7th NMOS pipe M
7Grid meet the 5th NMOS pipe M
5Grid, the 7th NMOS pipe M
7Drain electrode be the image current output, the 7th NMOS pipe M
7Source electrode meet the 8th NMOS pipe M
8Drain electrode; The 8th NMOS pipe M
8Grid meet the 6th NMOS pipe M
6Grid, the 8th NMOS pipe M
8Source ground; The 9th NMOS pipe M
9Drain electrode be the output of the second current source, the 9th NMOS pipe M
9Grid meet the 7th NMOS pipe M
7Grid, the 9th NMOS pipe M
9Source electrode meet the tenth NMOS pipe M
10Drain electrode; The tenth NMOS pipe M
10Grid meet the 8th NMOS pipe M
8Grid, the tenth NMOS pipe M
10Source ground.
The self adaptation self-bias current source is when input current changes, can regulate pressure drop on self-bias resistor by variable resistor, make the pressure drop on self-bias resistor constant as far as possible, guarantee that all metal-oxide-semiconductors all work in the saturation region, avoid causing the image current precision to reduce because metal-oxide-semiconductor enters linear zone, thereby can be applied to the variable occasion of input bias current, satisfy the application demand of wide input and output electric current.When the charge pump supply power voltage only is normal voltage, adopt the self adaptation self-bias current source in charge pump, can effectively improve effective output voltage range of charge pump, and output current is variable.
On the basis of circuit shown in Figure 3, charge pump can also comprise the cascade transistor array.The cascade transistor array refers to and transistor M
1~ M
10Transistor in parallel.Namely on the basis of circuit shown in Figure 3, charge pump can also comprise also N group cascade transistor array, and N is natural number.Wherein, each group cascade transistor array comprises the first cascade PMOS pipe, the second cascade PMOS pipe, third level connection PMOS pipe, fourth stage connection PMOS pipe, level V connection NMOS pipe, the 6th cascade NMOS pipe, the 7th cascade NMOS pipe, the 8th cascade NMOS pipe, the 9th cascade NMOS pipe and the tenth cascade NMOS pipe.The grid of the first cascade PMOS pipe and PMOS pipe M
1Grid be connected, the drain electrode of the first cascade PMOS pipe is managed M with a PMOS
1Drain electrode be connected, the source electrode of the first cascade PMOS pipe is connected with the drain electrode of third level connection PMOS pipe; The grid of third level connection PMOS pipe and the 3rd PMOS pipe M
3Grid be connected, the source electrode of third level connection PMOS pipe meets power supply Vdd; The grid of the second cascade PMOS pipe and the 2nd PMOS pipe M
2Grid be connected, the drain electrode of the second cascade PMOS pipe is managed M with the 2nd PMOS
2Drain electrode be connected, the source electrode of the second cascade PMOS pipe is connected with the drain electrode of fourth stage connection PMOS pipe; The grid of fourth stage connection PMOS pipe and the 4th PMOS pipe M
4Grid be connected, the source electrode of fourth stage connection PMOS pipe meets power supply Vdd; The grid of level V connection NMOS pipe and the 5th NMOS pipe M
5Grid be connected, the drain electrode of level V connection NMOS pipe is managed M with the 5th NMOS
5Drain electrode be connected, the source electrode of level V connection NMOS pipe is connected with the drain electrode of the 6th cascade NMOS pipe; The grid of the 6th cascade NMOS pipe and the 6th NMOS pipe M
6Grid be connected, the source ground of the 6th cascade NMOS pipe; The grid of the 7th cascade NMOS pipe and the 7th NMOS pipe M
7Grid be connected, the 7th cascade NMOS pipe drain electrode manage M with the 7th NMOS
7Drain electrode be connected, the 7th cascade NMOS pipe source electrode be connected with the drain electrode of the 8th cascade NMOS pipe; The grid of the 8th cascade NMOS pipe and the 8th NMOS pipe M
8Grid be connected, the source ground of the 8th cascade NMOS pipe; The grid of the 9th cascade NMOS pipe and the 9th NMOS pipe M
9Grid be connected, the drain electrode of the 9th cascade NMOS pipe is managed M with the 9th NMOS
9Drain electrode be connected, the source electrode of the 9th cascade NMOS pipe is connected with the drain electrode of the tenth cascade NMOS pipe; The grid of the tenth cascade NMOS pipe and the tenth NMOS pipe M
10Grid be connected, the source ground of the tenth cascade NMOS pipe.
Wherein, the group number of cascade transistor array can be determined according to the input current of charge pump.When charge pump has N group cascade transistor array, charge pump can also comprise N switch, this N switch is controlled respectively the opening and closing of above-mentioned N group cascade transistor array, and the opening and closing of each group cascade transistor are respectively by switch opens with close to realize.
In embodiment illustrated in fig. 3, the first current source also comprises the biasing automatic circuit.The biasing automatic circuit can have the multiple circuit of realizing.Realize circuit a kind of of biasing automatic circuit, the biasing automatic circuit comprises operational amplifier.When this biasing automatic circuit was put into charge pump shown in Figure 3, its annexation was: the output of inputting in the same way the termination charge pump of operational amplifier, reverse input end connects reference voltage V
ref, output termination the one PMOS pipe M
1Grid.
The biasing automatic circuit can be finely tuned the bias voltage of the first current source according to the output voltage of charge pump, can improve the effective output voltage range of charge pump when keeping the currents match degree.
In other embodiments of the invention, also can not comprise the biasing automatic circuit in charge pump.
The biasing automatic circuit can be according to the big or small trim transistors M of charge pump output voltage
1And transistor M
2Bias voltage.For example when the output voltage of charge pump was higher, the higher bias voltage of biasing automatic circuit output made transistor M
1With transistor M
2Still be in the saturation region, can improve effective output voltage range of charge pump when keeping the charging and discharging currents matching degree.
Charge pump of the present invention can in the situation that output current is variable or supply voltage is limited, improve effective output voltage range of charge pump.
The invention allows for a kind of phase-locked loop circuit.this phase-locked loop circuit comprises phase frequency detector, charge pump, loop filter, voltage controlled oscillator VCO and frequency divider, wherein, phase frequency detector, charge pump, loop filter, voltage controlled oscillator VCO is in sequential series, phase frequency detector connects the input of this phase-locked loop circuit, voltage controlled oscillator connects this phase-locked loop circuit output, frequency divider with the output frequency frequency division of this phase-locked loop circuit after the input phase frequency detector form loop (phase frequency detector in phase-locked loop circuit of the present invention, charge pump, loop filter, the annexation of voltage controlled oscillator VCO and frequency divider can be referring to Fig. 1).Wherein, the charge pump in this phase-locked loop circuit can be any one charge pump proposed by the invention, for example charge pump shown in Figure 3.this charge pump comprises the first current source, the second current source, the first switch SW 1, second switch SW2, the 3rd switch SW 3, the 4th switch SW 4 and operational amplifier, the first end of the first switch SW 1 is connected with the first end of the 3rd switch SW 3 and also jointly connects the output of the first current source, the second end of the first switch SW 1 is connected with the first end of second switch SW2 and also jointly connects the output of operational amplifier, the second end of second switch SW2 is connected with the second end of described the 4th switch SW 4 and also jointly connects the output of described the second current source, the second end of described the 3rd switch SW 3 is connected with the first end of described the 4th switch SW 4 and also jointly connects the input in the same way of operational amplifier, the reverse input end of operational amplifier is connected with the output of operational amplifier, wherein, the second current source of charge pump is the self adaptation self-bias current source.
As shown in Figure 3, wherein, in this phase-locked loop circuit, the second current source of charge pump can comprise variable resistor R
V, the 5th NMOS pipe M
5, the 6th NMOS pipe M
6, the 7th NMOS pipe M
7, the 8th NMOS pipe M
8, the 9th NMOS pipe M
9With the tenth NMOS pipe M
10, variable resistor R
VThe current input terminal of the first termination charge pump, variable resistor R
VThe second termination the 5th NMOS pipe M
5Drain electrode; The 5th NMOS pipe M
5Grid meet variable resistor R
VFirst end, the 5th NMOS pipe M
5Source electrode meet the 6th NMOS pipe M
6Drain electrode; The 6th NMOS pipe M
6Grid meet variable resistor R
VThe second end, the 6th NMOS pipe M
6Source ground; The 7th NMOS pipe M
7Grid meet the 5th NMOS pipe M
5Grid, the 7th NMOS pipe M
7Drain electrode be the image current output, the 7th NMOS pipe M
7Source electrode meet described the 8th NMOS pipe M
8Drain electrode; The 8th NMOS pipe M
8Grid meet the 6th NMOS pipe M
6Grid, the 8th NMOS pipe M
8Source ground; The 9th NMOS pipe M
9Drain electrode be the output of the second current source, the 9th NMOS pipe M
9Grid meet the 7th NMOS pipe M
7Grid, the 9th NMOS pipe M
9Source electrode meet the tenth NMOS pipe M
10Drain electrode; The tenth NMOS pipe M
10Grid meet the 8th NMOS pipe M
8Grid, the tenth NMOS pipe M
10Source ground.
As shown in Figure 3, wherein, in this phase-locked loop circuit, the first current source of charge pump can comprise a PMOS pipe M
1, the 2nd PMOS pipe M
2, the 3rd PMOS pipe M
3With the 4th PMOS pipe M
4, a PMOS pipe M
1Drain electrode connect the input of the first current source, a PMOS pipe M
1Source electrode meet the 3rd PMOS pipe M
3Drain electrode; The 3rd PMOS pipe M
3Grid meet a PMOS pipe M
1Drain electrode, the 3rd PMOS pipe M
3Source electrode meet power supply Vdd; The 4th PMOS pipe M
4Grid meet the 3rd PMOS pipe M
3Grid, the 4th PMOS pipe M
4Source electrode meet power supply Vdd, the 4th PMOS pipe M
4Drain electrode meet the 2nd PMOS pipe M
2Drain electrode; The 2nd PMOS pipe M
2Grid meet a PMOS pipe M
1Grid, the 2nd PMOS pipe M
2Drain electrode be the output of the first current source.
Charge pump in phase-locked loop circuit of the present invention can improve effective output voltage range of charge pump in the situation that output current is variable or supply voltage is limited, has therefore enlarged the range of application of phase-locked loop circuit of the present invention.
The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. charge pump, comprise the first current source, the second current source, the first switch (SW1), second switch (SW2), the 3rd switch (SW3), the 4th switch (SW4) and operational amplifier, the first end of described the first switch (SW1) is connected with the first end of described the 3rd switch (SW3) and also jointly connects the output of described the first current source, the second end of described the first switch (SW1) is connected with the first end of described second switch (SW2) and also jointly connects the output of described operational amplifier, the second end of described second switch (SW2) is connected with the second end of described the 4th switch (SW4) and also jointly connects the output of described the second current source, the second end of described the 3rd switch (SW3) is connected with the first end of described the 4th switch (SW4) and also jointly connects the input in the same way of described operational amplifier, the reverse input end of described operational amplifier is connected with the output of described operational amplifier, it is characterized in that, described the second current source is the self adaptation self-bias current source.
2. charge pump according to claim 1, is characterized in that, described the second current source comprises variable resistor (R
V), the 5th NMOS pipe (M
5), the 6th NMOS pipe (M
6), the 7th NMOS pipe (M
7), the 8th NMOS pipe (M
8), the 9th NMOS pipe (M
9) and the tenth NMOS pipe (M
10), described variable resistor (R
V) the current input terminal of the first termination charge pump, described variable resistor (R
V) described the 5th NMOS pipe (M of the second termination
5) drain electrode; Described the 5th NMOS pipe (M
5) grid meet described variable resistor (R
V) first end, described the 5th NMOS pipe (M
5) source electrode meet described the 6th NMOS pipe (M
6) drain electrode; Described the 6th NMOS pipe (M
6) grid meet described variable resistor (R
V) the second end, described the 6th NMOS pipe (M
6) source ground; Described the 7th NMOS pipe (M
7) grid meet described the 5th NMOS pipe (M
5) grid, described the 7th NMOS pipe (M
7) drain electrode be the image current output, described the 7th NMOS pipe (M
7) source electrode meet described the 8th NMOS pipe (M
8) drain electrode; Described the 8th NMOS pipe (M
8) grid meet described the 6th NMOS pipe (M
6) grid, described the 8th NMOS pipe (M
8) source ground; Described the 9th NMOS pipe (M
9) drain electrode be the output of the second current source, described the 9th NMOS pipe (M
9) grid meet described the 7th NMOS pipe (M
7) grid, described the 9th NMOS pipe (M
9) source electrode meet described the tenth NMOS pipe (M
10) drain electrode; Described the tenth NMOS pipe (M
10) grid meet described the 8th NMOS pipe (M
8) grid, described the tenth NMOS pipe (M
10) source ground.
3. charge pump according to claim 2, is characterized in that, described the first current source comprises a PMOS pipe (M
1), the 2nd PMOS pipe (M
2), the 3rd PMOS pipe (M
3) and the 4th PMOS pipe (M
4), a described PMOS pipe (M
1) drain electrode connect the input of described the first current source, a described PMOS pipe (M
1) source electrode meet described the 3rd PMOS pipe (M
3) drain electrode; Described the 3rd PMOS pipe (M
3) grid meet a described PMOS pipe (M
1) drain electrode, described the 3rd PMOS pipe (M
3) source electrode meet power supply Vdd; Described the 4th PMOS pipe (M
4) grid meet described the 3rd PMOS pipe (M
3) grid, described the 4th PMOS pipe (M
4) source electrode meet power supply Vdd, described the 4th PMOS pipe (M
4) drain electrode meet described the 2nd PMOS pipe (M
2) drain electrode; Described the 2nd PMOS pipe (M
2) grid meet a described PMOS pipe (M
1) grid, described the 2nd PMOS pipe (M
2) drain electrode be the output of the first current source.
4. according to claim 2 or 3 described charge pumps, it is characterized in that, also comprise N group cascade transistor array, N is natural number, wherein each group cascade transistor array comprises the first cascade PMOS pipe, the second cascade PMOS pipe, third level connection PMOS pipe, fourth stage connection PMOS pipe, level V connection NMOS pipe, the 6th cascade NMOS pipe, the 7th cascade NMOS pipe, the 8th cascade NMOS pipe, the 9th cascade NMOS pipe and the tenth cascade NMOS pipe, the grid of described the first cascade PMOS pipe and a described PMOS pipe (M
1) grid be connected, the drain electrode of described the first cascade PMOS pipe is managed (M with a described PMOS
1) drain electrode be connected, the source electrode of described the first cascade PMOS pipe is connected with the drain electrode of described third level connection PMOS pipe; The grid of described third level connection PMOS pipe and described the 3rd PMOS pipe (M
3) grid be connected, the source electrode of described third level connection PMOS pipe meets power supply Vdd; The grid of described the second cascade PMOS pipe and described the 2nd PMOS pipe (M
2) grid be connected, the drain electrode of described the second cascade PMOS pipe is managed (M with described the 2nd PMOS
2) drain electrode be connected, the source electrode of described the second cascade PMOS pipe is connected with the drain electrode of described fourth stage connection PMOS pipe; The grid of described fourth stage connection PMOS pipe and described the 4th PMOS pipe (M
4) grid be connected, the source electrode of described fourth stage connection PMOS pipe meets power supply Vdd; The grid of described level V connection NMOS pipe and described the 5th NMOS pipe (M
5) grid be connected, the drain electrode of described level V connection NMOS pipe is managed (M with described the 5th NMOS
5) drain electrode be connected, the source electrode of described level V connection NMOS pipe is connected with the drain electrode of described the 6th cascade NMOS pipe; The grid of described the 6th cascade NMOS pipe and described the 6th NMOS pipe (M
6) grid be connected, the source ground of described the 6th cascade NMOS pipe; The grid of described the 7th cascade NMOS pipe and described the 7th NMOS pipe (M
7) grid be connected, described the 7th cascade NMOS pipe drain electrode manage (M with described the 7th NMOS
7) drain electrode be connected, described the 7th cascade NMOS pipe source electrode be connected with the drain electrode of described the 8th cascade NMOS pipe; The grid of described the 8th cascade NMOS pipe and described the 8th NMOS pipe (M
8) grid be connected, the source ground of described the 8th cascade NMOS pipe; The grid of described the 9th cascade NMOS pipe and described the 9th NMOS pipe (M
9) grid be connected, the drain electrode of described the 9th cascade NMOS pipe is managed (M with described the 9th NMOS
9) drain electrode be connected, the source electrode of described the 9th cascade NMOS pipe is connected with the drain electrode of described the tenth cascade NMOS pipe; The grid of described the tenth cascade NMOS pipe and described the tenth NMOS pipe (M
10) grid be connected, the source ground of described the tenth cascade NMOS pipe.
5. charge pump according to claim 4, is characterized in that, also comprises N switch, and a described N switch is controlled respectively the opening and closing of described N group cascade transistor array.
6. charge pump according to claim 3, is characterized in that, described the first current source also comprises the biasing automatic circuit.
7. charge pump according to claim 6, is characterized in that, described biasing automatic circuit comprises operational amplifier, the described electric charge delivery side of pump of the input termination in the same way of described operational amplifier, and reverse input end connects reference voltage V
ref, the described PMOS pipe (M of output termination
1) grid.
8. phase-locked loop circuit, comprise phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider, wherein, described phase frequency detector, charge pump, loop filter, voltage controlled oscillator is in sequential series, described phase frequency detector connects the input of described phase-locked loop circuit, described voltage controlled oscillator connects described phase-locked loop circuit output, described frequency divider with the output frequency frequency division of described phase-locked loop circuit after the input phase frequency detector form loop, described charge pump comprises the first current source, the second current source, the first switch (SW1), second switch (SW2), the 3rd switch (SW3), the 4th switch (SW4) and operational amplifier, the first end of described the first switch (SW1) is connected with the first end of described the 3rd switch (SW3) and also jointly connects the output of described the first current source, the second end of described the first switch (SW1) is connected with the first end of described second switch (SW2) and also jointly connects the output of described operational amplifier, the second end of described second switch (SW2) is connected with the second end of described the 4th switch (SW4) and also jointly connects the output of described the second current source, the second end of described the 3rd switch (SW3) is connected with the first end of described the 4th switch (SW4) and also jointly connects the input in the same way of described operational amplifier, the reverse input end of described operational amplifier is connected with the output of described operational amplifier, it is characterized in that, the second current source of described charge pump is the self adaptation self-bias current source.
9. phase-locked loop circuit according to claim 8, is characterized in that, the second current source of described charge pump comprises variable resistor (R
V), the 5th NMOS pipe (M
5), the 6th NMOS pipe (M
6), the 7th NMOS pipe (M
7), the 8th NMOS pipe (M
8), the 9th NMOS pipe (M
9) and the tenth NMOS pipe (M
10), described variable resistor (R
V) the current input terminal of the first termination charge pump, described variable resistor (R
V) described the 5th NMOS pipe (M of the second termination
5) drain electrode; Described the 5th NMOS pipe (M
5) grid meet described variable resistor (R
V) first end, described the 5th NMOS pipe (M
5) source electrode meet described the 6th NMOS pipe (M
6) drain electrode; Described the 6th NMOS pipe (M
6) grid meet described variable resistor (R
V) the second end, described the 6th NMOS pipe (M
6) source ground; Described the 7th NMOS pipe (M
7) grid meet described the 5th NMOS pipe (M
5) grid, described the 7th NMOS pipe (M
7) drain electrode be the image current output, described the 7th NMOS pipe (M
7) source electrode meet described the 8th NMOS pipe (M
8) drain electrode; Described the 8th NMOS pipe (M
8) grid meet described the 6th NMOS pipe (M
6) grid, described the 8th NMOS pipe (M
8) source ground; Described the 9th NMOS pipe (M
9) drain electrode be the output of the second current source, described the 9th NMOS pipe (M
9) grid meet described the 7th NMOS pipe (M
7) grid, described the 9th NMOS pipe (M
9) source electrode meet described the tenth NMOS pipe (M
10) drain electrode; Described the tenth NMOS pipe (M
10) grid meet described the 8th NMOS pipe (M
8) grid, described the tenth NMOS pipe (M
10) source ground.
10. phase-locked loop circuit according to claim 9, is characterized in that, the first current source of described charge pump comprises a PMOS pipe (M
1), the 2nd PMOS pipe (M
2), the 3rd PMOS pipe (M
3) and the 4th PMOS pipe (M
4), a described PMOS pipe (M
1) drain electrode connect the input of described the first current source, a described PMOS pipe (M
1) source electrode meet described the 3rd PMOS pipe (M
3) drain electrode; Described the 3rd PMOS pipe (M
3) grid meet a described PMOS pipe (M
1) drain electrode, described the 3rd PMOS pipe (M
3) source electrode meet power supply Vdd; Described the 4th PMOS pipe (M
4) grid meet described the 3rd PMOS pipe (M
3) grid, described the 4th PMOS pipe (M
4) source electrode meet power supply Vdd, described the 4th PMOS pipe (M
4) drain electrode meet described the 2nd PMOS pipe (M
2) drain electrode; Described the 2nd PMOS pipe (M
2) grid meet a described PMOS pipe (M
1) grid, described the 2nd PMOS pipe (M
2) drain electrode be the output of the first current source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110417559.0A CN103166455B (en) | 2011-12-14 | Electric charge pump and phase-locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110417559.0A CN103166455B (en) | 2011-12-14 | Electric charge pump and phase-locked loop circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103166455A true CN103166455A (en) | 2013-06-19 |
| CN103166455B CN103166455B (en) | 2016-12-14 |
Family
ID=
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| CN111293876A (en) * | 2019-12-31 | 2020-06-16 | 广州思信电子科技有限公司 | Linear circuit of charge pump |
| CN111464182A (en) * | 2020-04-29 | 2020-07-28 | 四川玖越机器人科技有限公司 | Inspection robot |
| CN112910255A (en) * | 2021-01-29 | 2021-06-04 | 西安交通大学 | Charge pump circuit with low current mismatch |
| CN113054840A (en) * | 2021-03-30 | 2021-06-29 | 上海华力微电子有限公司 | Charge pump capable of reducing current mismatch |
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