CN113035066A

CN113035066A - Electronic device

Info

Publication number: CN113035066A
Application number: CN202110259996.8A
Authority: CN
Inventors: 王睦凯; 蔡艾茹; 黄国有; 洪仕馨; 徐雅玲; 王洸富
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-08-21
Filing date: 2021-03-10
Publication date: 2021-06-25
Anticipated expiration: 2041-03-10
Also published as: CN113035066B

Abstract

An electronic device comprises a substrate, a transverse signal line, a first longitudinal signal line, a second longitudinal signal line, a first insulating layer and a common electrode. The first longitudinal signal line intersects with the transverse signal lines and is connected with one of the transverse signal lines. The second longitudinal signal line is adjacent to and parallel to the first longitudinal signal line. The first insulating layer covers the first vertical signal line and the second vertical signal line. The first insulating layer is provided with a groove, wherein the groove extends along the first longitudinal signal line and the second longitudinal signal line, and the projection of the groove on the substrate is positioned between the projection of the first longitudinal signal line on the substrate and the projection of the second longitudinal signal line on the substrate. The common electrode covers the first insulating layer and the surface of the groove.

Description

Electronic device

Technical Field

The present disclosure relates to electronic devices, and particularly to an electronic device with a trench.

Background

With the progress of technology, large-sized panels are developed toward narrow-frame designs, and the circuit layout of various electronic devices is becoming more complicated. Coupling between many adjacent lines used to convey different types of signals tends to affect the quality of the signal conveyance, resulting in unexpected functionality being ultimately presented. Therefore, how to plan the circuit layout, reduce the width of the frame, reduce the requirement for low-resistance metal, and avoid the problems of insufficient charging due to the increase of resistance-capacitance loading (RC loading) has become an issue of concern for research and development personnel at present.

Disclosure of Invention

The invention provides an electronic device, which can meet the requirement of narrow frame design and reduce the coupling between lines so as to improve the quality of the electronic device.

At least one embodiment of the invention provides an electronic device, which includes a substrate, a plurality of transverse signal lines, a first longitudinal signal line, a second longitudinal signal line, a first insulating layer, and a common electrode. The plurality of transverse signal lines are arranged on the substrate. The first longitudinal signal line is configured on the substrate and is intersected with the plurality of transverse signal lines, and the first longitudinal signal line is connected with one of the plurality of transverse signal lines. The second longitudinal signal line is configured on the substrate and is parallel and adjacent to the first longitudinal signal line. The first insulating layer covers the first and second vertical signal lines, and has a trench (trench) extending along the first and second vertical signal lines. The projection of the groove on the substrate is positioned between the projection of the first longitudinal signal line on the substrate and the projection of the second longitudinal signal line on the substrate. The common electrode covers the first insulating layer, and the common electrode covers the surface of the groove.

In an embodiment of the invention, a distance between a sidewall of the trench and the first vertical signal line is 2.0 μm to 6.0 μm, and a distance between another sidewall of the trench and the second vertical signal line is 2.0 μm to 6.0 μm.

In an embodiment of the invention, the first insulating layer includes a lower insulating layer and an upper insulating layer, the lower insulating layer covers the first vertical signal line and the second vertical signal line, and the upper insulating layer is sandwiched between the lower insulating layer and the film layer where the common electrode is located.

In an embodiment of the invention, a depth of the trench corresponds to a film thickness of the upper insulating layer.

In an embodiment of the invention, the trench extends from the upper insulating layer to the lower insulating layer, and a depth of the trench is smaller than a film thickness of the lower insulating layer.

In an embodiment of the invention, a depth of the trench is smaller than a film thickness of the upper insulating layer.

In an embodiment of the invention, the electronic device further includes a second insulating layer. The second insulating layer is clamped between the film layer where the transverse signal line is located and the film layer where the first longitudinal signal line is located, and is provided with a groove corresponding to the groove. The common electrode is further formed in the groove of the second insulating layer.

In an embodiment of the invention, a depth of the groove is smaller than a film thickness of the second insulating layer.

In an embodiment of the invention, the groove of the second insulating layer exposes the substrate.

In an embodiment of the invention, the second insulating layer has a through hole and a conducting structure penetrating through the through hole, and the first vertical signal line is connected to one of the plurality of horizontal signal lines through the conducting structure.

In an embodiment of the invention, the electronic device further includes a plurality of pixel structures disposed on the substrate. One of the pixel structures is surrounded by two adjacent transverse signal lines and the first longitudinal signal line and comprises a pixel electrode and an active element, the active element is connected with the first longitudinal signal line through one of the transverse signal lines, the active element is connected with the second longitudinal signal line, and the first longitudinal signal line is positioned between the pixel structure and the groove.

In an embodiment of the invention, in a top view of the substrate, the first vertical signal lines and the horizontal signal lines overlap to have a pattern that bypasses the active devices.

In an embodiment of the invention, the first vertical signal line and the second vertical signal line have a meandering pattern parallel to each other.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a partial top view of an electronic device according to an embodiment of the invention.

Fig. 2A is a schematic diagram of a first embodiment of a cross section along the cross-sectional line a-a' in the electronic device of fig. 1.

Fig. 2B is a schematic diagram of a modification of the electronic device of fig. 2A.

Fig. 3 is a schematic view of a second embodiment of a cross section along the cross-sectional line a-a' in the electronic device of fig. 1.

Fig. 4 is a schematic view of a third embodiment of a cross section along the cross-sectional line a-a' in the electronic device of fig. 1.

Fig. 5 is a schematic view of a fourth embodiment of a cross section along the cross-sectional line a-a' in the electronic device of fig. 1.

Description of reference numerals:

10. 10A1, 10A2, 10B, 10C, 10D: electronic device

100: substrate

110: transverse signal line

120: first longitudinal signal line

130. 130a, 130 b: second longitudinal signal line

200: a first insulating layer

200a, 200 b: surface of

210. 210': a second insulating layer

212: lower insulating layer

214: upper insulating layer

300: a third insulating layer

400. 402, a step of: groove

AA: active region

COM, COM': common electrode

CS: conduction structure

L1, L2, L3, L4: distance between two adjacent plates

P: winding pattern

Pa1, Pa 2: transverse pattern

Pb: longitudinal pattern

PE, PE': pixel electrode

PX, PX1, PX 2: pixel structure

S1: first side

S2: second side

t1, t2, t3, t 4: film thickness

A TFT: active component

TR, TR1, TR 1', TR2, TR 3: groove

X: in the transverse direction

Y: longitudinal direction

Detailed Description

In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" or "overlapping" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" or "coupled" may mean that there are additional elements between the elements.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "lower" or "upper" may include both an orientation of above and below.

As used herein, "about," or "substantially" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about," or "substantially" may be selected based on optical properties, etch properties, or other properties, with a more acceptable range of deviation or standard deviation, and not all properties may be applied with one standard deviation.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1 is a schematic top view of a portion of an electronic device according to an embodiment of the invention; fig. 2A is a schematic diagram of a first embodiment of a cross section along the cross-sectional line a-a' in the electronic device of fig. 1. For convenience of explanation, the position of the insulating layer is omitted in fig. 1.

Referring to fig. 1, an electronic device 10 includes a substrate 100, a plurality of transverse signal lines 110, a first vertical signal line 120, a plurality of second vertical signal lines 130, a common electrode COM, and a plurality of pixel structures PX. The substrate 100 may have an active area AA and a peripheral area (not shown) outside the active area AA. In the embodiment, the material of the substrate 100 may include glass or other suitable materials, but the invention is not limited thereto.

The transverse signal line 110 is disposed on the substrate 100 and extends along the transverse direction X. The plurality of transverse signal lines 110 may be arranged along a longitudinal direction Y intersecting the transverse direction X. Therefore, the lateral direction and the longitudinal direction described in the following embodiments can be regarded as the lateral direction X and the longitudinal direction Y in fig. 1, respectively. In the present embodiment, the transverse signal line 110 may be a gate line.

The first vertical signal lines 120 are disposed on the substrate 100 and intersect the plurality of horizontal signal lines 110. In this embodiment, the first vertical signal line 120 can be used as a gate transmission line to connect with one of the horizontal signal lines 110. In some embodiments, the first vertical signal line 120 may be connected to the horizontal signal line 110 through a corresponding conducting structure CS, but the invention is not limited thereto.

The second vertical signal line 130 is disposed on the substrate 100 and parallel to the first vertical signal line 120. In the present embodiment, the second longitudinal signal line 130 is adjacent to the first longitudinal signal line 120 in the transverse direction X; in the longitudinal direction Y, the first longitudinal signal line 120 and the second longitudinal signal line 130 have, for example, a zigzag pattern parallel to each other, but the invention is not limited thereto. The second vertical signal line 130 may be a data line.

The plurality of pixel structures PX are disposed on the substrate 100 in an array arrangement. In other words, the pixel structures PX are arranged in an array along the transverse direction X and the longitudinal direction Y. In the present embodiment, the pixel structure PX is connected to one of the transverse signal lines 110 and one of the second longitudinal signal lines 130. In addition, the first longitudinal signal line 120 is not directly connected to the pixel structure PX.

In the present embodiment, one of the pixel structures PX1 is surrounded by two adjacent transverse signal lines 110 and the first longitudinal signal line 120. For example, the pixel structures PX arranged in a column along the transverse direction X are sandwiched between two transverse signal lines 110; the pixel structures PX arranged in a line along the longitudinal direction Y are sandwiched between the two second longitudinal signal lines 130; the first vertical signal line 120 is sandwiched between the pixel structure PX and the second vertical signal line 130. In some embodiments, the pixel structures PX1 and PX2 arranged in the same row along the longitudinal direction Y may be connected to the second longitudinal signal line 130a at the first side S1 and the second longitudinal signal line 130b at the opposite second side S2, respectively.

In this embodiment, each pixel structure PX may include an active device TFT and a pixel electrode PE connected to the active device TFT. Although the pixel electrode PE illustrated in fig. 1 does not overlap the first vertical signal line 120 when viewed in a plan view of the substrate 100, the pixel electrode PE may overlap the first vertical signal line 120 in other embodiments, and the invention is not limited thereto. In addition, as shown in fig. 1, the first vertical signal line 120 may have a wiring pattern P bypassing the active device TFT where it overlaps the horizontal signal line 110. For example, the winding pattern P may include a transverse portion pattern Pa1, a transverse portion pattern Pa2 and a longitudinal portion pattern Pb, as shown in fig. 1, the transverse portion pattern Pa1 crosses between the pixel electrode PE and the active device TFT of the pixel structure PX1 along the transverse direction X and is adjacent to the longitudinal portion pattern Pb, the longitudinal portion pattern Pb extends to the transverse portion pattern Pa2 along the longitudinal direction Y, and the transverse portion pattern Pa2 extends to the first side of the pixel structure PX2 along the pixel structure PX 2. The wiring pattern P may thus bypass the active device TFT in a manner along the side of the active device TFT. In addition, as shown in fig. 1, the conductive structure CS may be located at an intersection of the vertical portion pattern Pb and the horizontal portion pattern Pa2, but the invention is not limited thereto.

The active element TFT is connected to the first vertical signal line 120, for example, through one of the horizontal signal lines 110, and the active element TFT is connected to the second vertical signal line 130. For example, the active device TFT may be a transistor having a gate, a source and a drain, the gate being connected to one of the lateral signal lines 110, the source being connected to one of the second vertical signal lines 130, and the drain being connected to the pixel electrode PE. Accordingly, in some embodiments, the electronic device 100 may further include a driving circuit, and the driving circuit is located at one end of the first vertical signal line 120. The transverse signal line 110 can receive a corresponding signal through the first longitudinal signal line 120. Thus, the design of the narrow frame can be achieved without disposing the signal transmission lines or related circuits at the two ends of the transverse signal line 110 in the transverse direction X. The first vertical signal line 120 may transmit a signal from the driving circuit to the horizontal signal line 110, and the signal is input to the gate of the pixel structure PX in the same column through the horizontal signal line 110, thereby turning on or off the active device TFT of the pixel structure PX in the column. In addition, in order to avoid short circuit between the transverse signal line 110 and the second longitudinal signal line 130, the transverse signal line 110 and the second longitudinal signal line 130 may be formed of different layers, and one or more insulating layers may be interposed between the transverse signal line 110 and the second longitudinal signal line 130. In some embodiments, the first vertical signal line 120 and the second vertical signal line 130 may be located on the same film layer, and the horizontal signal line 110 may be located on a different film layer than the first vertical signal line 120 and the second vertical signal line 130. In some embodiments, in order to transmit a signal from the first vertical signal line 120 to the horizontal signal line 110, a conductive structure CS may be disposed between the corresponding first vertical signal line 120 and the horizontal signal line 110. In this way, the signal required by the gate can be transmitted from the first vertical signal line 120 to the horizontal signal line 110 through the conducting structure CS, and then transmitted from the horizontal signal line 110 to the gate. In some embodiments, other vertical signal lines (not shown) may be included in the electronic device 10, and the vertical signal lines may not be used for transmitting signals required by the horizontal signal lines 110, but may be input with dc potentials. For example, the vertical signal lines may not be connected to any of the horizontal signal lines 110, and may be applied to the implementation of touch control or other functions.

The common electrode COM covers, for example, the entire active area AA of the substrate 100. The common electrode COM may be a common electrode for connecting a panel or implementing a touch function. In some embodiments, in a case that the electronic device 10 further includes a touch signal line (TP trace), the common electrode COM may also include a plurality of common electrodes, and a gap exists between the plurality of common electrodes COM to expose the touch signal line, which may be applied to implement touch control or other functions. For example, the common electrodes COM may be spaced apart by about 2.0 μm to 8.0 μm with the touch signal line as a center.

Referring to fig. 1 and fig. 2A together, an electronic device 10a1 is an example of an implementation of the electronic device 10 shown in fig. 1, in which a trench TR1 shown in fig. 2A corresponds to the trench TR shown in fig. 1. It should be noted that the embodiment of the trench can be adjusted according to the design requirement, which will be described in detail later.

In the present embodiment, as shown in fig. 2A, the electronic device 10a1 may include a first insulating layer 200 and a second insulating layer 210. The first insulating layer 200 covers the substrate 100, and the second insulating layer 210 covers the first vertical signal line 120 and the second vertical signal line 130. In some embodiments, the transverse signal line 110 is located at a first conductor layer, and the first longitudinal signal line 120 and the second longitudinal signal line 130 are located at a second conductor layer above the first conductor layer. The first insulating layer 200 is, for example, sandwiched between a first conductor layer and a second conductor layer, and the second insulating layer 210 is, for example, sandwiched between the second conductor layer and a film layer where the common electrode COM is located.

The first insulating layer 200 may have a through hole and a conducting structure CS (as shown in fig. 1) penetrating through the through hole. Whereby the first vertical signal line 120 can be connected to one of the horizontal signal lines 110 through the conducting structure CS.

The second insulating layer 210 may have a single-layer or multi-layer structure. In the present embodiment, the second insulating layer 210 includes, for example, a lower insulating layer 212 and an upper insulating layer 214, wherein the lower insulating layer 212 covers the first vertical signal line 120 and the second vertical signal line 130, and the upper insulating layer 214 is sandwiched between the lower insulating layer 212 and the common electrode COM. In some embodiments, the first insulating layer 200 and the second insulating layer 210 may include an inorganic insulating material or an organic insulating material, wherein the inorganic insulating material includes silicon oxide, silicon nitride, silicon oxynitride, or the like, and the organic insulating material includes polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), Polyimide (PI), or the like, for example, the lower insulating layer 212 may be a passivation layer (passivation layer) of the inorganic insulating material, and the upper insulating layer 214 may be a planarization layer of the organic insulating material, but the invention is not limited thereto.

In the present embodiment, the second insulating layer 210 has a trench TR1, as shown in fig. 1, the trench TR1 extends along the first vertical signal line 120 and the second vertical signal line 130. Also, the projection of the trench TR1 on the substrate 100 is located between the projection of the first vertical signal line 120 on the substrate 100 and the projection of the second vertical signal line 130 on the substrate 100. In other words, the first longitudinal signal line 120 is located between the pixel structure PX and the trench TR 1. As shown in fig. 2A, the sidewall of the trench TR1 is separated from the side surface of the first longitudinal signal line 120 by a distance L1, for example, and the lower limit of the distance L1 is preferably 2.0 μm, and preferably 3.0 μm. The upper limit of the distance L1 is preferably 6.0. mu.m, and preferably 5.0. mu.m. In one embodiment, the trench TR1 is spaced apart from the first vertical signal line 120 by about 2.0 μm to about 6.0 μm, for example. The other side wall of the trench TR1 is, for example, spaced apart from the side surface of the second longitudinal signal line 130 by a distance L2, and the lower limit of the distance L2 is preferably 2.0 μm, preferably 3.0 μm. The upper limit of the distance L2 is preferably 6.0. mu.m, and preferably 5.0. mu.m. In one embodiment, the trench TR1 is spaced apart from the second vertical signal line 130 by about 2.0 μm to about 6.0 μm, for example.

In the present embodiment, the depth of the trench TR1 corresponds to, for example, the film thickness t1 of the upper insulating layer 214. In some embodiments, trench TR1 may extend from upper insulating layer 214 into lower insulating layer 212. For example, the depth of trench TR1 may be greater than the film thickness t1 of upper insulating layer 214 and less than the film thickness t2 of lower insulating layer 212.

The common electrode COM covers, for example, the surface of the trench TR 1. Therefore, it can be used to shield (shielding) the interference between the first vertical signal line 120 and the second vertical signal line 130, so as to reduce the adverse effect caused by the coupling between the lines. For example, the common electrode COM covers the surface of the trench TR1 and the trench TR1 is located between the first vertical signal line 120 and the second vertical signal line 130, so that the electric field generated by the first vertical signal line 120 is shielded and is not coupled to the second vertical signal line 130, thereby ensuring that the second vertical signal line 130 maintains a certain level of output voltage, and further improving the functions (such as image display, touch sensing, etc.) performed by the electronic device.

It should be noted that the first embodiment shown in fig. 2A is exemplified as follows: the film layer where the pixel electrode (such as the pixel electrode PE in fig. 1) is located on the film layer where the common electrode COM is located. In other words, in the manufacturing process of the electronic device, the electronic device 10a1 of the embodiment forms the common electrode COM and then forms the pixel electrode, but the invention is not limited thereto.

Fig. 2B is a schematic diagram of a modification of the electronic device of fig. 2A. It should be noted that the embodiment of fig. 2B follows the element numbers and partial contents of the embodiment of fig. 2A, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

The electronic device 10a2 of the present embodiment is different from the electronic device 10a1 of fig. 2A in that the film layer where the pixel electrodes are located and the film layer where the common electrode is located are different. More specifically, referring to fig. 2B, in the electronic device 10a2 of fig. 2B, a film layer where the pixel electrode PE 'is located between a film layer where the first vertical signal line 120 or the second vertical signal line 130 is located and a film layer where the common electrode COM' is located. In other words, in the manufacturing process of the electronic device, the electronic device 10a2 of the present embodiment forms the pixel electrode PE 'and then forms the common electrode COM'. On the other hand, in the electronic device 10a2 shown in fig. 2B, the pixel electrode PE 'overlaps the first vertical signal line 120 when viewed from the top of the substrate 100, but in other embodiments, the pixel electrode PE' may not overlap the first vertical signal line 120, and the invention is not limited thereto.

In the present embodiment, a third insulating layer 300 is provided between the pixel electrode PE 'and the common electrode COM'. The third insulating layer 300 and the common electrode COM 'sequentially cover the surface of the trench TR 1'. In other words, the third insulating layer 300 is interposed between the common electrode COM 'and the surface of the trench TR 1'. Thus, the shielding effect can be improved to reduce the interference between the first vertical signal line 120 and the second vertical signal line 130.

Fig. 3 is a schematic view of a second embodiment of a cross section along the cross-sectional line a-a' in the electronic device of fig. 1. It should be noted that the embodiment of fig. 3 follows the element numbers and partial contents of the embodiments of fig. 1 and fig. 2A, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein. The electronic device 10B of fig. 3 is an example of an implementation of the electronic device 10 of fig. 1, wherein the trench TR2 shown in fig. 3 corresponds to the trench TR of fig. 1.

Referring to fig. 3, the electronic device 10B of the present embodiment is different from the electronic device 10a1 of fig. 2A in that the depth of the trench TR2 of the electronic device 10B is smaller than the depth of the trench TR1 of the electronic device 10a 1. In the present embodiment, the depth of the trench TR2 is, for example, smaller than the film thickness t1 of the upper insulating layer 214. Thus, in addition to the shielding effect, the process steps can be omitted to reduce the manufacturing cost.

Fig. 4 is a schematic view of a third embodiment of a cross section along the cross-sectional line a-a' in the electronic device of fig. 1. It should be noted that the embodiment of fig. 4 follows the element numbers and partial contents of the embodiments of fig. 1 and fig. 2A, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein. The electronic device 10C of fig. 4 is an example of an implementation of the electronic device 10 of fig. 1, wherein the trench TR3 shown in fig. 4 corresponds to the trench TR of fig. 1.

Referring to fig. 4, a difference between the electronic device 10C of the present embodiment and the electronic device 10a1 of fig. 2A is that the second insulating layer 210' of the electronic device 10C is a single-layer structure, and in the present embodiment, the first insulating layer 200 further has a groove 400 corresponding to the trench TR 3. In detail, in the present embodiment, the trench TR3 of the second insulating layer 210 ' penetrates through the thickness direction of the second insulating layer 210 ', and the groove 400 of the first insulating layer 200 completely overlaps with the trench TR3 of the second insulating layer 210 ' in the top view direction of the electronic device 10C, so that the groove 400 of the first insulating layer 200 and the trench TR3 of the second insulating layer 210 ' together form a receiving space spanning the second insulating layer 210 ' and the first insulating layer 200, and the common electrode COM is formed in the receiving space formed by the trench TR3 and the groove 400 together. In the present embodiment, the second insulating layer 210' may be an oxide layer. The material of the second insulating layer 210' may use the same material as the lower insulating layer 212 in fig. 2A, but the present invention is not limited thereto.

In the present embodiment, the groove 400 may have the same shape as the trench TR3 as viewed in a top view of the substrate 100. For example, the groove 400 may extend along the first vertical signal line 120 and the second vertical signal line 130, and the width of the groove 400 in the transverse direction X may be equivalent to the width of the trench TR3 in the transverse direction X, but the invention is not limited thereto. The sidewall of the groove 400 is spaced apart from the side of the first longitudinal signal line 120 by a distance L3, for example, and the lower limit of the distance L3 is preferably 2.0 μm, preferably 3.0 μm. The upper limit of the distance L3 is preferably 6.0. mu.m, and preferably 5.0. mu.m. In one embodiment, the groove 400 is spaced apart from the first longitudinal signal line 120 by about 2.0 μm to about 6.0 μm, for example. The other sidewall of the groove 400 is spaced apart from the side surface of the second longitudinal signal line 130 by, for example, a distance L4, and the lower limit of the distance L4 is preferably 2.0 μm, and preferably 3.0 μm. The upper limit of the distance L4 is preferably 6.0. mu.m, and preferably 5.0. mu.m. In one embodiment, the groove 400 is spaced apart from the second longitudinal signal line 130 by about 2.0 μm to about 6.0 μm, for example.

In the present embodiment, the depth of the trench TR3 is, for example, equal to the film thickness t3 of the second insulating layer 210', and the depth of the groove 400 is, for example, smaller than the film thickness t4 of the first insulating layer 200. In other words, the bottom surface of the groove 400 is between the surface 200a and the surface 200b of the first insulating layer 200. Since the first vertical signal line 120 and the second vertical signal line 130 cover the surface 200a of the first insulating layer 200, the common electrode COM can be substantially located between the first vertical signal line 120 and the second vertical signal line 130 by covering the surface of the trench TR3 and the surface of the groove 400. Therefore, the shielding effect of the interference between the first vertical signal line 120 and the second vertical signal line 130 can be ensured, and the functions performed by the electronic device can be further improved.

Fig. 5 is a schematic view of a fourth embodiment of a cross section along the cross-sectional line a-a' in the electronic device of fig. 1. It should be noted that the embodiment of fig. 5 uses the element numbers and part of the contents of the embodiments of fig. 1 and 4, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein. The electronic device 10D of fig. 5 is an example of an embodiment of the electronic device 10 of fig. 1, wherein the trench TR3 shown in fig. 5 corresponds to the trench TR of fig. 1.

Referring to fig. 5, a difference between the electronic device 10D of the present embodiment and the electronic device 10C of fig. 4 is that the depth of the groove 402 of the electronic device 10D is greater than the depth of the groove 400 of the electronic device 10C. In the present embodiment, the groove 402 of the first insulating layer 200 exposes the substrate 100, for example. For example, the depth of the groove 402 corresponds to the film thickness t4 of the first insulating layer 200. Thus, the common electrode COM covers the surface of the trench TR3 and the surface of the groove 402 to completely block the interference between the first vertical signal line 120 and the second vertical signal line 130, so as to further improve the shielding effect.

In summary, the electronic device of the present invention can achieve the requirement of narrow frame design by disposing the first vertical signal line. In addition, the groove is arranged between the first vertical signal line and the second vertical signal line, and the common electrode covers the surface of the groove, so that the common electrode can be used for shielding the interference among a plurality of signal lines, and the problems of adverse effects and the like caused by the coupling among lines are avoided. In addition, the signal line can be ensured to maintain a certain level of output voltage, and the functions executed by the electronic device are further improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. An electronic device, comprising:

a substrate;

a plurality of transverse signal lines disposed on the substrate;

the first longitudinal signal line is configured on the substrate and is intersected with the plurality of transverse signal lines, and the first longitudinal signal line is connected with one of the plurality of transverse signal lines;

a second longitudinal signal line disposed on the substrate, parallel to and adjacent to the first longitudinal signal line;

a first insulating layer covering the first and second longitudinal signal lines, the first insulating layer having a groove, wherein the groove extends along the first and second longitudinal signal lines, and a projection of the groove on the substrate is located between a projection of the first longitudinal signal line on the substrate and a projection of the second longitudinal signal line on the substrate; and

and the common electrode covers the first insulating layer, and covers the surface of the groove.

2. The electronic device according to claim 1, wherein a sidewall of the trench is spaced from the first vertical signal line by 2.0 μm to 6.0 μm, and another sidewall of the trench is spaced from the second vertical signal line by 2.0 μm to 6.0 μm.

3. The electronic device according to claim 1 or claim 2, wherein the first insulating layer includes a lower insulating layer and an upper insulating layer, the lower insulating layer covers the first vertical signal line and the second vertical signal line, and the upper insulating layer is interposed between the lower insulating layer and a film layer where the common electrode is located.

4. The electronic device according to claim 3, wherein a depth of the trench corresponds to a film thickness of the upper insulating layer.

5. The electronic device of claim 4, wherein the trench extends from the upper insulating layer into the lower insulating layer, and a depth of the trench is less than a film thickness of the lower insulating layer.

6. The electronic device of claim 3, wherein a depth of the trench is less than a film thickness of the upper insulating layer.

7. The electronic device of claim 1 or claim 2, further comprising:

and the second insulating layer is clamped between a film layer where the transverse signal line is located and a film layer where the first longitudinal signal line is located, the second insulating layer is provided with a groove corresponding to the groove, and the common electrode is further formed in the groove of the second insulating layer.

8. The electronic device according to claim 7, wherein a depth of the groove is smaller than a film thickness of the second insulating layer.

9. The electronic device of claim 7, wherein the recess of the second insulating layer exposes the substrate.

10. The electronic device according to claim 7, wherein the second insulating layer has a via and a conductive structure passing through the via, and the first vertical signal line is connected to one of the plurality of the horizontal signal lines via the conductive structure.

11. The electronic device of claim 1 or claim 2, further comprising:

a plurality of pixel structures disposed on the substrate, wherein one of the pixel structures is surrounded by two adjacent ones of the plurality of transverse signal lines and the first longitudinal signal line and includes a pixel electrode and an active device, the active device is connected to the first longitudinal signal line through one of the plurality of transverse signal lines, the active device is connected to the second longitudinal signal line, and the first longitudinal signal line is located between the pixel structure and the trench.

12. The electronic device according to claim 11, wherein the first longitudinal signal line has a pattern that bypasses the active element where it overlaps with the transverse signal line in a top view of the substrate.

13. The electronic device according to claim 1 or claim 2, wherein the first longitudinal signal line and the second longitudinal signal line have meandering patterns parallel to each other.