CN104181733A - Display device and transistor array substrate thereof - Google Patents

Display device and transistor array substrate thereof Download PDF

Info

Publication number
CN104181733A
CN104181733A CN201310188276.2A CN201310188276A CN104181733A CN 104181733 A CN104181733 A CN 104181733A CN 201310188276 A CN201310188276 A CN 201310188276A CN 104181733 A CN104181733 A CN 104181733A
Authority
CN
China
Prior art keywords
edge
pixel
transistor
array substrate
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310188276.2A
Other languages
Chinese (zh)
Inventor
徐毓伦
杨舜臣
李宜锦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innolux Corp
Original Assignee
Innolux Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innolux Display Corp filed Critical Innolux Display Corp
Priority to CN201310188276.2A priority Critical patent/CN104181733A/en
Publication of CN104181733A publication Critical patent/CN104181733A/en
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention discloses a display device and a transistor array substrate thereof. The transistor array base plate comprises a substrate, multiple signal lines, multiple transistors, an insulating layer, multiple pixel electrodes and a common electrode, wherein the signal lines are arranged on the substrate and are mutually staggered; the transistors are arranged on the substrate and are electrically connected with the signal lines; the insulating layer covers the signal lines and the transistors; the pixel electrodes are formed on the insulating layer and are electrically connected with the transistors; each pixel electrode is provided with multiple pixel edges which are mutually opposite; the common electrode is arranged under the insulating layer, and multiple grooves are formed in the common electrode; each groove is located under one of the pixel edges and is provided with a first edge; the first edges stretch along the adjacent pixel edges and are not covered by the pixel electrodes.

Description

Display device and transistor (TFT) array substrate thereof
Technical field
The present invention relates to a kind of display device, refer to especially a kind of liquid crystal indicator and transistor (TFT) array substrate thereof.
Background technology
Current wide viewing angle (wider viewing angle) display technique has developed the display that utilizes horizontal component of electric field (horizontal electric field) to drive liquid crystal molecule, it is for example that fringe field switches (Fringe Field Switching, FFS) display and transverse electric field effect (In-Plane-Switching, IPS) display.
Specifically, such display has a plurality of pixel electrodes, and these pixel electrodes can produce above-mentioned horizontal component of electric field.Utilization can be controlled liquid crystal molecule at the deflection amplitude being parallel in the plane of substrate to the change of horizontal component of electric field intensity, so that the pixel of display demonstrates different GTGs.To this, how the manufacturing plant of many liquid crystal display research improves the intensity of above-mentioned horizontal component of electric field, to strengthen the amplitude that liquid crystal molecule can deflection, thereby improves the liquid crystal efficiency of display.
Summary of the invention
The invention provides a kind of transistor (TFT) array substrate, its common electrode has many grooves, the intensity of electric field and these grooves can be improved the standard.
The invention provides a kind of display device, it comprises above-mentioned transistor (TFT) array substrate.
One embodiment of the invention provide a kind of transistor (TFT) array substrate, comprise substrate, many signal line, a plurality of transistor, insulation course, a plurality of pixel electrode and common electrode.Substrate has surface.Many signal line configurations from the teeth outwards.Each signal line has a signal wire view field from the teeth outwards.A plurality of transistor arrangement from the teeth outwards, and are electrically connected these signal wires.Insulation course is configured on these signal wires and these transistors.A plurality of pixel electrodes are formed on insulation course, and are electrically connected these transistors.The periphery of each pixel electrode has a plurality of pixel edges respect to one another.Each pixel electrode has a pixel projection region from the teeth outwards.Common electrode is configured under insulation course, and has a plurality of grooves.These grooves one of them be positioned at one of them pixel edge under, and groove has one first edge.The first edge extends along pixel edge adjacent thereto, and has from the teeth outwards a projected segment.Projected segment is between the pixel projection region being adjacent and signal wire view field.
Another embodiment of the present invention provides a kind of display device, and it comprises display panels, backlight module and circuit board assemblies.Display panels comprises above-mentioned transistor (TFT) array substrate, subtend substrate and liquid crystal layer, and wherein liquid crystal layer is configured between transistor (TFT) array substrate and subtend substrate.Backlight module is electrically connected display panels, and circuit board assemblies drives display panels to show image frame.
Based on above-mentioned, because groove position is under the wherein pixel edge of pixel electrode, and the first edge extends along pixel edge adjacent thereto, add that the projected segment of the first edge on substrate surface is between the pixel projection region being adjacent and signal wire view field, therefore above-mentioned groove can improve the intensity of the horizontal component of electric field that pixel electrode produces, to increase the amplitude that liquid crystal molecule can deflection.
In order further to understand the present invention, reach technology, method and the effect that set object is taked, refer to following relevant detailed description of the present invention, graphic, believe object of the present invention, feature and feature, when being goed deep into thus and concrete understanding, yet appended graphic and annex only provide with reference to and explanation use, be not used for to the present invention's limitr in addition.
Accompanying drawing explanation
Figure 1A is the wiring schematic diagram of the transistor (TFT) array substrate of one embodiment of the invention.
Figure 1B is the diagrammatic cross-section that in Figure 1A, I-I section along the line illustrates.
Fig. 1 C is the diagrammatic cross-section that in Figure 1A, II-II section along the line illustrates.
Fig. 2 A is the wiring schematic diagram of the transistor (TFT) array substrate of another embodiment of the present invention.
Fig. 2 B is the diagrammatic cross-section that in Fig. 2 A, III-III section along the line illustrates.
Fig. 3 is the wiring schematic diagram of the transistor (TFT) array substrate of another embodiment of the present invention.
Fig. 4 A is the schematic perspective view of the display device of one embodiment of the invention.
Fig. 4 B is the decomposing schematic representation of the display device in Fig. 4 A.
Fig. 4 C is the diagrammatic cross-section of display panels in Fig. 4 B.
[symbol description]
100,200,300,422: transistor (TFT) array substrate
110: substrate
120d, 120s: signal wire
130: transistor
130c: channel layer
130d: drain electrode
130g: grid
130s: source electrode
140,240,340: common electrode
151,152: insulation course
160,360: pixel electrode
160e, 360e: pixel edge
160s, 360s: slit
170: gate insulator
242: electrode strip
400: display device
410: assemble case
412,414: housing unit
420: display panels
426: liquid crystal layer
430: circuit board assemblies
432: rigid wiring board
434: bendable wiring board
440: backlight module
424: subtend substrate
E11, E21, E31: the first edge
E22, E22, E32: the second edge
H: contact hole
H1: opening
L1, L2: distance
P1: pixel region
S1, S2, S3: groove
Embodiment
Figure 1A is the wiring schematic diagram of the transistor (TFT) array substrate of one embodiment of the invention, and Figure 1B is the diagrammatic cross-section that in Figure 1A, I-I section along the line illustrates.Refer to Figure 1A and Figure 1B, the transistor (TFT) array substrate 100 of the present embodiment comprises substrate 110, many signal line 120d and 120s, a plurality of transistor 130, common electrode 140, insulation course 151 and a plurality of pixel electrode 160.Substrate 110 is transparent panel, and it is for example glass plate or transparent plastic sheet (for example acrylic plate), and has surface 112, and these signal wires 120d and 120s and these transistors 130 are all configured on surface 112.Therefore, each signal line 120d and 120s have signal wire view field, its shape and scope signal wire 120d and 120s as shown in Figure 1A on surface 112.
These signal wires 120d and 120s are electrically connected these transistors 130.Particularly, these signal wires 120d can be many data lines (data line) arranged side by side each other, and these signal wires 120s can be many sweep traces (scan line) arranged side by side each other.These signal wires 120d and 120s are interlaced with each other, to form a plurality of pixel region P1.These transistors 130 are respectively formed in the P1 of these pixel regions, and each transistor 130 can be all field-effect transistor (Field-Effect Transistor, FET).So, each transistor 130 has channel layer (channel) 130c, grid (gate) 130g, source electrode (source) 130s and drain electrode (drain) 130d, wherein these signal wires 120s(is sweep trace) connect respectively these grids 130g, and these signal wires 120d(is data line) connect respectively these source electrodes.So, signal wire 120d and 120s can be electrically connected transistor 130.
Insulation course 151 is configured on these signal wires 120d, 120s and these transistors 130.Transistor (TFT) array substrate 100 can also comprise another layer insulating 152, and wherein insulation course 152 covers these signal wires 120d, 120s and these transistors 130, and position is between insulation course 151 and substrate 110.Insulation course 152 covers signal wire 120d, 120s and transistor 130, and insulation course 151 covers insulation course 152, as shown in Figure 1B.In addition, transistor (TFT) array substrate 100 can also comprise that gate insulator 170(refers to Figure 1B).Gate insulator 170 is formed on substrate 110, and covered substrate 110, signal wire 120s with gate pole 130g.Gate insulator 170 can separate grid 130g and channel layer 130C, to produce grid capacitance effect (gate capacitive effect), makes transistor 130 be had the function of switch.
These pixel electrodes 160 are formed on insulation course 151, and are electrically connected these transistors 130.Specifically, a plurality of contact holes (contact window) H(is only presented in Figure 1B, and Figure 1B only illustrates one) be formed in insulation course 151 and 152.Contact hole H runs through insulation course 151 to form with insulation course 152, and position is directly over these drain electrodes 130d.Pixel electrode 160 extends to respectively in contact hole H from the upper surface of insulation course 151, thereby connects the drain electrode 130d of transistor 130.
Because signal wire 120s(is sweep trace) connection grid 130g, signal wire 120d(is data line) connection source electrode, and pixel electrode 160 connects drain electrode 130d, therefore these signal wires 120s can open and close these transistors 130, thereby control signal wire 120d input pixel voltage is to pixel electrode 160, so that pixel electrode 160 can drive liquid crystal deflecting element.In addition, each pixel electrode 160 has a plurality of slit 160s arranged side by side each other, and the bearing of trend of these slits 160s is mutually the same.
Common electrode 140 can provide common voltage (common voltage), and is configured in insulation course 151 times, and wherein common electrode 140 can be interposed between insulation course 151 and 152.Pixel electrode 160 passes common electrode 140 from contact hole H, but does not contact with common electrode 140, so pixel electrode 160 is electrically insulated with common electrode 140.In addition, common electrode 140 is overlapping with these pixel electrodes 160, and the distribution range of common electrode 140 contains these slits 160s, and these slits 160s occupied region on substrate 110 is contained in common electrode 140 occupied region on substrate 110.
When pixel voltage inputs to pixel electrode 160, the common voltage that utilizes these slits 160s and common electrode 140 to provide, pixel electrode 160 can produce horizontal component of electric field, so that liquid crystal molecule can be parallel to the plane upper deflecting of substrate 110.So, transistor (TFT) array substrate 100 can be used to manufacture fringe field switching display or transverse electric Field Effect Display.In addition, should be noted that, in the embodiment shown in Figure 1A, slit 160s can extend along signal wire 120d, but in other embodiments, slit 160s also can extend along signal wire 120s.
Fig. 1 C is the diagrammatic cross-section that in Figure 1A, II-II section along the line illustrates.Refer to Figure 1A and Fig. 1 C, each pixel electrode 160 has pixel projection region on surface 112, its shape and scope pixel electrode 160 as shown in Figure 1A, and the periphery of each pixel electrode 160 has a plurality of pixel edge 160e respect to one another.These pixel edges 160e all extends towards same direction, and wherein slit 160s extends along pixel edge 160e, pixel edge 160e and slit 160s the two move towards identical.In addition,, in the embodiment of Figure 1A, these pixel edges 160e can also extend along these signal wires 120d.But, in other embodiments, when slit 160s extends along signal wire 120s, pixel edge 160e also can extend along signal wire 120s.
Common electrode 140 has a plurality of groove S1, and these grooves S1 one of them be positioned at a pixel edge 160e wherein under, and hidden by pixel electrode 160 is local, groove S1 is partly overlapping with pixel electrode 160.Specifically, groove S1 has the first edge E11 and the second edge E12, and wherein the second E12 position, edge is on the opposite of the first edge E11.From Figure 1A and Fig. 1 C, the first edge E11 extends along pixel edge 160e adjacent thereto, and be parallel to this contiguous pixel edge 160e, wherein these first edges E11 is not hidden by these pixel electrodes 160, but these second edges E12 is hidden by these pixel electrodes 160.
Particularly, the first edge E11 and the second edge E12 have separately projected segment on surface 112, wherein the projected segment of the first edge E11 is positioned between the view field (signal wire 120d as shown in Figure 1A) of the pixel projection region (pixel electrode 160 as shown in Figure 1A) that is adjacent and signal wire 120d, wherein the projected segment of the first edge E11 is positioned at outside the pixel projection region being adjacent, the pixel projection region overlapping that the projected segment of the second edge E12 is adjacent.
Hold above-mentioned, in same groove S1, pixel edge 160e can position between the first edge E11 and the second edge E12, the distance L between the distance L 2 between the first edge E11 and pixel edge 160e and the second edge E12 and pixel edge 160e 1 the two neither can equal zero.In addition, can have one or two groove S1 in a pixel region P1, and these grooves S1 is staggered with these signal wires 120d, 120s, the complete position of groove S1 is in the P1 of pixel region.In addition, in same pixel region P1, slit 160s and groove S1 are not overlapping, groove S1 not can position under slit 160s.
Because having these, common electrode 140 is positioned at the groove S1 under pixel edge 160e, and each groove S1 has along pixel edge 160e and extends, and the first edge E11 not hidden by pixel electrode 160, therefore in same groove S1, between pixel edge 160e and the first edge E11, can produce the electric field with stronger horizontal component.So, these grooves S1 can improve the intensity of the horizontal component of electric field that pixel electrode 160 produces, and to increase the amplitude that liquid crystal molecule can deflection, thereby improves the liquid crystal efficiency of display.
It is worth mentioning that, in the present embodiment, common electrode 140 can be overlapping with these signal wires 120d, 120s and transistor 130, and common electrode 140 can also comprehensively cover these signal wires 120d.So, when transistor (TFT) array substrate 100 running, common electrode 140 can be used as electro-magnetic screen layer, to reduce signal wire 120d and the 120s interference to pixel electrode 160.
Fig. 2 A is the wiring schematic diagram of the transistor (TFT) array substrate of another embodiment of the present invention, and Fig. 2 B is the diagrammatic cross-section that in Fig. 2 A, III-III section along the line illustrates.Refer to Fig. 2 A and Fig. 2 B, transistor (TFT) array substrate 200 and aforementioned transistor (TFT) array substrate 100 the two structural similarity of the present embodiment, effect is identical haply, and therefore following article transistor (TFT) array substrate 200 is different from the difference characteristic of transistor (TFT) array substrate 100.As for the two identical feature, be no longer described in detail.
Transistor (TFT) array substrate 200 comprises common electrode 240, and common electrode 240 also has many groove S2 arranged side by side each other.But, be different from the common electrode 140 in previous embodiment, these grooves S2 and these signal wires 120s are staggered.That is to say, groove S2 can extend to one other pixel district P1 from one of them pixel region P1, and by least two pixel region P1, as shown in Figure 2 A.In addition, in the present embodiment, it is data line that the two trend of groove S2 and slit 160s can be same as signal wire 120d() trend, but in other embodiments, it is sweep trace that the two trend of groove S2 and slit 160s also can be same as signal wire 120s() trend.
Some pixel electrodes 160 can be arranged in a linear along a groove S2 wherein, and the part edge of pixel electrode 160 can trim at groove S2 adjacent thereto edge.Specifically, each groove S2 has the first edge E21 and the second edge E22, and the second E22 position, edge is on the opposite of the first edge E21.The first edge E21 is not hidden by pixel electrode 160, and extends along pixel edge 160e adjacent thereto, and the pixel edge 160e of the second edge E22 and pixel electrode 160 trims, as shown in Figure 2 A and 2 B.Utilize the first edge E11, these grooves S2 also can improve the intensity of the horizontal component of electric field that pixel electrode 160 produces, and then improves the liquid crystal efficiency of display.
Should be noted that, although groove S2 and these signal wires 120s are staggered, and groove S2 is by least two pixel region P1, and these grooves S2 can't split into plural parts by common electrode 240.So the integral edge of groove S2 is continuous, but not separated from one another.That is to say, the two can be connected the first edge E21 of groove S2 and the second edge E22 via other edges.
In addition, in the embodiment shown in Fig. 2 A, 240 of common electrodes have groove S2, and do not there is the groove S1 in previous embodiment, but in other embodiments, common electrode 240 also can have the groove of two kinds of different lengths, and common electrode 240 not only has groove S2, and can have groove S1.In addition,, according to multiple different product demand and specification, groove S1 can have multiple different design on quantity and arrangement mode from S2.For example, the wherein at least one groove S2 in Fig. 2 A can be replaced with groove S1.Or common electrode 240 can have groove S1 and the S2 of equal number, and these grooves S1 and S2 ground interlaced with each other are side by side.Therefore, these grooves S1 shown in Figure 1A and Fig. 2 A and S2 are only for illustrating, and non-limiting the present invention.
Common electrode 240 can also have a plurality of opening H1 and many strip electrodes bar 242.Specifically, it is data line that each opening H1 is formed on a wherein signal line 120d() directly over, and extend along this signal wire 120d.These openings H1 is not all connected with any groove S2, so partial common electrode 240 can be formed on one of them opening H1 and the groove S2 that is adjacent between, and this partial common electrode 240 is electrode strip 242, wherein part the first edge E21 can become the edge of electrode strip 242, and each strip electrode bar 242 can extend along pixel edge 160e.These electrode strips 242 can not hidden by pixel electrode 160, and can produce stronger horizontal component of electric field between electrode strip 242 and pixel electrode 160, thereby increase the amplitude that liquid crystal molecule can deflection.
In addition, due to each opening H1 be formed on a signal line 120d wherein directly over, therefore these openings H1 can dwindle the overlapping region between common electrode 240 and signal wire 120d, to weaken the capacitance coupling effect being caused between common electrode 240 and signal wire 120d, and then alleviate the signal delay situation in signal wire 120d.In addition, in the present embodiment, a plurality of opening H1 arrange along signal wire 120d, but in other embodiments, be positioned at same signal wire 120d directly over these signal wires 120d can be connected with each other, to form a long and narrow groove.
In addition, according to multiple different product demand and specification, wherein at least one the opening H1 in Fig. 2 A can be filled up by common electrode 240, even can be as the embodiment shown in Figure 1A, and common electrode 240 also can comprehensively cover these signal wires 120d.So these openings H1 shown in Fig. 2 A is only for illustrating, and non-limiting the present invention.
Fig. 3 is the wiring schematic diagram of the transistor (TFT) array substrate of another embodiment of the present invention.Refer to Fig. 3, transistor (TFT) array substrate 300 and aforementioned transistor (TFT) array substrate 100 the two structural similarity of the present embodiment, effect is identical haply, and the two identical feature is no longer described in detail below.But, transistor (TFT) array substrate 300 and 100 still has difference between the two, it is that the profile of the pixel electrode 360 of transistor (TFT) array substrate 300 is different from the profile of pixel electrode 160, and the common electrode 340 of transistor (TFT) array substrate 300 has the groove S3 that shape is different from groove S1.
Particularly, in transistor (TFT) array substrate 300, pixel electrode 360 has a plurality of slit 360s.Slit 360s is shaped as V-arrangement, and these slits 360s is arranged side by side each other, wherein these slits 360s in same pixel electrode 360 move towards mutually the same, as shown in Figure 3.In the present embodiment, these slits 360s of same pixel electrode 360 can arrange along signal wire 120d, but in other embodiments, these slits 360s of same pixel electrode 360 also can arrange along signal wire 120s.Therefore, the orientation of these slits 360s in single pixel electrode 360 is not subject to the disclosure of Fig. 3 and is limited.In addition, each pixel electrode 360 also has a pair of pixel edge 360e respect to one another, and pixel edge 360e can extend along the slit 360s being adjacent, so the shape of pixel edge 360e is also V-arrangement, as shown in Figure 3.
Common electrode 340 has many groove S3 arranged side by side each other, and groove S3 be positioned at a pixel edge 360e wherein under.Groove S3 has the first edge E31 and the second edge E32, and wherein the second E32 position, edge is on the opposite of the first edge E31.The first edge E31 extends along pixel edge 360e adjacent thereto, and by pixel electrode 360, is not hidden.Due to the V-arrangement that is shaped as of pixel edge 360e, so the shape of the first edge E31 extending along pixel edge 360e is also V-arrangement.
In the present embodiment, the second edge E32 is hidden by pixel electrode 360, but in other embodiments, the second edge E32 also can trim with the pixel edge 360e of pixel electrode 360.In addition, in the embodiment shown in fig. 3, common electrode 340 can be overlapping with these signal wires 120d, 120s and transistor 130, and common electrode 340 can also comprehensively cover these signal wires 120d.So, when transistor (TFT) array substrate 300 running, common electrode 340 can be used as electro-magnetic screen layer, to reduce signal wire 120d and the 120s interference to pixel electrode 360.
But, in other embodiments, common electrode 340 also can have a plurality of opening H1 and many strip electrodes bars 242 as shown in Figure 2 A, and wherein these openings H1 can be along signal wire 120d or 120s and arranged.So, can dwindle the overlapping region between common electrode 340 and signal wire 120d or 120s, thereby weaken the capacitance coupling effect causing between common electrode 340 and signal wire 120d or 120s.In addition, these openings H1 that above-mentioned common electrode 340 has can be connected with each other, to form a long and narrow groove.
Fig. 4 A is the schematic perspective view of the display device of one embodiment of the invention, and Fig. 4 B is the decomposing schematic representation of the display device in Fig. 4 A.Refer to Fig. 4 A and Fig. 4 B, the display device 400 of the present embodiment can be the displays such as computer screen (as shown in Figure 4 A and 4 B shown in FIG.) or televisor.Or, display device 400 can be the screen of hand-hold electronic equipments (portable electronic device), and wherein this hand-hold electronic equipments is such as being mobile phone, wisdom mobile phone, panel computer, notebook computer, digital camera, digital camera or handheld game device etc.
Display device 400 comprises assemble case 410, display panels 420, backlight module 440 and circuit board assemblies 430, and wherein assemble case 410 can comprise two housing units 412 and 414.Utilize housing unit 412 and 414 the two combinations, display panels 420, backlight module 440 and circuit board assemblies 430 are installed in assemble case 410.Display panels 420 is electrically connected circuit board assemblies 430.Backlight module 440 is relative with display panels 420 and establish, and backlight module 440 can be used as the backlight of display panels 420.
Circuit board assemblies 430 can be the hard circuit board (flex-rigid circuit board) that a kind of installing (mount) has a plurality of electronic components, and comprise rigid wiring board (rigid circuit board) 432 and bendable wiring board (flexible circuit board) 434, wherein above-mentioned electronic component comprises a plurality of passive devices and a plurality of active member, and these passive devices and these active members can form driving circuit and feed circuit, wherein driving circuit can drive display panels 420 to show image frame, and feed circuit can be controlled extraneous electric energy and input to backlight module 440 and display panels 420.
In addition, bendable wiring board 434 is connected between rigid wiring board 432 and display panels 420.Utilize bendable wiring board 434, circuit board assemblies 430 can be electrically connected display panels 420.In addition, circuit board assemblies 430 also can utilize many wires to carry out electrical connecting fluid LCD panel 420, so circuit board assemblies 430 does not limit, is only hard circuit board.
Fig. 4 C is the diagrammatic cross-section of display panels in Fig. 4 B.Refer to Fig. 4 C, display panels 420 comprises transistor (TFT) array substrate 422, subtend substrate 424 and liquid crystal layer 426, wherein liquid crystal layer 426 is configured between transistor (TFT) array substrate 422 and subtend substrate 424, and transistor (TFT) array substrate 422 can be bonded to each other via frame glue (scheming not shown) with subtend substrate 424, wherein this frame glue can around and sealing liquid crystal layer 426.
Transistor (TFT) array substrate 422 can be the transistor (TFT) array substrate 100,200 or 300 in previous embodiment, and display panels 420 can be fringe field switching (FFS) display or the special-purpose panel of transverse electric field effect (IPS).Therefore, liquid crystal layer 426 can comprise the liquid crystal material of horizontal direction matching.In addition, subtend substrate 424 can be colored optical filtering substrates (color filter array substrate).
In sum, common electrode in the embodiment of the present invention has a plurality of grooves, and groove position is under one of them pixel edge of pixel electrode, and have the part edge (for example the first edge) not hidden by pixel electrode, wherein this part edge is along the pixel edge of pixel electrode and extend.Therefore, these grooves can improve the intensity of the horizontal component of electric field that pixel electrode produces, and to increase the amplitude that liquid crystal molecule can deflection, thereby improve the liquid crystal efficiency of display.
The foregoing is only preferred possible embodiments of the present invention, all equalizations of doing according to the claims in the present invention scope change and modify, and all should belong to covering scope of the present invention.

Claims (10)

1. a transistor (TFT) array substrate, is characterized in that, described transistor (TFT) array substrate comprises:
One substrate, has a surface;
Many signal line, are configured on described surface, and each described signal wire has a signal wire view field on described surface;
A plurality of transistors, are configured on described surface and are electrically connected described signal wire;
One insulation course, is configured on described signal wire and described transistor;
A plurality of pixel electrodes, are formed on described insulation course and are electrically connected described transistor, and described in each, the periphery of pixel electrode has a plurality of pixel edges respect to one another, and described in each, pixel electrode has a pixel projection region on described surface; And
One common electrode, be configured under described insulation course and there are a plurality of grooves, one of them of described groove be positioned at pixel edge described in one of them under, and described groove has one first edge, described the first edge is along extending with the contiguous described pixel edge in described the first edge and have a projected segment on described surface, and described projected segment is between the described pixel projection region adjacent with described projected segment and described signal wire view field.
2. transistor (TFT) array substrate according to claim 1, is characterized in that, described projected segment is positioned at outside the described pixel projection region adjacent with described projected segment.
3. transistor (TFT) array substrate according to claim 1, is characterized in that, described the first edge is parallel to the described pixel edge contiguous with described the first edge.
4. transistor (TFT) array substrate according to claim 1, is characterized in that, described groove also has one second edge, and described the second edge is positioned at the opposite at described the first edge, and and trims with the described pixel edge of described the second edge vicinity.
5. transistor (TFT) array substrate according to claim 1, is characterized in that, described in each, pixel electrode has a plurality of slits, and each other side by side and extend along described pixel edge, described slit and described groove are not overlapping for described slit.
6. transistor (TFT) array substrate according to claim 1, is characterized in that, a wherein part for described signal wire is arranged side by side each other, and each other described in this part arranged side by side signal wire and described groove staggered.
7. transistor (TFT) array substrate according to claim 1, it is characterized in that, described signal wire comprises many data lines and multi-strip scanning line, and described data line is arranged side by side each other, and described sweep trace is arranged side by side each other, wherein said data line and described sweep trace are interlaced with each other.
8. transistor (TFT) array substrate according to claim 7, it is characterized in that, described common electrode also has a plurality of openings and a plurality of electrode strip, described in each opening be formed on a described data line wherein directly over, and described in each, electrode strip is formed between opening described in one of them and the described groove adjacent with described electrode strip, and extend along described pixel edge.
9. according to the transistor (TFT) array substrate described in claim 7, it is characterized in that, described common electrode and described data line are overlapping.
10. a display device, is characterized in that, described display device comprises:
One display panels, comprises;
One transistor (TFT) array substrate according to claim 1;
One subtend substrate;
One liquid crystal layer, is configured between described transistor (TFT) array substrate and described subtend substrate; And
One backlight module; And
One circuit board assemblies, drives described display panels to show an image frame.
CN201310188276.2A 2013-05-20 2013-05-20 Display device and transistor array substrate thereof Pending CN104181733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310188276.2A CN104181733A (en) 2013-05-20 2013-05-20 Display device and transistor array substrate thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310188276.2A CN104181733A (en) 2013-05-20 2013-05-20 Display device and transistor array substrate thereof

Publications (1)

Publication Number Publication Date
CN104181733A true CN104181733A (en) 2014-12-03

Family

ID=51962895

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310188276.2A Pending CN104181733A (en) 2013-05-20 2013-05-20 Display device and transistor array substrate thereof

Country Status (1)

Country Link
CN (1) CN104181733A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107957645A (en) * 2016-10-14 2018-04-24 瀚宇彩晶股份有限公司 Display panel and its production method
US10663822B2 (en) 2016-10-14 2020-05-26 Hannstar Display Corporation Display panel and manufacturing method thereof
CN113035066A (en) * 2020-08-21 2021-06-25 友达光电股份有限公司 Electronic device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1223427A (en) * 1997-11-03 1999-07-21 三星电子株式会社 Liquid crystal display having modified electrode array
TW513600B (en) * 2000-06-07 2002-12-11 Ind Tech Res Inst In-plane switching liquid crystal displaying device and method of fabricating the same
TW200931105A (en) * 2008-01-11 2009-07-16 Chunghwa Picture Tubes Ltd Liquid crystal display
US20110317117A1 (en) * 2010-06-24 2011-12-29 Jeong-Oh Kim Array substrate for wide viewing angle liquid crystal display device and mehod of manufacturing the same
CN103018973A (en) * 2011-09-22 2013-04-03 瀚宇彩晶股份有限公司 Unit pixel of liquid crystal display

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1223427A (en) * 1997-11-03 1999-07-21 三星电子株式会社 Liquid crystal display having modified electrode array
TW513600B (en) * 2000-06-07 2002-12-11 Ind Tech Res Inst In-plane switching liquid crystal displaying device and method of fabricating the same
TW200931105A (en) * 2008-01-11 2009-07-16 Chunghwa Picture Tubes Ltd Liquid crystal display
US20110317117A1 (en) * 2010-06-24 2011-12-29 Jeong-Oh Kim Array substrate for wide viewing angle liquid crystal display device and mehod of manufacturing the same
CN103018973A (en) * 2011-09-22 2013-04-03 瀚宇彩晶股份有限公司 Unit pixel of liquid crystal display

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107957645A (en) * 2016-10-14 2018-04-24 瀚宇彩晶股份有限公司 Display panel and its production method
US10663822B2 (en) 2016-10-14 2020-05-26 Hannstar Display Corporation Display panel and manufacturing method thereof
CN113035066A (en) * 2020-08-21 2021-06-25 友达光电股份有限公司 Electronic device
CN113035066B (en) * 2020-08-21 2022-12-02 友达光电股份有限公司 Electronic device with a detachable cover

Similar Documents

Publication Publication Date Title
CN106325608B (en) Touch display panel and touch display device
CN106647071B (en) A kind of array substrate, display panel and display device
KR101463694B1 (en) Liquid crystal display device with a built-in touch panel
US10156925B2 (en) Array substrate, method for fabricating the same, and display apparatus
CN104793362B (en) Liquid crystal display panel
CN100592183C (en) Liquid crystal display device and display apparatus
CN102844803B (en) Active matrix substrate and display device
CN102854674A (en) Display panel and liquid crystal display
CN205353532U (en) Array substrate and display panel
CN103135294B (en) Pixel structure of liquid crystal display panel
US9971218B2 (en) Display device, display panel, array substrate and driving method thereof
CN105807979A (en) Embedded touch control display panel
JP6475947B2 (en) Liquid crystal display
CN104156101A (en) Touch display panel, touch display device and drving method thereof
CN107179637B (en) Array substrate, liquid crystal display panel and liquid crystal display device
CN104204928A (en) Liquid crystal display panel
CN109388265A (en) A kind of array substrate, touch-control display panel and display device
CN114280861A (en) Array substrate and display device
CN104181733A (en) Display device and transistor array substrate thereof
US20180373091A1 (en) Display panel
CN104698699A (en) Array substrate, display panel, display device and driving method thereof
CN104122715A (en) Thin film transistor substrate and LCD panel
US9395590B2 (en) Liquid crystal display
US9001285B2 (en) Electronic device and display panel thereof
US11199919B2 (en) In-cell touch display device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20141203