CN107179637B

CN107179637B - Array substrate, liquid crystal display panel and liquid crystal display device

Info

Publication number: CN107179637B
Application number: CN201710455475.3A
Authority: CN
Inventors: 谢惠敏; 张沼栋
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2017-06-16
Filing date: 2017-06-16
Publication date: 2020-05-12
Anticipated expiration: 2037-06-16
Also published as: CN107179637A

Abstract

The invention discloses an array substrate, a liquid crystal display panel and a liquid crystal display device, comprising: a substrate base plate; the pixel electrode comprises a plurality of common electrode blocks, a plurality of signal lines, thin film transistors arranged in an array and pixel electrodes arranged in an array; the common electrode block is provided with hollow parts, the hollow parts are arranged in the area between two adjacent rows of thin film transistors, and the orthographic projection of the signal line on the substrate covers the orthographic projection of the hollow parts on the substrate; the pixel electrode comprises a convex part, the orthographic projection of the convex part on the substrate base plate is not overlapped with the orthographic projection of the hollow part on the substrate base plate, the convex part comprises one side of the convex part extending along the second direction and two sides of the convex part extending along the first direction, the length of one side of the convex part is d1, and d1 is 1.65-3.5 um. The array substrate, the liquid crystal display panel and the liquid crystal display device provided by the embodiment of the invention can improve the signal transmission precision of the signal lines and improve the display effect.

Description

Array substrate, liquid crystal display panel and liquid crystal display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a liquid crystal display panel and a liquid crystal display device.

Background

With the development of display technology, display devices with touch control function are popular with consumers, such as mobile phones, tablet computers, and notebook computers with touch control function.

In a display device provided in the prior art, a touch electrode is integrated in a display panel to implement a touch function. Referring to fig. 1, fig. 1 is a schematic plan view of a display panel in the prior art, which includes a substrate 01, a plurality of touch electrodes 02 arranged along a row direction and a column direction, and a touch signal line 03 electrically connected to the touch electrodes 02. When the touch electrode block 02 detects a touch operation, the coupling capacitance formed by the touch electrode block 02 and the ground changes, the capacitance changes to change the charge amount carried by the touch electrode block 02, the charge amount changes to change the current, the touch signal line 03 outputs the current change, and the current change is calculated and analyzed to determine the information of the touch operation.

Referring to fig. 2, fig. 2 is a partial structure diagram of the display panel provided in fig. 1, fig. 2 illustrates a structure diagram of a sub-pixel, the display panel further includes a gate line 04, a pixel electrode 05 and a thin film transistor 06, wherein the pixel electrode 05 and the thin film transistor 06 are electrically connected, the pixel electrode 05 extends along a first direction, the first direction intersects with a row direction and the first direction intersects with a column direction, and the arrangement of the pixel electrode 05 extending along the first direction can effectively improve the transmittance of the display panel and enhance the display effect. However, researchers have found that when a finger presses the display panel, a moire phenomenon (mura) occurs on the display panel, and the speed at which the moire phenomenon disappears is slow after the finger is separated.

Disclosure of Invention

In view of the above, the present invention provides an array substrate, including:

a substrate base plate; the array substrate comprises a substrate base plate, a plurality of common electrode blocks and a plurality of signal wires, wherein the common electrode blocks are arranged in m rows and n columns along the row direction and the column direction, m is more than or equal to 2, n is more than or equal to 2, the signal wires are arranged in parallel and extend along the column direction, and one common electrode block is electrically connected with at least one signal wire and is insulated from the rest signal wires; the array-arranged thin film transistors and the array-arranged pixel electrodes are positioned on the substrate, and the signal lines are arranged in the area between two adjacent columns of pixel electrodes; the common electrode block is provided with hollow parts, the hollow parts are arranged in the area between two adjacent rows of thin film transistors, and the orthographic projection of the signal line on the substrate covers the orthographic projection of the hollow parts on the substrate; the pixel electrode comprises a convex part, a first strip-shaped electrode part extending along a first direction and a connecting part, and the connecting part is electrically connected with the thin film transistor; the first strip-shaped electrode part comprises a first edge and a second edge which are oppositely arranged, and a third edge and a fourth edge which are oppositely arranged, wherein the first edge is electrically connected with the connecting part, the second edge is arranged on one side of the first strip-shaped electrode part, which is far away from the connecting part, the first edge and the second edge both extend along a second direction, the third edge and the fourth edge both extend along a first direction, and the first direction is intersected with the second direction; the orthographic projection of the convex part on the substrate base plate is not overlapped with the orthographic projection of the hollow part on the substrate base plate; the bulge includes the bulge that extends along the second direction on one side and the bulge that extends along the first direction on two sides, and the bulge is located the extension line of second limit place straight line on one side, and the two sides of bulge coincide with the third side part, and the length on one side of bulge is d1, and d1 is 1.65 ~ 3.5 um.

Optionally, fretwork portion is including relative fretwork portion that sets up on one side and two limits of fretwork portion, and the second direction all is extended on one side of fretwork portion and two limits of fretwork portion, and the distance between one side of protrusion and fretwork portion is d2, and d2 is 4.2 ~ 7.6 um.

Optionally, the first direction intersects with the column direction, and the second direction is a row direction.

Optionally, the protruding portion is a quadrilateral, and further includes three protruding portion edges and four protruding portion edges, the three protruding portion edges extend along the row direction, an included angle between a straight line where the four protruding portion edges are located and the first direction is θ, and θ is 50 ° to 60 °.

Optionally, the signal line is electrically connected to the common electrode block through a bridge portion, and the bridge portion is made of the same material as the pixel electrode.

Optionally, the pixel electrode is disposed on a side of the common electrode block away from the substrate base plate.

Optionally, the pixel electrode further includes at least one second strip-shaped electrode portion, and the second strip-shaped electrode portion extends along the first direction and is arranged in parallel with the first strip-shaped electrode portion.

Optionally, the common electrode block is reused as a touch electrode block, and the signal line is used for inputting a touch emission signal to the corresponding common electrode block and outputting a touch sensing signal.

The invention also provides a liquid crystal display panel which comprises the array substrate provided by the invention, a color film substrate and a liquid crystal layer clamped between the array substrate and the color film substrate, wherein the material of the liquid crystal layer comprises negative liquid crystal.

The invention also provides a liquid crystal display device which comprises the liquid crystal display panel provided by the invention.

Compared with the prior art, the array substrate, the liquid crystal display panel and the liquid crystal display device provided by the invention at least realize the following beneficial effects:

in the array substrate, the liquid crystal display panel and the liquid crystal display device provided by the invention, the hollow parts are arranged in the common electrode block and are arranged in the area between two adjacent rows of thin film transistors, the orthographic projection of the signal line on the substrate covers the orthographic projection of the hollow parts on the substrate, and the direct coupling capacitance of the common electrode block and the signal line is reduced, so that the interference on the electric signal transmitted by the signal line is reduced, and the signal transmission precision of the signal line is improved.

In the array substrate, the liquid crystal display panel and the liquid crystal display device provided by the invention, the convex part is arranged in the pixel electrode, so that the ripple phenomenon caused by finger pressing can be effectively reduced, the orthographic projection of the convex part on the substrate is not overlapped with the orthographic projection of the hollow part on the substrate, the length of one side of the convex part is d1, d1 is 1.65-3.5 um, and the length of one side of the convex part is in the range of 1.65-3.5 um, so that the convex part and the hollow part are not overlapped in the direction vertical to the substrate, and the coupling effect between the signal lines exposed by the convex part and the hollow part is reduced.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel provided in the prior art;

FIG. 2 is a schematic diagram of a partial structure of the display panel provided in FIG. 1;

fig. 3 is a schematic plan view illustrating an array substrate according to an embodiment of the present invention;

FIG. 4 is a schematic view of a partial structure of the array substrate provided in the embodiment of FIG. 3;

FIG. 5 is a schematic view of another partial structure of the array substrate provided in the embodiment of FIG. 3;

FIG. 6 is a schematic diagram of another partial structure of the array substrate provided in the embodiment of FIG. 3;

FIG. 7 is a schematic view of another partial structure of the array substrate provided in the embodiment of FIG. 3;

FIG. 8 is a schematic view of a partial structure of the array substrate provided in the embodiment of FIG. 7;

FIG. 9 is a schematic view of another partial structure of the array substrate provided in the embodiment of FIG. 3;

fig. 10 is a schematic cross-sectional view illustrating an array substrate according to an embodiment of the present invention;

fig. 11 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the invention;

fig. 12 is a schematic plan view of a display device according to an embodiment of the present invention;

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Referring to fig. 3, fig. 4 and fig. 5 in combination, fig. 3 is a schematic plan structure view of an array substrate according to an embodiment of the present invention, fig. 4 is a schematic partial structure view of the array substrate according to the embodiment of fig. 3, and fig. 5 is a schematic partial structure view of the array substrate according to the embodiment of fig. 3. Referring to fig. 3, an array substrate according to an embodiment of the present invention includes: a substrate base plate 00; the array substrate comprises a plurality of common electrode blocks 10 and a plurality of signal lines 20, wherein the common electrode blocks 10 are arranged in m rows and n columns along the row direction and the column direction, m is more than or equal to 2, n is more than or equal to 2, the signal lines are arranged in parallel and extend along the column direction, one common electrode block 10 is electrically connected with at least one signal line 20 and is insulated from the rest signal lines 20, and optionally, the common electrode blocks 10 are electrically connected with the signal lines 20 through via holes 22. It should be noted that, in fig. 1, only 4 common electrode blocks 10 are arranged in 2 rows and 2 columns along the row direction and the column direction for illustration, in other implementation manners of the present invention, the number of the common electrode blocks may be 6 and arranged in 3 rows and 2 columns along the row direction and the column direction, or the number of the common electrode blocks may be 9 and arranged in 3 rows and 3 columns along the row direction and the column direction, which is not limited in this embodiment. In fig. 1, only one common electrode block 10 is electrically connected to one signal line 20 and insulated from the other signal lines 20, in other implementations of the present invention, one common electrode block 10 may be electrically connected to more than two signal lines 20 and insulated from the other signal lines 20, and when there is an open circuit or the like in a signal line 20, the other signal lines 20 electrically connected to the common electrode block 10 may still transmit electrical signals to the common electrode block 10, thereby improving the reliability of the array substrate.

Referring to fig. 4, the array substrate according to the embodiment of the present invention further includes thin film transistors 30 arranged in an array and pixel electrodes 40 arranged in an array on the substrate 00; the signal line 20 is disposed in a region between two adjacent columns of the pixel electrodes 40; the common electrode block 10 has a hollow portion 11, the hollow portion 11 is disposed in a region between two adjacent rows of the thin film transistors 30, and an orthogonal projection of the signal line 20 on the substrate 00 covers an orthogonal projection of the hollow portion 11 on the substrate 00. It should be noted that in the array substrate provided in this embodiment, one common electrode block 10 may cover a plurality of rows and a plurality of columns of thin film transistors 30 and pixel electrodes 40; the thin film transistor 30 is electrically connected to the corresponding pixel electrode 40, and the thin film transistor 30 may have a structure including a gate electrode 31, a source electrode 32, and a drain electrode 33, and in particular, the drain electrode 33 is electrically connected to the pixel electrode 40. The orthographic projection of the signal line 20 on the substrate base 00 means that in the parallel projection of the signal line 20, the projection line is perpendicular to the substrate base 00, and the parallel projection is called the orthographic projection, and similarly, the orthographic projection of the hollow part 11 on the substrate base 00 means that in the parallel projection of the hollow part 11, the projection line is perpendicular to the substrate base 00, and the parallel projection is called the orthographic projection. The orthographic projection of the signal line 20 on the substrate base 00 covers the orthographic projection of the hollow part 11 on the substrate base 00, in other words, the length and the width of the hollow part 11 do not exceed the length and the width of the signal line 20; and the hollow parts 11 are disposed in the area between two adjacent rows of the thin film transistors 30, in other words, one common electrode block 10 may have a plurality of hollow parts 11.

The area where the signal line 20 is disposed between two adjacent columns of pixel electrodes 40 includes two cases, in the first case, the signal line 20 is disposed in the area between any two adjacent columns of pixel electrodes 40; in the second case, the signal line 20 is provided only in a region between two adjacent columns of pixel electrodes 40, and the signal line 20 is not provided in the remaining region between two adjacent columns of pixel electrodes 40. In fig. 4, an embodiment in which the signal line 20 is disposed only in a region between two adjacent columns of the pixel electrodes 40 in the second case is illustrated, and this is not particularly limited in the embodiment of the present invention.

Referring to fig. 5, the pixel electrode 40 includes a protrusion 41, a first strip electrode 42 extending along a first direction, and a connection portion 43, wherein the connection portion 43 is electrically connected to the thin film transistor 30; the first strip-shaped electrode part 42 comprises a first side L1 and a second side L2 which are oppositely arranged, and a third side L3 and a fourth side L4 which are oppositely arranged, wherein the first side L1 is electrically connected with the connecting part 43, the second side L2 is arranged on one side of the first strip-shaped electrode part 42 away from the connecting part 43, the first side L1 and the second side L2 both extend along the second direction, the third side L3 and the fourth side L4 both extend along the first direction, and the first direction is crossed with the second direction; the orthographic projection of the convex part 41 on the substrate base 00 is not overlapped with the orthographic projection of the hollow part 11 on the substrate base 00. It should be noted that the pixel electrode 40 includes a protrusion 41, a first strip-shaped electrode portion 42 extending along a first direction, and a connection portion 43, where any two of the protrusion 41, the first strip-shaped electrode portion 42, and the connection portion 43 are electrically connected, one pixel electrode 40 is an integral structure, and the structures of the parts of the pixel electrode 40 do not physically exist independently; note that the first side L1 of the first stripe electrode portion 42 is electrically connected to the connection portion 43, and the first side L1 is not a boundary in the physical structure, but is a boundary artificially divided for the purpose of clearly describing the technical solution of the present invention. The connection portion 43 is electrically connected to the thin film transistor 30, and specifically, the connection portion 43 is electrically connected to the drain electrode 33 of the thin film transistor 30. Wherein, in some alternative implementations, the second direction is the same direction as the row direction. In other alternative implementations, the first direction intersects the column direction and the first direction is at an angle in the range of 10 ° to 15 ° to the column direction.

With reference to fig. 5, the protrusion 41 includes a protrusion side T1 extending along the second direction and a protrusion side T2 extending along the first direction, the protrusion side T1 is located on an extension line of a straight line of the second side L2, the protrusion side T2 and the third side L3 are partially overlapped, a length of the protrusion side T1 is d1, and d1 is 1.65-3.5 um. The second projecting edge T2 partially coincides with the third edge L3, and the second projecting edge T2 is not a boundary embodied on a physical structure, but a boundary artificially divided for clearly describing the technical solution of the present invention. The projection 41 and the first strip electrode 42 are substantially of an integral structure, and are not physically independent.

It should be noted that, in the array substrate provided in the embodiment of the present invention, there are two relative positional relationships between the protruding portion 41 and the signal line 20. Specifically, when the signal line 20 is disposed in the area between two adjacent columns of the pixel electrodes 40, the protruding portion 41 may be disposed on the side of the first strip-shaped electrode portion 42 close to the signal line 20, or on the side of the first strip-shaped electrode portion 42 away from the signal line 20. Referring to fig. 4, the protrusion 411 is disposed on a side of the first stripe electrode 42 close to the signal line 20, and the protrusion 412 is disposed on a side of the first stripe electrode 42 away from the signal line 20. Optionally, in order to ensure uniformity of the display effect of the array substrate, the relative position relationship between the protruding portion 41 and the first strip electrode portion 42 is the same.

In the array substrate provided by the embodiment of the invention, the hollow-out parts are arranged in the common electrode block and are arranged in the area between two adjacent rows of thin film transistors, the orthographic projection of the signal line on the substrate covers the orthographic projection of the hollow-out parts on the substrate, and the direct coupling capacitance of the common electrode block and the signal line is reduced, so that the interference of an electric signal transmitted by the signal line is reduced, and the signal transmission precision of the signal line is improved. In the array substrate provided by the embodiment of the invention, the convex part is arranged in the pixel electrode, so that the ripple phenomenon caused by pressing of fingers can be effectively reduced, the orthographic projection of the convex part on the substrate is not overlapped with the orthographic projection of the hollow part on the substrate, the length of one side of the convex part is d1, d1 is 1.65-3.5 um, and the length of one side of the convex part is set within the range of 1.65-3.5 um, so that the convex part and the hollow part are not overlapped in the direction vertical to the substrate, and the coupling effect between the signal lines exposed by the convex part and the hollow part is reduced.

In some optional implementation manners, please refer to fig. 6, fig. 6 is a schematic diagram of another partial structure of the array substrate provided in the embodiment of fig. 3, and fig. 6 follows the reference numerals of fig. 5, and the same parts are not repeated. Fig. 6 is different from fig. 5 in that the pixel electrode 40 further includes at least one second stripe electrode portion 411, and the second stripe electrode portion 411 extends along the first direction and is parallel to the first stripe electrode portion 42. It should be noted that in the array substrate provided in this embodiment, the pixel electrode 40 includes a first strip electrode portion 42 and at least one second strip electrode portion 411, wherein any two of the protrusion portion 41, the first strip electrode portion 42, the connection portion 43, and the second strip electrode portion 411 are electrically connected, one pixel electrode 40 is an integral structure, and the structures of the parts of the pixel electrode 40 do not physically exist independently. The pixel electrode 40 includes at least two strip electrode portions, each of the strip electrode portions is arranged in parallel, and a slit is formed between two adjacent strip electrode portions.

In some optional implementations, in the array substrate provided in the embodiment of the present invention, the hollow portion includes a hollow portion side and a hollow portion both opposite to each other, the hollow portion side and the hollow portion both extend along the second direction, a distance between one side of the protruding portion and the hollow portion side is d2, d2 is 4.2-7.6 um, and specifically, refer to fig. 7, and fig. 7 only illustrates the array substrate provided in the embodiment of fig. 6. Fig. 7 uses the reference numerals of fig. 6, the same parts are not repeated, and fig. 7 differs from fig. 6 in that the hollow portion 11 includes a hollow portion side K1 and a hollow portion two side K2 which are arranged oppositely, the hollow portion side K1 and the hollow portion two side K2 both extend along the second direction, the distance between the protruding portion side T1 and the hollow portion side K1 is d2, and d2 is 4.2-7.6 um. In the array substrate provided by this embodiment, by setting the distance between the T1 on one side of the protruding portion and the K1 on one side of the hollow portion to be d2, and the length of d2 to be within the range of 4.2 to 7.6um, the protruding portion and the hollow portion 11 are further prevented from overlapping in the direction perpendicular to the substrate, and the coupling effect between the signal lines exposed by the protruding portion and the hollow portion 11 is reduced. The derivation relationship between the value range of d2 and the value range of d1 is explained in detail below.

In some alternative implementations, referring to fig. 8, fig. 8 is a schematic diagram of a partial structure of the array substrate provided in the embodiment of fig. 7, for clarity of derivation relationship between a value range of D2 and a value range of D1, fig. 8 only illustrates a partial structure of the pixel electrode 40 and a partial structure of the common electrode block 10, points and line segments in fig. 8 are first described, the hollowed portion 11 has a boundary near one side of the pixel electrode 40, an extension line of the boundary has an intersection point a with a row direction boundary of the common electrode block 10, one end of the hollowed portion K1 near the pixel electrode 40 has an end point B, a straight line passing through point B and extending in a column direction has an intersection point C with a row direction boundary 865 of the common electrode block 10, one side T1 of the pixel electrode 40 has two end points D and an end point H, where the end point H is located on an extension line of a third side L3, a line segment DH 63i is one side T1, the bulged portion 41 also has an apex E and an apex F, where a segment DE extends in a column direction, a segment extends along a line F-a perpendicular line F60-F, and an included angle θ F35 is equal to a straight line F8, and an angle formed by a derivation relationship between a straight line F60-F8, where the straight line connecting a straight line extending along a straight line F60-F20, and a straight line which is equal to a straight line which a straight:

d2＝AC/tanα＝(AH-CH)/tanα＝(m/cosα-d1-n*sinβ)/tanα ①

when the minimum value of d1 is 1.65 μm, d1 ═ 1.65 μm, m ═ 3.5 μm, α ═ 15 °, θ ═ 50 °, β ═ 25 °, n ═ 2 μm are put into equation ①, and the following results are obtained:

d2＝(3.5/cos15°-1.65-2*sin25°)/tan15°＝4.2μm。

when the length of D1 becomes larger, point D moves to point D, keeping the length of DE unchanged, point E moves to point E, point F moves to point F, and if the distance from point B to the straight line of the EF connection line is kept constant, point B moves to point B, it can be deduced that D2 and D1 have the relationship of formula ②:

d2＝AC/tanα+Bb*cosα＝(m/cosα-d1-n*sinβ)/tanα+(Ee*sinβ/sinθ)*cosα ②

when d1 is 3.5 μm as the maximum value, Ee is 3.5-1.65 μm, d 1' is 3.5 μm, Ee is 1.85 μm, m is 3.5 μm, α is 10 °, θ is 60 °, β is 20 °, n is 2 μm, and the formula ② is given as follows:

d2’＝(3.5/cos15°-3.5-2*sin25°)/tan15°+(1.85*sin20°/sin60°)*cos10°＝7.6μm。

as can be derived from the above, in the array substrate provided in this embodiment, when d1 is 1.65 to 3.5um, d2 is 4.2 to 7.6 um.

In some optional implementations, in the array substrate provided in any of the above embodiments of the present invention, the first direction intersects with a column direction, and the second direction is a row direction.

In some optional implementations, in the array substrate provided in any of the above embodiments of the present invention, the protruding portion is a quadrilateral, and further includes three sides of the protruding portion and four sides of the protruding portion, where the three sides of the protruding portion extend along the column direction, an included angle between a straight line on which the four sides of the protruding portion are located and the first direction is θ, and θ is 50 ° to 60 °. Referring to fig. 9, fig. 9 is a schematic diagram illustrating the above features of the array substrate according to the embodiment of fig. 7. Fig. 9 is marked along with the reference numerals of fig. 7, and the same parts are not repeated, and in the array substrate provided in the embodiment of fig. 9, the protruding portion 41 is a quadrilateral, and further includes three protruding portion sides T3 and four protruding portion sides T4, the three protruding portion sides T3 extend along the column direction, and an included angle between a straight line where the four protruding portion sides T4 are located and the first direction is θ, where θ is 50 ° to 60 °.

In some optional implementation manners, please refer to fig. 10, where fig. 10 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention. In the array substrate provided in this embodiment of the present invention, the signal line 20 is electrically connected to the common electrode block 10 through the bridge portion 21, and the bridge portion 21 and the pixel electrode 40 are made of the same material. Optionally, the bridge 21 is electrically connected to the pixel electrode 40 through the via 211 and the via 212. The bridge part 21 and the pixel electrode 40 are made of the same material, and the bridge part 21 and the pixel electrode 40 can be formed in the same process in the process of manufacturing the array substrate, so that the process for manufacturing the array substrate is saved.

Alternatively, with continued reference to fig. 10, the pixel electrode 40 is disposed on a side of the common electrode block 10 away from the substrate base 00. The array substrate provided by the embodiment is of a midle-com structure, so that the transmittance of light passing through the array substrate is high, and the display quality of the display panel is improved.

In some optional implementations, the common electrode block 10 is multiplexed as a touch electrode block, and the signal line 20 is used to input a touch emission signal to the corresponding common electrode block 10 and output a touch sensing signal. In the array substrate provided by this embodiment, when the array substrate is used to perform a display function, the common electrode block 10 receives a common voltage signal; when the array substrate is used for executing a touch function, the common electrode block 10 is reused as a touch electrode block, and the working mode of the touch electrode block is a self-capacitance touch mode. Specifically, the signal line 20 inputs a touch emission signal to the common electrode block 10, the touch emission signal is usually a pulse signal, when the common electrode block 10 detects a touch operation, the coupling capacitance formed by the common electrode block 10 and the ground changes, the change of the capacitance causes the change of the charge amount charged in the common electrode block 10, the change of the charge amount causes the change of the current, the signal line 20 outputs the change of the current, and the change of the current is calculated and analyzed to determine the information of the touch operation.

Referring to fig. 10, a display panel 400 includes the array substrate 100 provided in any of the embodiments of the present invention, a color film substrate 200, and a liquid crystal layer 300 sandwiched between the array substrate 100 and the color film substrate 200, where the liquid crystal layer 300 is made of a negative liquid crystal. In the display panel provided by the embodiment, the material of the liquid crystal layer comprises negative liquid crystal, so that the light leakage phenomenon of the display panel in the working process can be reduced, and the display quality is improved. The liquid crystal display panel provided in this embodiment has the advantages of the array substrate provided in any of the above embodiments of the present invention, and details of this embodiment are not repeated herein.

Referring to fig. 11, a liquid crystal display device 500 includes the liquid crystal display panel 400 according to an embodiment of the present invention. Optionally, the liquid crystal display device 500 further includes a housing 410. The liquid crystal display device provided by the embodiment of the invention can be a mobile phone, a tablet computer, a notebook computer, a television and the like. The liquid crystal display device provided by the embodiment of the invention has the advantages of the liquid crystal display panel provided by the embodiment of the invention, and the details of the embodiment are not repeated herein.

According to the array substrate, the liquid crystal display panel and the liquid crystal display device, the hollow parts are arranged in the common electrode block and are arranged in the area between two adjacent rows of thin film transistors, the orthographic projection of the signal lines on the substrate covers the orthographic projection of the hollow parts on the substrate, and the direct coupling capacitance of the common electrode block and the signal lines is reduced, so that the interference of electric signals transmitted by the signal lines is reduced, and the signal transmission accuracy of the signal lines is improved.

In the array substrate, the liquid crystal display panel and the liquid crystal display device provided by the invention, the convex part is arranged in the pixel electrode, so that the ripple phenomenon caused by finger pressing can be effectively reduced, the orthographic projection of the convex part on the substrate is not overlapped with the orthographic projection of the hollow part on the substrate, the length of one side of the convex part is d1, d1 is 1.65-3.5 um, and the length of one side of the convex part is set within the range of 1.65-3.5 um, so that the convex part and the hollow part are not overlapped in the direction vertical to the substrate, and the coupling effect between the signal lines exposed by the convex part and the hollow part is reduced.

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. An array substrate, comprising:

a substrate base plate;

the array substrate comprises a substrate base plate, a plurality of common electrode blocks and a plurality of signal wires, wherein the substrate base plate is provided with the substrate base plate, the plurality of common electrode blocks are arranged in m rows and n columns along the row direction and the column direction, m is more than or equal to 2, n is more than or equal to 2, the plurality of signal wires are arranged in parallel and extend along the column direction, and one common electrode block is electrically connected with at least one signal wire and is insulated from the rest signal wires;

the array-arranged thin film transistors and the array-arranged pixel electrodes are positioned on the substrate base plate; the signal line is arranged in a region between two adjacent columns of the pixel electrodes; the common electrode block is provided with a hollow part, the hollow part is arranged in an area between two adjacent rows of the thin film transistors, and the orthographic projection of the signal line on the substrate covers the orthographic projection of the hollow part on the substrate;

the pixel electrode comprises a convex part, a first strip-shaped electrode part extending along a first direction and a connecting part, and the connecting part is electrically connected with the thin film transistor; the first strip-shaped electrode part comprises a first edge and a second edge which are oppositely arranged, and a third edge and a fourth edge which are oppositely arranged, wherein the first edge is electrically connected with the connecting part, the second edge is arranged on one side of the first strip-shaped electrode part, which is far away from the connecting part, the first edge and the second edge both extend along a second direction, the third edge and the fourth edge both extend along the first direction, and the first direction is intersected with the second direction; the orthographic projection of the convex part on the substrate base plate is not overlapped with the orthographic projection of the hollow part on the substrate base plate;

the bulge includes along bulge one side that the second direction extends and edge two sides of bulge that the first direction extends, bulge one side is located on the extension line of second limit place straight line, two sides of bulge with the overlap of third side part, the length on one side of bulge is d1, and d1 is 1.65 ~ 3.5 um.

2. The array substrate of claim 1,

the fretwork portion is including relative fretwork portion one side and the two limits of fretwork portion that set up, fretwork portion one side with two limits of fretwork portion all follow the second direction extends, protruding portion one side with the distance between fretwork portion one side is d2, and d2 is 4.2 ~ 7.6 um.

3. The array substrate of claim 1, wherein the first direction intersects the column direction and the second direction is the row direction.

4. The array substrate of claim 1, wherein the protrusion is a quadrilateral, further comprising three protrusion sides and four protrusion sides, the three protrusion sides extend along the column direction, and an included angle between a straight line where the four protrusion sides are located and the first direction is θ, and θ is 50 ° to 60 °.

5. The array substrate of claim 1, wherein the signal line is electrically connected to the common electrode block through a bridge portion, and the bridge portion is made of the same material as the pixel electrode.

6. The array substrate of claim 1, wherein the pixel electrode is disposed on a side of the common electrode block away from the substrate.

7. The array substrate of claim 1, wherein the pixel electrodes further comprise at least one second strip electrode portion extending along the first direction and arranged in parallel with the first strip electrode portion.

8. The array substrate of claim 1, wherein the common electrode blocks are multiplexed as touch electrode blocks, and the signal lines are used for inputting touch emission signals to the corresponding common electrode blocks and outputting touch sensing signals.

9. A liquid crystal display panel, comprising the array substrate according to any one of claims 1 to 8, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate, wherein the liquid crystal layer is made of a negative liquid crystal.

10. A liquid crystal display device comprising the liquid crystal display panel according to claim 9.