CN113032314A - Cross-platform PCIE link training assisting system and method - Google Patents
Cross-platform PCIE link training assisting system and method Download PDFInfo
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Abstract
The invention discloses a cross-platform auxiliary PCIE link training system and a method thereof, wherein the system comprises: the server comprises a plurality of PCIE card slots; the system comprises a plurality of PCIE cards, wherein each PCIE card comprises an MCU control system, each PCIE card is correspondingly inserted into one PCIE card slot, and the MCU control system of each PCIE card is electrically connected with the server through the corresponding PCIE card slot; the types of the plurality of PCIE cards are the same or different.
Description
Technical Field
The invention relates to the field of computer communication, in particular to a cross-platform auxiliary PCIE link training system and a cross-platform auxiliary PCIE link training method.
Background
With the development of PCIE (Peripheral Component Interconnect Express, a high speed serial computer extended bus standard) related technology, various PCIE adapter cards are also continuously appearing, such as some network cards, AI cards (artificial intelligence accelerator cards), FPGA (Field Programmable Gate Array) cards, video cards, and the like, and need to be used on servers With different architectures, such as an X86 platform, an arm (advanced RISC) platform, an MIPS (Million Instructions Per Second, single-word length instruction average execution speed) platform, a POWER PC (PPC for short, full Performance Optimization With Enhanced-Performance Computing, a central processing unit With a reduced instruction set architecture), and when PCIE cards are used on these servers, problems such as failure in PCIE link compatibility or failure to find a PCIE link training device are also caused. The premise that the PCIE card can normally work is that PCIE link training is completed, and the timing sequence of the PCIE link training needs to establish connection according to the PCIE protocol, and the PCIE link needs to establish connection through a process of link initialization and link training, and meanwhile, this process also determines the width of the link, the link rate, the link inversion, and the link polarity.
The server is more complex than a common PC (personal computer), the server needs to detect various external devices during the starting process, the starting time of the server is usually from several minutes to tens of minutes, and even longer, while the starting time of the common PC is only from tens of seconds to several minutes, so the whole power-on time sequence of the server and the PC is greatly different. Different power-on time sequences result in different time points in the process of performing PCIE link training, for example, a device that can be found on a PCIE card slot of a PC is inserted into a server but cannot be found. The power-on time sequences of servers with different architectures are different, so that, for example, a PCIE card that can be used on the X86 server cannot be detected on the ARM server, and cannot be used. Even if the power-on time sequences of servers produced by different manufacturers under the same architecture are different, the time for performing PCIE link training is different, and a great challenge is brought to the compatibility of PCIE cards. The PCIE card has a PCIE reset signal, the mainboard of the server of different platforms also has a PCIE reset signal, after the server is powered on, the PCIE link training is only carried out after various peripheral equipment configurations are required to be completed, and after the common PCIE card is powered on, the PCIE card is started to enter a working state to carry out the PCIE link training, and the PCIE link training between the PCIE card and the PCIE card can be completed only when the time sequence in a certain time is met.
The prior technical scheme includes that a clock signal and a reset signal time sequence of a PCIE card are captured by an oscilloscope of hardware detection equipment, a PCIE reset signal time sequence and a reset signal time sequence of a server are captured at the same time, and the reset time sequences of the PCIE card and the server are made to accord with a PCIE transmission protocol by referring to the PCIE transmission protocol according to the time sequences of the PCIE transmission protocol and adopting a software or hardware circuit mode. For example, both the hardware delay circuit and the reset circuit may affect the PCIE reset signal, and change the duration of the high and low levels (0 or 1) and the high and low levels (0 or 1) of the reset signal. In this scheme, the server reset signals captured by different platform servers have different time sequence changes, and the PCIE card needs to adjust the reset signal of the PCIE card in order to cooperate with different server platforms, and adjust the high-low level holding time after the PCIE card is powered on and the high-low level at different time points.
However, it takes a long time to perform cross-platform adaptation of a PCIE card in the prior art, the time sequences of PCIE reset and platform reset signals of different platforms are different, a dedicated oscilloscope is required to capture a signal during adaptation, a dedicated device is required to be used in a specific laboratory, the time sequence of capturing a corresponding signal also needs to be analyzed, and the high-low level holding time of the reset signal of the PCIE card is modified from the software and hardware level. The modification on the hardware circuit level needs to be carried out again, the welding debugging of the plate is required to be carried out, the time for the product to be released to the market is increased, different hardware circuits need to be adjusted on different platforms, and the research, development and debugging time is greatly increased; in the software level debugging, software environments and corresponding drivers of different platforms need to be considered, and the debugging difficulty is increased. In addition, the power-on time sequences of the servers of different platforms are inconsistent, so that the training time points of the PCIE links of the servers of different platforms are inconsistent, and even if different manufacturers of the same platform design the servers according to their own requirements, the respective power-on and PCIE link training times are also different, so that the problem of compatibility of the PCIE card on the same platform also occurs. The existing method can only adapt to the power-on time sequence of one server platform at a time, if the server of other platforms is needed to be adapted, the detection adaptation process needs to be repeated, and the adaptation difficulty is increased.
Disclosure of Invention
In order to solve the above problems, the present invention provides a system and a method for cross-platform assisted PCIE link training, which achieve the purpose of assisting PCIE link training by recording PCIE reset signal timing sequences after servers of different platforms are powered on, adjusting a reset signal of a PCIE card, and satisfying the timing sequence specified by a PCIE transmission protocol in combination with PCIE reset signal conditions of the servers. Meanwhile, the problem of compatibility caused by PCIE link training in the process of the PCIE card cross-server platform adaptation is solved, and various PCIE card devices can be found on servers of different platforms.
In order to achieve the above object, the present invention provides a system for cross-platform assisted PCIE link training, including:
the server comprises a plurality of PCIE card slots;
the system comprises a plurality of PCIE cards, wherein each PCIE card comprises an MCU control system, each PCIE card is correspondingly inserted into one PCIE card slot, and the MCU control system of each PCIE card is electrically connected with the server through the corresponding PCIE card slot;
the types of the PCIE cards are the same or different.
In an implementation of the present invention, the types of platform architectures of the server include: an X86 platform, a MIPS platform, an ARM platform, or a POWER PC platform.
In an implementation of the present invention, the types of the PCIE card include an FPGA card, an AI card, a network card, and a display card.
In an implementation of the present invention, a plurality of the servers are connected through a network, where the plurality of servers are servers of the same platform architecture or servers of different platform architectures, and a PCIE card slot of each server is inserted with a PCIE card.
In order to achieve the above object, the present invention provides a cross-platform assisted PCIE link training method, which includes the following steps:
step 1: the server mainboard is powered on and started, and meanwhile any PCIE card is also powered on through the PCIE card slot, and the MCU control system on the corresponding PCIE card is powered on;
step 2: the MCU control system on the PCIE card is communicated with the server mainboard and judges whether the model of the corresponding server platform is recorded or not,
if the record exists, the MCU control system on the PCIE card reads the duration time of the high and low level of the PCIE reset signal of the corresponding server from the memory of the MCU control system, sets the PCIE reset signal of the PCIE card to be consistent with the stored PCIE reset signal time sequence of the server, and then jumps to the step 5;
if no record is recorded, the next step is carried out;
and step 3: the MCU control system respectively detects a PCIE reset signal of the server and a PCIE reset signal of the PCIE card, and simultaneously records the high-low level duration of the PCIE reset signal of the server and the high-low level duration of the PCIE reset signal of the PCIE card;
and 4, step 4: setting the PCIE reset signal of the PCIE card and the PCIE reset signal of the server recorded in the step 3 to be consistent in time sequence,
and 5: it is checked whether the PCIE link training is successful, i.e. whether the server can detect the corresponding PCIE card,
if not successful, returning to the step 1 for retraining;
and if the server is successful, displaying the equipment serial number of the PCIE card on the server, and recording corresponding server information into the MCU control system, wherein the server information comprises the PCIE reset signal high-low level duration time of the server, server CPU information and server hardware platform manufacturer information.
In one implementation of the present invention, in step 1, the server further generates a PCIE reset signal of the motherboard and a voltage of 3.3V or 12V of the motherboard after being powered on, and the PCIE card further generates a reset signal of the PCIE card and a PCIE reset signal of the PCIE card after being powered on.
In one implementation of the present invention, in step 3, the duration of the high and low levels of the PCIE reset signal of the server is the duration of the high and low levels of the PCIE reset signal of the server from the power-on of the server motherboard to the normal operation, and the duration of the high and low levels of the PCIE reset signal of the PCIE card is the duration of the high and low levels of the PCIE reset signal of the PCIE card calculated from the power-on of the server motherboard;
in one implementation of the present invention, the specific process of setting the PCIE reset signal of the PCIE card and the PCIE reset signal of the server to be consistent in time sequence in step 2 and step 4 is as follows:
step 401: the service PCIE reset signal keeps low level after being electrified, and at the moment, the MCU control system keeps the reset signal of the PCIE card and the PCIE reset signal of the PCIE card at low level;
step 402: when the service PCIE reset signal is changed into high level, the MCU control system changes the reset signal of the PCIE card and the PCIE reset signal of the PCIE card into high level.
In an implementation of the present invention, the method further includes:
when a plurality of servers are connected to the same network, after any PCIE card on any server completes PCIE link training of the corresponding server, the MCU control system of the PCIE card can also be connected to other servers through the network to perform PCIE link training of different servers.
Compared with the prior art, the method and the device can adapt to PCIE reset time sequences of different server platforms, assist the PCIE cards to carry out PCIE link training with the server mainboard, realize link training data sharing of cross-platform PCIE cards, and achieve the purpose of training the PCIE cards in batches, thereby improving the efficiency of PCIE link training, enhancing the compatibility of each PCIE card and shortening the adaptation time of the PCIE cards.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a system architecture diagram of one embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a connection between a server and a PCIE card according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a server type according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating types of PCIE cards according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating network connections of a plurality of servers according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a training method according to another embodiment of the present invention.
Description of reference numerals: 100-a server; 101-a PCIE card slot; 200-PCIE card; 201-MCU control system; 15-a server; 16. 17, 18, 19-PCIE card slot; 20. 21, 22, 23-PCIE card; 1-X86 platform; 2-ARM platform; 3-MIPS platform; 4-POWER PC platform; 9-FPGA card; 10-AI card; 11-a network card; 12-display card.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Example one
Fig. 1 is a system architecture diagram of an embodiment of the present invention, and as shown in fig. 1, the embodiment provides a system for cross-platform assisted PCIE link training, including:
a server (100) comprising a plurality of PCIE card slots (101);
the system comprises a plurality of PCIE cards (200), wherein any PCIE card (200) comprises an MCU (Microcontroller Unit) control system (201), each PCIE card (200) is correspondingly inserted into one of the PCIE card slots (101), and the MCU control system (201) of each PCIE card (200) is electrically connected with a server (100) through the corresponding PCIE card slot (101);
wherein, the types of the PCIE cards (200) are the same or different.
The server (100) of this embodiment includes a PCIE card slot (101), the server (100) is connected to the PCIE card (200) through the PCIE card slot (101), and the PCIE card (200) is inserted into the PCIE card slot (101), thereby completing the connection with the server (100) on the physical layer. After the server is powered on, the server can work according to the working time sequence of the server, and PCIE reset signals of the mainboard and 3.3V/12V voltage of the mainboard are generated. The PCIE card (200) is connected and communicated with a mainboard of the server (100) through the PCIE card slot (101), and the PCIE card (200) can generate a board card reset signal and a board card PCIE reset signal after being electrified. An MCU control system (201) is integrated on the PCIE card (200), the MCU control system (201) communicates with the server (100) through the PCIE card slot (101), and the MCU control system (201) can detect PCIE reset signals of a mainboard and the state of 3.3V/12V voltage of the mainboard in the platform power-on starting process and record the high level and low level time of the PCIE signals of the mainboard from power-on to normal work.
Meanwhile, the MCU control system (201) is integrated on the PCIE card (such as an FPGA card, an AI card, a network card, or a display card), and thus can record the high level and the low level duration of the reset signal of the PCIE card (200) and the PCIE reset signal of the PCIE card (200) after being powered on. The MCU control system (201) can also control a reset signal of the PCIE card (200) and a PCIE reset signal of the PCIE card (200), the MCU control system (201) analyzes the time sequence of the PCIE reset signal of the PCIE card (200) and the PCIE reset signal of the server (100) according to a PCIE transmission protocol, and adjusts the reset signal of the PCIE card (200) and the PCIE reset signal of the PCIE card (200), so that the PCIE link training of the PCIE card (200) and the PCIE link training of the platform of the server (100) are successful, and the platform of the server (100) can detect the PCIE card (200) equipment.
Fig. 2 is a schematic diagram illustrating a connection between a server and a PCIE card in an embodiment of the present invention, as shown in fig. 2, in this embodiment, different PCIE cards may be inserted into different PCIE card slots on one server platform, a server (15) includes 4 PCIE card slots (16, 17, 18, and 19), and each PCIE card slot may be inserted with one PCIE card, so that 4 PCIE cards (20, 21, 22, and 23) may be inserted, where the PCIE card slot 16 corresponds to the PCIE card 20, the PCIE card slot 17 corresponds to the PCIE card 21, the PCIE card slot 18 corresponds to the PCIE card 22, and the PCIE card slot 19 corresponds to the PCIE card 23. Each PCIE card may be the same type of card or different types of cards.
Fig. 3 is a schematic diagram of server types according to an embodiment of the present invention, as shown in fig. 3, in this embodiment, the types of platform architectures of the servers include: x86 platform (1), MIPS platform (3), ARM platform (2) or POWER PC platform (4).
Fig. 4 is a schematic diagram illustrating types of PCIE cards in an embodiment of the present invention, as shown in fig. 4, in the embodiment, the types of PCIE cards include an FPGA card (9), an AI card (10), a network card (11), and a display card (12).
In this embodiment, different PCIE card slots on one server platform may be inserted with different PCIE cards, for example, there are four PCIE card slots on the X86 platform, each PCIE card slot may be inserted with four cards, namely, an FPGA card (9), an AI card (10), a network card (11), and a display card (12), the four cards are all integrated with an MCU control system, and after power-on, the MCU control system may train the four cards independently at the same time, therefore, the process of training the PCIE cards by the server is a process of communication adaptation of one of the cards and the inserted server.
Example two
Fig. 5 is a schematic diagram of network connection of multiple servers in another embodiment of the present invention, as shown in fig. 5, in this embodiment, multiple servers (server 1, server 2, server 3, and server 4 … … server n) are connected through a network and used for performing data communication, where the multiple servers (server 1, server 2, server 3, and server 4 … … server n) may be servers with the same platform architecture or servers with different platform architectures, and a PCIE card is inserted into a PCIE card slot of each server, and since each server is connected to the same network, link training of a large number of PCIE cards across platforms may be performed.
EXAMPLE III
Fig. 6 is a schematic diagram of a training method according to another embodiment of the present invention, and as shown in fig. 6, this embodiment provides a method for cross-platform assisted PCIE link training, which is implemented by the training system, and the specific implementation process includes:
step 1: the server mainboard is powered on and started, and meanwhile any PCIE card is also powered on through the PCIE card slot, and the MCU control system on the corresponding PCIE card is powered on;
in this embodiment, in step 1, the server is powered on and then generates a PCIE reset signal of the motherboard and a voltage of 3.3V or 12V of the motherboard, and the PCIE card is powered on and then generates a reset signal of the PCIE card and a PCIE reset signal of the PCIE card.
Step 2: the MCU control system on the PCIE card is communicated with the server mainboard and judges whether the model of the corresponding server platform is recorded or not,
if the record is available, the MCU control system on the PCIE card reads the duration time of the high and low level of the PCIE reset signal of the corresponding server from the memory of the MCU control system, sets the PCIE reset signal of the corresponding PCIE card to be consistent with the stored PCIE reset signal time sequence of the server, and then jumps to step 5, sets the PCIE reset signal of the PCIE card to assist in realizing PCIE link training of the PCIE card, so that the server can detect the PCIE card;
if no record is recorded, the next step is carried out;
and step 3: the MCU control system respectively detects a PCIE reset signal of the server and a PCIE reset signal of the PCIE card, and simultaneously records the high-low level duration of the PCIE reset signal of the server and the high-low level duration of the PCIE reset signal of the PCIE card;
in this embodiment, in step 3, the duration of the high and low levels of the PCIE reset signal of the server is the duration of the high and low levels of the PCIE reset signal of the server from the power-on of the server motherboard to the normal operation, and the duration of the high and low levels of the PCIE reset signal of the PCIE card is the duration of the high and low levels of the PCIE reset signal of the PCIE card calculated from the power-on of the server motherboard;
and 4, step 4: setting the PCIE reset signal of the PCIE card and the PCIE reset signal of the server recorded in the step 3 to be consistent in time sequence,
and 5: it is checked whether the PCIE link training is successful, i.e. whether the server can detect the corresponding PCIE card,
if not successful, returning to the step 1 for retraining;
and if the detection result is successful, displaying the equipment serial number of the PCIE card on the server, and recording the corresponding server information into the MCU control system, wherein the server information comprises the high-low level duration of the PCIE reset signal of the server, the CPU (central processing unit) information of the server and the manufacturer information of the hardware platform of the server.
In this embodiment, the specific process of setting the PCIE reset signal of the corresponding PCIE card and the PCIE reset signal of the server to be consistent in time sequence in step 2 and step 4 is as follows:
step 401: the service PCIE reset signal keeps low level after being electrified, and at the moment, the MCU control system keeps the reset signal of the PCIE card and the PCIE reset signal of the PCIE card at low level, namely the reset state does not work;
step 402: when the service PCIE reset signal is changed into high level, the MCU control system changes the reset signal of the PCIE card and the PCIE reset signal of the PCIE card into high level, thereby realizing the consistency of the PCIE reset signal of the corresponding PCIE card and the PCIE reset signal of the server mainboard.
In this embodiment, one server may train multiple PCIE cards at the same time, and each PCIE card is controlled by the MCU to record a training result. Therefore, one PCIE card can be used for successfully training PCIE links on the servers of the four platforms respectively. The MCU control system acquires CPU information of a platform, manufacturer information of a server hardware platform, PCIE reset signal time for storing the platform and other information through PCIE communication, after training is successful, the PCIE reset signal duration of different corresponding platforms and manufacturers can be recorded, and after the same PCIE card is successfully trained on different platforms, if the same PCIE card is pulled down from one platform and then inserted into other platforms, re-training is not needed. The PCIE card acquires CPU information of the server and corresponding platform information in a power-on process, and then uses the configuration information stored before to implement the PCIE link. According to the PCIE transmission protocol, all the powered PCIE devices need to be link-trained, and can communicate only after successful training, so that the MCU control system can assist link training, thereby shortening the link training time.
Example four
Referring to fig. 5, in this embodiment, when multiple servers are connected to the same network, after any PCIE card on any server completes PCIE link training of the corresponding server, the MCU control system of the PCIE card may also be connected to other servers through the network to perform PCIE link training of different servers.
The MCU control system of each PCIE card firstly realizes the link training of the PCIE card in the server by the aid of the server in which the MCU control system is inserted, records and stores data, and then realizes the PCIE link training of different servers in the whole communication network by the aid of network communication and other servers in the network. Therefore, the link training data of the PCIE cards can be shared and stored, and a large batch of PCIE card cross-platform link training can be realized at the same time.
According to the invention, the MCU control system is added on the PCIE card to control the PCIE card reset signal and the PCIE signal reset signal of the PCIE card so as to adapt to the PCIE reset time sequence of different server platforms, assist the PCIE card and a server mainboard to carry out PCIE link training, and realize the link training data sharing of the cross-platform PCIE card, thereby achieving the purpose of training the PCIE cards in batches, improving the PCIE link training efficiency, enhancing the compatibility of the PCIE card and shortening the adaptation time of the PCIE card.
Those of ordinary skill in the art will understand that: the figures are merely schematic representations of one embodiment, and the blocks or flow diagrams in the figures are not necessarily required to practice the present invention.
Those of ordinary skill in the art will understand that: modules in the devices in the embodiments may be distributed in the devices in the embodiments according to the description of the embodiments, or may be located in one or more devices different from the embodiments with corresponding changes. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. A system for cross-platform assisted PCIE link training, comprising:
the server comprises a plurality of PCIE card slots;
the system comprises a plurality of PCIE cards, wherein each PCIE card comprises an MCU control system, each PCIE card is correspondingly inserted into one PCIE card slot, and the MCU control system of each PCIE card is electrically connected with the server through the corresponding PCIE card slot;
the types of the PCIE cards are the same or different.
2. The system of claim 1, wherein the type of platform architecture of the server comprises: an X86 platform, a MIPS platform, an ARM platform, or a POWER PC platform.
3. The system of claim 1, wherein the types of PCIE cards include FPGA cards, AI cards, network cards, and video cards.
4. The system of claim 1, wherein a plurality of the servers are connected via a network, wherein the plurality of servers are servers of a same platform architecture or servers of different platform architectures, and a PCIE card slot of each server is inserted with a PCIE card.
5. A cross-platform assisted PCIE link training method realized by any one of the systems of claims 1-4, characterized by comprising the following steps:
step 1: the server mainboard is powered on and started, and meanwhile any PCIE card is also powered on through the PCIE card slot, and the MCU control system on the corresponding PCIE card is powered on;
step 2: the MCU control system on the PCIE card is communicated with the server mainboard and judges whether the model of the corresponding server platform is recorded or not,
if the record exists, the MCU control system on the PCIE card reads the duration time of the high and low level of the PCIE reset signal of the corresponding server from the memory of the MCU control system, sets the PCIE reset signal of the PCIE card to be consistent with the stored PCIE reset signal time sequence of the server, and then jumps to the step 5;
if no record is recorded, the next step is carried out;
and step 3: the MCU control system respectively detects a PCIE reset signal of the server and a PCIE reset signal of the PCIE card, and simultaneously records the high-low level duration of the PCIE reset signal of the server and the high-low level duration of the PCIE reset signal of the PCIE card;
and 4, step 4: setting the PCIE reset signal of the PCIE card and the PCIE reset signal of the server recorded in the step 3 to be consistent in time sequence,
and 5: it is checked whether the PCIE link training is successful, i.e. whether the server can detect the corresponding PCIE card,
if not successful, returning to the step 1 for retraining;
and if the server is successful, displaying the equipment serial number of the PCIE card on the server, and recording corresponding server information into the MCU control system, wherein the server information comprises the PCIE reset signal high-low level duration time of the server, server CPU information and server hardware platform manufacturer information.
6. The method according to claim 5, wherein in step 1, the server further generates a PCIE reset signal of the motherboard and a voltage of 3.3V or 12V for the motherboard after being powered on, and the PCIE card further generates a PCIE reset signal of the PCIE card and a PCIE reset signal of the PCIE card after being powered on.
7. The method according to claim 5, wherein in step 3, the duration of the high and low levels of the PCIE reset signal of the server is the duration from power-on of the PCIE reset signal of the server to the high and low levels of normal operation from a server motherboard, and the duration of the high and low levels of the PCIE reset signal of the PCIE card is the duration from the power-on of the PCIE reset signal of the PCIE card that is calculated from the time of the power-on of the server motherboard.
8. The method according to claim 5, wherein the specific process of setting the PCIE reset signal of the PCIE card and the PCIE reset signal of the server to be consistent in time sequence in step 2 and step 4 is as follows:
step 401: the service PCIE reset signal keeps low level after being electrified, and at the moment, the MCU control system keeps the reset signal of the PCIE card and the PCIE reset signal of the PCIE card at low level;
step 402: when the service PCIE reset signal is changed into high level, the MCU control system changes the reset signal of the PCIE card and the PCIE reset signal of the PCIE card into high level.
9. The method of claim 5, further comprising:
when a plurality of servers are connected to the same network, after any PCIE card on any server completes PCIE link training of the corresponding server, the MCU control system of the PCIE card can also be connected to other servers through the network to perform PCIE link training of different servers.
Priority Applications (1)
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| WO2023060928A1 (en) * | 2021-10-14 | 2023-04-20 | 华为技术有限公司 | Method, apparatus, and system for communicating with pcie device |
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