CN115914873A

CN115914873A - Testing device and testing method of multi-node management board

Info

Publication number: CN115914873A
Application number: CN202211217551.4A
Authority: CN
Inventors: 徐志豪
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2023-04-04

Abstract

The embodiment of the application provides a testing device and a testing method of a multi-node management board, relates to the technical field of chip testing, and is used for reducing the number of control nodes when the multi-node management board is tested, so that the material cost is reduced. The test device includes: a control node and a switching unit. The control node is used for generating a test signal; the switching unit is provided with a first signal end and a plurality of second signal ends; the first signal end is electrically connected with the control node, and the plurality of second signal ends are electrically connected with the plurality of node connecting ends in a one-to-one correspondence manner; the switching unit is used for: the test signal is received through the first signal end, and the test signal of the first signal end is transmitted to different second signal ends in a time-sharing mode, so that the plurality of node connecting ends of the multi-node management board can be tested. The testing device is used for testing the multi-node management board.

Description

Testing device and testing method of multi-node management board

Technical Field

The embodiment of the application relates to the technical field of chip testing, in particular to a testing device and a testing method of a multi-node management board.

Background

As the computing demands of users on computers increase, multi-node servers also come into play. A multi-node server refers to a server having a plurality of server nodes.

In addition, a multi-node management board is also arranged in the multi-node server, and one node of the multi-node management board needs to be electrically connected with a main board of one server node. In the prior art, the material cost for testing the multi-node management board is high.

Disclosure of Invention

An object of the embodiments of the present application is to provide a testing apparatus and a testing method for a multi-node management board, which are used to reduce the number of control nodes when testing the multi-node management board, so as to reduce the testing cost.

In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:

in one aspect, a test device board is provided. The test device board is used for testing the multi-node management board; wherein the multi-node management board comprises a plurality of node connection ends. The test device includes: a control node and a switching unit. The control node is used for generating a test signal. The switching unit is provided with a first signal end and a plurality of second signal ends; the first signal end is electrically connected with the control node, and the plurality of second signal ends are electrically connected with the plurality of node connecting ends in a one-to-one correspondence manner; the switching unit is used for: and receiving the test signal through the first signal end, and transmitting the test signal of the first signal end to different second signal ends in a time-sharing manner so as to test a plurality of node connecting ends of the multi-node management board.

In the multi-node management board, the switching unit can transmit the test signal of one control node to different second signal ends in a time-sharing manner, so that the test of a plurality of node connecting ends can be completed only by setting one control node, the number of the control nodes can be reduced, and the material cost of the test device is reduced. In addition, the control node can finish the test of the connecting ends of the nodes only by starting once, so that the starting time of the system is short, and the test time of the multi-node management board is shortened. For example, the control node may comprise a motherboard of the server node.

In some embodiments, the switching unit includes: a switch controller and at least one switch chip. Any one of the switch chips is electrically connected between the first signal end and the plurality of second signal ends. The switch controller is electrically connected with the control node, and the switch controller is electrically connected with the at least one switch chip; the control node is further configured to generate a selection signal; the switch controller is used for controlling at least one switch chip to communicate the first signal end and a second signal end corresponding to the selection signal based on the selection signal.

The switch controller can control the first signal end to be communicated with the second signal end corresponding to the selection signal according to the selection signal, so that the corresponding node connecting end can receive the test signal, and the test signal can be transmitted to the plurality of node connecting ends in a time-sharing mode.

In some embodiments, the kinds of all the switch chips in the switching unit include at least two; the test signal comprises at least two different test sub-signals; one test sub-signal corresponds to one switch chip, and the same test sub-signal can be transmitted to different second signal ends in a time-sharing manner through the corresponding switch chip.

By enabling the same type of test sub-signals to be transmitted to different second signal ends in a time-sharing manner through the corresponding switch chips, mutual interference among different types of test sub-signals can be avoided.

In some embodiments, the at least one switch chip includes a first switch chip and a second switch chip; the first switch chip and the second switch chip are different in type; the first signal end comprises a first interface group and a second interface group, and the first switch chip is electrically connected to the control node through the first interface group; the second switch chip is electrically connected to the control node through the second interface group; each second signal terminal comprises a third interface group and a fourth interface group; the first switch chip is connected to each node connection terminal through each third interface group, and the second switch chip is connected to each node connection terminal through each fourth interface group.

The first switch chip transmits the signal received by the first interface group to the third interface group, and the second switch chip transmits the signal received by the second interface group to the fourth interface group, so that the signal received by the first interface group and the signal received by the second interface group can be transmitted on different switch chips, and mutual interference between the signal received by the first interface group and the signal received by the second interface group can be avoided.

In some embodiments, the first interface group and the third interface group each include at least one high speed interface for transmitting high speed sub-signals; the second interface group and the fourth interface group both comprise at least one low-speed interface, and the low-speed interfaces are used for transmitting low-speed sub-signals.

The high-speed sub-signals are transmitted through the first switch chip, and the low-speed sub-signals are transmitted through the second switch chip, so that the high-speed sub-signals and the low-speed sub-signals can be prevented from being transmitted on the same switch chip, and further the high-speed sub-signals and the low-speed sub-signals can be prevented from being greatly interfered.

In some embodiments, the first interface group and the third interface group each include: at least one of a Serial Gigabit Media Independent Interface (SGMII) Interface and a Universal Serial Bus (USB) Interface. The second interface group and the fourth interface group each include: at least one of an I2C (Inter-Integrated Circuit) interface, an MDIO (Management Data Input/Output) interface, a JTAG (Joint Test Action Group) interface, a GPIO (General-Purpose Input/Output) interface, a UART (Universal Asynchronous Receiver/Transmitter) interface, and a VGA (Video Graphics Array) interface.

In some embodiments, the control node comprises a management control unit and a processing unit electrically connected to the management control unit; the control node comprises a first interface group electrically connected with the management control unit and a second interface group electrically connected with the processing unit; the test signals comprise a first test signal and a second test signal; the management control unit is used for generating the first test signal and outputting the first test signal by the first interface group; the management control unit is further used for controlling the processing unit to generate the second test signal and outputting the second test signal by the second type interface group.

The types of the interfaces connected with the management control unit and the processing unit are different, so that more interfaces can be arranged in the control node by arranging the management control unit and the processing unit in the control node, more interfaces in the node connecting end can be tested, and the test result of the multi-node pipe vertical plate is more reliable.

In some embodiments, the first type interface group comprises: at least one of an I2C interface, a UART interface, an MDIO interface, a VGA interface, an SGMII interface and a USB interface; the second type interface group comprises: at least one of a GPIO interface and a JTAG interface.

In some embodiments, the Management control unit includes a BMC (Baseboard Management Controller) chip; the processing unit includes a CPLD (Complex Programmable Logic Device) chip.

In another aspect, a method for testing a multi-node management board is provided. The test method of the multi-node management board comprises the following steps: the plurality of second signal terminals of the testing device provided in some embodiments above are electrically connected to the plurality of node connection terminals of the multi-node management board in a one-to-one correspondence. A control node of the test device generates a test signal. And the switching unit of the test device transmits the test signals to each node connecting end in sequence so as to test the plurality of node connecting ends of the multi-node management board.

In the testing method of the multi-node management board, the switching unit can transmit the testing signal to different second signal ends in a time-sharing manner, so that the testing of the plurality of node connecting ends can be completed by only arranging one control node, the number of the control nodes can be reduced, and the material cost of the testing device is reduced.

In some embodiments, the method for testing a multi-node management board further comprises: the control node generates a plurality of selection signals. The step of the switching unit of the test device sequentially transmitting the test signal to each node connection end comprises: and the switch controller controls each switch chip to communicate with the first signal end and the second signal end corresponding to the selection signal according to the selection signal so as to sequentially transmit the test signal to the plurality of node connecting ends.

Drawings

In order to more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to these drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, according to the embodiments of the present application.

FIG. 1 is a block diagram of a motherboard electrically connected to a fan management board according to the prior art;

FIG. 2 is a block diagram of a test apparatus according to some embodiments electrically connected to a multi-node management board;

FIG. 3 is a block diagram of a control node of the test apparatus provided in FIG. 2, including a management control unit and a processing unit;

FIG. 4 is a block diagram of a switching unit of the testing apparatus shown in FIG. 2, which includes a switch controller and a switch chip;

FIG. 5 is a block diagram of a switching unit of the testing apparatus shown in FIG. 2 including four second signal terminals;

FIG. 6 is a block diagram of a switching unit of the testing apparatus shown in FIG. 2 including two switch chips;

FIG. 7 is a block diagram of the switch chip of FIG. 4 including a plurality of conductive via sets;

FIG. 8 is an internal circuit diagram of a MAX14979 chip;

FIG. 9 is an internal circuit diagram of a MAX333 chip;

FIG. 10 is a block diagram of a control node of the test apparatus provided in FIG. 4, including a management control unit and a processing unit;

FIG. 11 is a flow diagram of a method of testing a multi-node management board according to some embodiments;

FIG. 12 is another flow diagram of a method of testing a multi-node management board provided in accordance with some embodiments;

FIG. 13 is a block diagram of a connection structure of a test device, a multi-node management board, and an external device according to some embodiments.

Detailed Description

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. The schematic representations of the terms used above are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present application, "a plurality" means two or more unless otherwise specified.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

The fan management board is an indispensable board card in the server, is mainly responsible for controlling the fan, and simultaneously can also be used as a patch board between the mainboard and an external connection, namely the mainboard can be electrically connected to external equipment through the fan management board.

For a multi-node server, the fan management board needs to interface with multiple motherboards. The fan management board is provided with a plurality of node connecting ends, and one node connecting end is used for being in butt joint with one main board.

Before the fan management board is assembled in the electronic equipment, the fan management board needs to be tested, and the fan management board passing the test can be assembled in the electronic equipment, so that the phenomenon that the fan management board in the electronic equipment fails is improved.

Fig. 1 is a block diagram illustrating a structure of a motherboard electrically connected to a fan management board according to the prior art.

Referring to fig. 1, in the prior art, when testing a fan management board, a plurality of main boards are used to be respectively connected to a plurality of node connection ends of the fan management board, for example, if the fan management board has two node connection ends, two main boards are required to be respectively electrically connected to the two node connection ends. Wherein, a plurality of mainboards can generate test signal respectively to transmit respectively to a plurality of node link ends, test a plurality of node link ends with this, thereby accomplish the test of fan management board.

Therefore, in the prior art, when testing the fan management board, a plurality of motherboards need to be used, which results in a large number of motherboards and a high testing cost. In addition, when the fan management board is tested, the test systems in the mainboards are respectively started, so that the test time of the fan management boards is longer.

Based on this, embodiments of the present application provide a test apparatus 200.

FIG. 2 is a block diagram of a test apparatus 200 electrically connected to the multi-node management board 100 according to some embodiments.

Referring to FIG. 2, the testing apparatus 200 is used for testing the multi-node management board 100. Wherein the multi-node management board 100 includes a plurality of node connection terminals 110. In some examples, the multi-node management board 100 may be a fan management board.

The test apparatus 200 may include a control node 210 and a switching unit 220. The switching unit 220 has a first signal terminal 221 and a plurality of second signal terminals 222. The first signal terminal 221 is electrically connected to the control node 210, and the plurality of second signal terminals 222 are electrically connected to the plurality of node connection terminals 110 in a one-to-one correspondence. The switching unit 220 is configured to: the test signal is received through the first signal terminal 221, and the test signal of the first signal terminal 221 is transmitted to the different second signal terminal 222 in a time-sharing manner, so as to test the plurality of node connection terminals 110 of the multi-node management board 100.

The control node 210 stores a test program therein, and the control node 210 may generate a test signal according to the test program. The test signal generated by the control node 210 may be used to test each node connection 110.

Illustratively, the control node 210 may comprise a motherboard of a server node.

Illustratively, the switching unit 220 may be, for example, a switching circuit board.

The plurality of second signal terminals 222 are electrically connected to the plurality of node connection terminals 110 in a one-to-one correspondence, and therefore, the number of the second signal terminals 222 and the number of the node connection terminals 110 may be the same, and the number of the second signal terminals 222 is not limited in the embodiments of the present application. In fig. 2, the test apparatus 200 provided in some embodiments of the present application is illustrated with the switching unit 220 including two second signal terminals 222.

In some examples, the control node 210 may include an interface, and correspondingly, the first signal terminal 221 may include an interface, each of the second signal terminals 222 may include an interface, and each of the node connection terminals 110 may include an interface.

In other examples, the control node 210 may include a plurality of interfaces, and correspondingly, the first signal terminal 221 also includes a plurality of interfaces, each of the second signal terminals 222 also includes a plurality of interfaces, and the node connection terminal 110 also includes a plurality of interfaces. In this case, the test signal may include a plurality of test sub-signals, one interface of the control node 210 may be used to transmit one test sub-signal, and one interface of each node connection terminal 110 may be used to receive one test sub-signal.

The control node 210, the first signal terminal 221, each second signal terminal 222 and each node connection terminal 110 include interfaces corresponding to each other, i.e. the types and the number of the included interfaces may be the same.

For example, if the control node 210 includes a plurality of USB interfaces, the first signal terminal 221 and each second signal terminal 222 also include a plurality of USB interfaces, and the number of USB interfaces in the first signal terminal 221 and each second signal terminal 222 is the same as the number of USB interfaces in the control node 210. At this time, the control node 210 may test the multi-node management board 100 including a plurality of USB interfaces in each node connection terminal 110.

In this example, the interfaces in each node connection terminal 110 may be different, and in this case, the test sub-signals received by the interfaces may be different. Furthermore, it is also possible that some of the interfaces of one node connecting terminal 110 may be the same interface, wherein a plurality of the same interfaces may receive the same test sub-signal or different test sub-signals.

In some examples, the plurality of node connecting ends 110 are identical, and each node connecting end 110 includes the same type and number of interfaces. It is understood that each of the second signal terminals 222 is identical because the plurality of second signal terminals 222 are connected to the plurality of node connection terminals 110 in a one-to-one correspondence. At this time, the plurality of test sub-signals received by each node connection terminal 110 may be the same.

The control node 210 is electrically connected to the first signal terminal 221, so that the first signal terminal 221 can receive the test signal transmitted by the control node 210.

In some examples, the switching unit 220 may electrically connect the different second signal terminals 222 to the first signal terminal 221 respectively, so as to transmit the test signal received by the first signal terminal 221 to the different second signal terminals 222 in a time-sharing manner, where the time-sharing transmission of the test signal to the different second signal terminals 222 may be understood as that the test signal may not be sent to the plurality of second signal terminals 222 at the same time.

The plurality of second signal terminals 222 are respectively in one-to-one correspondence with and electrically connected to the plurality of node connection terminals 110, so that the plurality of node connection terminals 110 can receive the test signals from the plurality of second signal terminals 222. Therefore, the switching unit 220 can send the test signal sent by one control node 210 to the plurality of node connecting terminals 110, so as to test the plurality of node connecting terminals 110 and test the multi-node management board 100.

In the test apparatus 200, the switching unit 220 can transmit the test signal of one control node 210 to the different second signal terminals 222 in a time-sharing manner, so that the test of the plurality of node connection terminals 110 can be completed by only providing one control node 210, thereby reducing the number of control nodes 110 and reducing the test cost. In addition, the control node 210 can complete the testing of the plurality of node connecting terminals 110 only by starting once, so that the starting time of the system is short, and the testing time of the multi-node management board 100 is shortened.

The following describes control node 210.

Fig. 3 is a block diagram illustrating a structure of a control node 210 of the testing apparatus 200 shown in fig. 2, which includes a management control unit 212 and a processing unit 213.

Referring to fig. 3, in some embodiments, the control node 210 includes a management control unit 212 and a processing unit 213 electrically connected to the management control unit 212.

In some examples, the management control unit 212 may include a BMC chip.

In some examples, the processing unit 213 may include a CPLD chip. The CPLD chip is programmable, high in flexibility, low in power consumption and low in cost.

In some examples, the management control unit 212 and the processing unit 213 may be integrated on a motherboard.

The control node 210 includes a first type interface group 214 electrically connected to the management control unit 212. The test signal includes a first test signal. The management control unit 212 is configured to generate a first test signal and output the first test signal by the first type interface group 214, wherein the first type interface group 214 may be electrically connected to the first signal terminal 221, so that the first signal terminal 221 receives the first test signal.

In some examples, the first type interface group 214 may include one or more interfaces, and correspondingly, the first test signal includes one or more test sub-signals.

In some examples, the plurality of interfaces included in the first class interface group 214 may all be high-speed interfaces, and in this case, the test sub-signals included in the first test signal all are high-speed sub-signals, where the high-speed interfaces are used for transmitting the high-speed sub-signals. Illustratively, the high-speed sub-signals may be high-speed differential signals.

In other examples, the one or more first interfaces included in the first type interface group 214 may also be all low-speed interfaces, and in this case, the plurality of test sub-signals included in the first test signal are all low-speed sub-signals, where the low-speed interfaces are used for transmitting the low-speed sub-signals. For example, the low-speed sub-signal may be a low-speed single-ended signal.

In other examples, the first type interface set 214 may include both high-speed and low-speed interfaces, and in this case, the first test signal includes both high-speed and low-speed sub-signals.

In some embodiments, the first type interface group 214 includes: at least one of an I2C interface, a UART interface, an MDIO interface, a VGA interface, an SGMII interface, and a USB interface. The I2C interface, the UART interface, the MDIO interface and the VGA interface are high-speed interfaces, and the SGMII interface and the USB interface are low-speed interfaces.

In some examples, the plurality of interfaces of the first-type interface group 214 are integrated on a motherboard.

In some embodiments, the control node 210 further includes a second type interface set 215 electrically connected to the processing unit 213, the test signal further includes a second test signal, the management control unit 212 is further configured to control the processing unit 213 to generate the second test signal and output the second test signal by the second type interface set 215, and the second type interface set 215 is electrically connected to the first signal terminal 221 so that the first signal terminal 221 receives the second test signal.

In some examples, the second type interface set 215 may include one or more first interfaces, and correspondingly, the second test signal includes one or more test sub-signals. For example, the second type interface group 215 may include interfaces different from those included in the first type interface group 214.

In some examples, the plurality of first interfaces included in the second type interface set 215 may all be high-speed interfaces, and in this case, the test sub-signals included in the second test signal are all high-speed sub-signals.

In other examples, the plurality of first interfaces included in the second type interface set 215 may also be all low-speed interfaces, and in this case, the plurality of test sub-signals included in the second test signal are all low-speed sub-signals.

In other examples, the second type of interface set 215 may include both high-speed interfaces and low-speed interfaces, and in this case, the second test signal includes both high-speed sub-signals and low-speed sub-signals.

In some embodiments, the second type interface group 215 includes: at least one of a GPIO interface and a JTAG interface. And the GPIO interface and the JTAG interface are low-speed interfaces.

In some examples, the interfaces included in the second type interface group 215 may be integrated on a motherboard.

In some embodiments described above, the types of the interface to which the management control unit 212 is connected and the interface to which the processing unit 213 is connected are different, and therefore, by providing the management control unit 212 and the processing unit 213 in the control node 210, more interfaces can be provided in the control node 210, so that more interfaces in the node connection terminal 110 can be tested, and the test result of the multi-node management board 100 is more reliable.

In some of the above embodiments, the control node 210 is described, followed by the switching unit 220.

Fig. 4 is a block diagram of the switching unit 220 of the testing apparatus 200 provided in fig. 2, which includes a switch controller 223 and a switch chip 224. Fig. 4 illustrates an example of a switch chip 224.

Referring to fig. 4, in some embodiments, the switching unit 220 includes: a switch controller 223 and at least one switch chip 224. The switch controller 223 is electrically connected to the at least one switch chip 224, that is, the switch controller 223 may be electrically connected to all switch chips 224, thereby controlling all switch chips 224. Any one of the switch chips 224 is electrically connected between the first signal terminal 221 and the plurality of second signal terminals 222. The number of the switch chips 224 is not limited in the embodiment of the application. In fig. 4, some embodiments of the present application are illustrated by an example in which the switching unit 220 includes one switch chip 224.

In some examples, the switch controller 223 and the at least one switch chip 224 may be disposed on one circuit board.

Control node 210 is also configured to generate a select signal, and switch controller 223 is electrically coupled to control node 210 to receive the select signal. The switch controller 223 is configured to control at least one switch chip 224 to communicate the first signal terminal 221 and the second signal terminal 222 corresponding to the selection signal based on the selection signal, so that the test signal can be transmitted from the first signal terminal 221 to any one of the second signal terminals 222, and the corresponding node connection terminal 110 can receive the test signal.

The at least one switch chip 224 may enable any one of the second signal terminals 222 to be conducted with the first signal terminal 221, wherein the plurality of second signal terminals 222 are conducted with the first signal terminal 221 at different time instants, so that the plurality of second signal terminals 222 receive the test signal at different time instants.

In a case where the first signal terminal 221 and each of the second signal terminals 222 include a plurality of interfaces, the switch controller 223 may control at least one switch chip 224 according to the selection signal, so that all the interfaces of the second signal terminals 222 corresponding to the selection signal are electrically connected to all the interfaces of the first signal terminal 221 in a one-to-one correspondence manner, and thus the plurality of test sub-signals are respectively transmitted to the plurality of interfaces of the second signal terminals 222.

The switch controller 223 may generate a control command based on the selection signal and transmit the control command to the switch chip 224, thereby controlling the switch chip 224. At this time, the switch controller 223 may transmit a control instruction to at least part of the switch chips 224, thereby controlling at least part of the switch chips 224.

In some examples, the switch controller 223 may be an IO (Input/Output) expansion chip, wherein the IO expansion chip may have a plurality of IO pins, and the switch controller 223 may be electrically connected to the control node 210 through at least some of the plurality of IO pins. For example, the IO pin of the switch controller 223 may be electrically connected to the control node 210 through an I2C bus. For example, the switch controller 223 may be a PCA9555 chip, the PCA9555 chip having 16 IO pins.

Illustratively, the selection signal is a level signal, and the control node 210 sends a different level signal to the IO pin of the switch controller 223, so that the level of the IO pin of the switch controller 223 changes. The switch controller 223 can control each switch chip 224 according to different level signals, so that different second signal terminals 222 are electrically connected to the first signal terminal 221.

In some examples, the number of select signals may be the same as the number of second signal terminals 222. In the example given in fig. 4, the number of the second signal terminals 222 is two, and the number of the node connection terminals 110 is two, in which case the control node 210 can generate two selection signals.

Some embodiments of the present application are described below based on an example in which the number of the second signal terminals 222 is two.

Referring to fig. 4, in some examples, the plurality of second signal terminals 222 of the switching unit 220 include a first second signal terminal 222A and a second signal terminal 222B, and the plurality of node connection terminals 110 of the multi-node management board 100 include a first node connection terminal 110A and a second node connection terminal 110B.

Control node 210 may generate a first select signal corresponding to a first one of second signal terminals 222A and first node connection 110A, and a second select signal corresponding to a second one of second signal terminals 222B and second node connection 110B.

When the switch controller 223 receives the first selection signal, the first signal terminal 221 may be controlled to be electrically connected to the first second signal terminal 222A, so that the test signal may be transmitted to the first second signal terminal 222A, and thus to the first node connection terminal 110A.

When the switch controller 223 receives the second selection signal, the first signal terminal 221 and the second signal terminal 222B can be controlled to be electrically connected, so that the test signals can be respectively transmitted to the second signal terminal 222B and then to the second node connection terminal 110B.

In the case where the number of the second signal terminals 222 is two, one of the first selection signal and the second selection signal may be a high level signal, and the other may be a low level signal. Wherein the level of the high level signal is higher than the level of the low level signal. The control node 210 may be electrically connected to one IO pin of the switch controller 223.

The number of the second signal terminals 222 may be two, or may be 4, 8, or more, which is not listed here, and some embodiments of the present application will be described below by taking the number of the second signal terminals 222 as 4 as an example.

Fig. 5 is a block diagram illustrating a structure of the switching unit 220 of the testing apparatus 200 shown in fig. 2 including four second signal terminals 222.

Referring to fig. 5, the switching unit 220 includes four second signal terminals 222, and the testing apparatus 200 can test the multi-node management board 100 having four node connection terminals 110. When the multi-node management board 100 is tested, the four second signal terminals 222 may be in one-to-one correspondence with and electrically connected to the four node connection terminals 110. At this time, the control node 210 may generate four selection signals.

In the case where the number of the second signal terminals 222 is four, the selection signal may include two level signals, and at this time, two IO pins of the switch controller 223 may be electrically connected to the control node 210, so that the two IO pins may receive the level signals. At this time, the IO pin of the switch controller 223 may be recorded as 1 if receiving a high level signal, and may be recorded as 0 if the IO pin of the switch controller 223 receives a low level signal. In this example, the signal received by the switch controller 223 may include the following four cases: 00. 01, 10, 11. The above four cases correspond to four selection signals, respectively.

In the case that the number of the node connection terminals 110 is 8, three IO pins of the switch controller 223 may be used for receiving level signals, and in this case, the signals received by the switch controller 223 may include the following eight cases: 000. 010, 001, 011, 100, 101, 110, 111, the above eight cases correspond to eight selection signals, respectively.

When the number of the second signal terminals 222 is greater than 2, the switch chip 224 may include a multiplexer.

In some embodiments, all the switch chips 224 in the switching unit 220 include at least two kinds, and the at least two kinds of switch chips 224 are respectively used for transmitting different kinds of test sub-signals.

The test signal comprises at least two different test sub-signals. One test sub-signal corresponds to one switch chip 224, and the same test sub-signal can be transmitted to different second signal terminals 222 in a time-sharing manner through the corresponding switch chip 224.

Wherein, the number of each switch chip 224 is plural, and each test sub-signal may include a plurality of different test sub-signals.

Illustratively, the at least two different test sub-signals include a high-speed sub-signal and a low-speed sub-signal, and one of the at least two switch chips 224 is used for transmitting the high-speed sub-signal and the other is used for transmitting the low-speed sub-signal. Illustratively, the high-speed sub-signals are high-speed differential signals, and the low-speed sub-signals are low-speed single-ended signals. The high-speed sub-signals are transmitted on the two wires, and the amplitudes of the signals transmitted by the two wires are equal and the phases of the signals are opposite. The low-speed sub-signal only uses one line to transmit signal, and adds a reference line, namely a ground line.

The number of high-speed sub-signals in all the test sub-signals may be one or more, and the number of low-speed sub-signals in all the test sub-signals may also be one or more.

In some examples, the same kind of test sub-signals can be time-shared to different second signal terminals 222 through the corresponding switch chips 224, so that mutual interference between different kinds of test sub-signals can be avoided.

Fig. 6 is a block diagram of a switching unit 220 of the testing apparatus 200 shown in fig. 2 including two switch chips 224.

Referring to fig. 6, the at least one switch chip 224 includes a first switch chip 224A and a second switch chip 224B; the first switch chip 224A and the second switch chip 224B are different in kind. The first signal terminal 221 includes a first interface group 2211, and the first switch chip 224A is electrically connected to the control node 210 through the first interface group 2211. Each of the second signal terminals 222 includes a third interface group 2221, and the first switch chip 224A is connected to the respective node connection terminal 110 through the respective third interface group 2221.

Therefore, the first switch chip 224A is electrically connected between the first signal terminal 221 and each of the third interface groups 2221. Each of the third interface groups 2221 is electrically connected to a different node connection terminal 110.

The first signal terminal 221 includes a second interface group 2212, and the second switch chip 224B is electrically connected to the control node 210 through the second interface group 2212; each second signal terminal 222 includes a fourth interface group 2222; the second switch chip 224B is connected to each node connection terminal 110 through each fourth interface group 2222. Therefore, the second switch chip 224B is electrically connected between the second interface group 2212 and each fourth interface group 2222. Wherein each fourth interface group 2222 is electrically connected to a different node connection terminal 110, respectively.

In the switching unit 220, the first switch chip 224A transmits the signal received by the first interface group 2211 to the third interface group 2221, and the second switch chip 224B transmits the signal received by the second interface group 2212 to the fourth interface group 2222, so that the signal received by the first interface group 2211 and the signal received by the second interface group 2212 can be transmitted on different switch chips 224, and thus mutual interference between the signal received by the first interface group 2211 and the signal received by the second interface group 2212 can be avoided.

In some embodiments, first interface group 2211 and third interface group 2221 each include at least one high-speed interface for transmitting high-speed sub-signals. The high-speed interfaces included in the first interface group 2211 and the third interface group 2221 are the same in number and are in one-to-one correspondence.

The second interface group 2212 and the fourth interface group 2222 each include at least one low-speed interface for transmitting low-speed sub-signals. The number of low-speed interfaces included in the second interface group 2212 and the fourth interface group 2222 is the same, and they correspond to each other one by one.

The high-speed sub-signal is transmitted through the first switch chip 224A, and the low-speed sub-signal is transmitted through the second switch chip 224B, so that the high-speed sub-signal and the low-speed sub-signal can be prevented from being transmitted on the same switch chip 224, and further, the high-speed sub-signal and the low-speed sub-signal can be prevented from being interfered greatly.

In some embodiments, first interface group 2211 and third interface group 2221 each include therein: at least one of an SGMII interface and a USB interface.

Each of the second interface group 2212 and the fourth interface group 2222 includes: at least one of an I2C interface, an MDIO interface, a JTAG interface, a GPIO interface, a UART interface, and a VGA interface.

Fig. 7 is a block diagram illustrating a structure of the switch chip 224 provided in fig. 4 including a plurality of conductive paths 2241.

Referring to fig. 7, the at least one switch chip 224 may include a plurality of conductive path sets 2241, and one conductive path set 2241 includes a plurality of conductive paths, where each conductive path has two states of on and off, and in fig. 7, an example in which one conductive path set 2241 includes two conductive paths is taken to illustrate some embodiments of the present application. Further, in the example illustrated in fig. 7, two conductive path groups 2241 are located in the same switch chip 224.

In some examples below, for convenience of description, an interface of the control node 210 is defined as a first interface, an interface of the first signal terminal 221 is defined as a second interface, an interface of the second signal terminal 222 is defined as a third interface, and an interface of the node connection terminal 110 is defined as a fourth interface.

Wherein the number of conductive paths in one set 2241 of conductive paths may be the same as the number of second signal terminals 222. The number of sets of conductive paths included in the at least one switch chip is the same as the number of second interfaces in one second signal terminal 222.

One end of each of the plurality of conductive paths of one conductive path group 2241 may be electrically connected to a second interface of the first signal terminal 221, and the other end of each of the plurality of conductive paths may be electrically connected to a plurality of third interfaces, respectively, where the second interface and the third interface electrically connected to one conductive path group 2241 are the same interface. The plurality of third interfaces electrically connected to one conductive path group 2241 are respectively located in the plurality of second signal terminals 222, the plurality of third interfaces electrically connected to one conductive path group 2241 may be defined as a group of third interfaces, and the plurality of fourth interfaces electrically connected to the group of third interfaces are respectively located in the plurality of node connection terminals 110.

When the switch controller 223 receives a selection signal, it may control a conduction path corresponding to the selection signal in each conduction path group 2241, where the conduction path conducted in each conduction path group 2241 is electrically connected to the same second signal end 222, so that multiple third interfaces in the second signal end 222 may receive the test sub-signal, and the node connection end 110 corresponding to the selection signal may receive the test signal.

Illustratively, where the second signal terminal 222 includes a first second signal terminal 222A and a second signal terminal 222B, each conductive path set 2241 includes a first conductive path electrically connected to the third interface in the first second signal terminal 222A and a second conductive path electrically connected to the interface in the second signal terminal 222B.

When the switch controller 223 receives the first selection signal, the switch controller 223 may control the first conductive paths electrically connected to the plurality of conductive path groups 2241 to be conducted, so that the plurality of second interfaces of the first signal terminal 221 are electrically connected to the plurality of third interfaces of the first second signal terminal 222A, respectively. When the switch controller 223 receives the second selection signal, the switch controller 223 can control the second conductive paths electrically connected to the plurality of conductive path sets 2241 to be conducted, so that the plurality of second interfaces of the first signal terminal 221 are electrically connected to the plurality of third interfaces of the second signal terminal 222B, respectively.

Some of the above examples are described below with the MDIO interface and the VGA interface as examples.

Referring to fig. 7, for example, the control node 210 includes a first MDIO interface, and correspondingly, the first signal terminal 221 includes a second MDIO interface, any one of the second signal terminals 222 includes a third MDIO interface, and any one of the node connection terminals 110 includes a fourth MDIO interface. Wherein the second MDIO interface may belong to a second interface group 2212 (shown in fig. 6), and the third MDIO interface may be located in a fourth interface group 2222 (shown in fig. 6).

One set of conductive paths 2241 includes a first conductive path and a second conductive path, wherein one end of the first conductive path and one end of the second conductive path are electrically connected to the second MDIO interface in the first signal terminal 221, the other end of the first conductive path is electrically connected to the third MDIO interface in the first second signal terminal 222A, and the other end of the second conductive path is electrically connected to the third MDIO interface in the second signal terminal 222B.

Illustratively, the control node 210 includes a first VGA interface, and correspondingly, the first signal terminal 221 includes a second VGA interface, any one of the second signal terminals 222 includes a third VGA interface, and any one of the node connection terminals 110 includes a fourth VGA interface. One end of each of the plurality of conductive paths in the another conductive path group 2241 is electrically connected to the second VGA interface in the first signal terminal 221, and the other end is electrically connected to the third VGA interface in the plurality of second signal terminals 222, respectively. Wherein the second VGA interface can belong in a second interface group 2212 (shown in fig. 6), and the third VGA interface can be located in a fourth interface group 2222 (shown in fig. 6).

In yet another set 2241 of conductive paths, one end of the first conductive path and one end of the second conductive path are electrically connected to the second VGA interface in the first signal terminal 221, while the other end of the first conductive path is electrically connected to the third VGA interface in the first second signal terminal 222A, while the other end of the second conductive path is electrically connected to the third VGA interface in the second signal terminal 222B.

When the switch controller 223 receives the first selection signal, the switch controller 223 may control the conduction of the first conductive paths electrically connected to the plurality of conductive path groups 2241, the second MDIO interface is electrically connected to the third MDIO interface in the first second signal terminal 222A, and the second VGA interface is electrically connected to the third VGA interface in the first second signal terminal 222A.

When the switch controller 223 receives the second selection signal, the switch controller 223 may control the conduction of the second conductive paths electrically connected to the plurality of conductive path groups 2241, the second MDIO interface is electrically connected to the third MDIO interface in the second signal terminal 222B, and the second VGA interface is electrically connected to the third VGA interface in the second signal terminal 222B.

It should be noted that, in the example given in fig. 7, only the MDIO interface and the VGA interface are used to illustrate some embodiments of the present application, and in some embodiments of the present application, the control node 210, the first signal terminal 221 and the second signal terminal 222 may further include other interfaces, which are not listed here. In the example given in fig. 7, the switch chip 224 may be a second switch chip 224B.

The conductive paths of one conductive path group 2241 may be disposed on the same switch chip 224, or may be disposed on different switch chips 224.

In some examples, in one set 2241 of conducting paths, each conducting path is provided with a switch, and the switch controller 223 can control the on or off of the switch to control the conducting path to be turned on or off.

In other examples, one or more single pole, multiple throw switches may be included in one conductive path group 2241. For example, the single pole, multiple throw switch may be a single pole, double throw switch. For example, in a case that one conductive path group 2241 includes two conductive paths, the one conductive path group 2241 may include a single-pole double-throw switch, where a fixed terminal of the single-pole double-throw switch is electrically connected to a second interface (e.g., the second MDIO interface), and two moving terminals of the single-pole double-throw switch are electrically connected to a third interface (e.g., the third MDIO interface) corresponding to the second interface, respectively, of the two second signal terminals 222, so as to form two conductive paths between the second interface and the third interface corresponding to the second interface. At this time, the test apparatus 200 may test the multi-node management board 100 having two node connection terminals 110.

For example, the single-pole, multiple-throw switch may be a single-pole, multiple-throw analog switch. Illustratively, the single-pole double-throw switch is a single-pole double-throw analog switch.

Next, a specific example of the switch chip 224 will be described.

Fig. 8 is an internal circuit diagram of a MAX14979 chip.

Referring to fig. 8 and also to fig. 6, for example, the first switch chip 224A may be a MAX14979 chip. The first switch chip 224A is not limited to the MAX14979 chip, and may be an analog switch chip of another model, which is not listed here.

The switch controller 223 may be electrically connected to the SEL pin, so as to control a plurality of switches in the MAX14979 chip.

Next, taking the SGMII interface as an example, and the number of the second signal terminals 222 is two, the connection relationship between the first interface group 2211, the third interface group 2221, and the MAX14979 chip will be described.

Illustratively, the first interface group 2211 includes a second SGMII interface. The number of the second signal terminals 222 is two, so the number of the third interface group 2221 is two, and one third interface group 2221 includes one third SGMII interface, so the number of the third SGMII interface is two.

The positive end of the second SGMII interface can be electrically connected to a COM0+ pin, the negative end of the second SGMII interface can be electrically connected to a COM 0-pin, the positive end of one of the two third SGMII interfaces is electrically connected to an NC0+ pin, the negative end of the one of the two third SGMII interfaces is electrically connected to an NC 0-pin, the positive end of the other of the two third SGMII interfaces is electrically connected to an NO0+ pin, and the negative end of the other of the two third SGMII interfaces is electrically connected to an NO 0-pin.

Fig. 9 is an internal circuit diagram of a MAX333 chip.

Referring to fig. 9 and also to fig. 6, the second switch chip 224B may be a MAX333 chip. The second switch chip 224B is not limited to the MAX333 chip, and may be an analog switch chip of another model, which is not listed here.

The switch controller 223 may be electrically connected to any one of the IN1 pin, the IN2 pin, the IN3 pin, and the IN4 pin, so as to control a plurality of switches IN the MAX333 chip.

In the following, taking VGA interfaces as an example, and the number of the second signal terminals 222 is two, the connection relationship between the second interface group 2212 and the fourth interface group 2222 to the MAX333 chips is described.

Illustratively, the second interface group 2212 includes one second VGA interface, and the number of the second signal terminals 222 is two, so the number of the fourth interface group 2222 is two, and the one fourth interface group 2222 includes one third VGA interface, so the number of the third VGA interfaces is two.

Wherein the second VGA interface can be electrically connected to the COM1 pin, one of the two VGA interfaces can be electrically connected to the NO1 interface, the other of the two VGA interfaces can be electrically connected to the NC1 interface, and in the example given in fig. 8, the COM1 pin can be electrically connected to the NC1 pin.

Fig. 10 is a block diagram illustrating the structure of the control node 210 of the testing apparatus 200 shown in fig. 4, which includes a management control unit 212 and a processing unit 213.

Referring to fig. 10, in the case that the control node 210 includes a management control unit 212 and a processing unit 213, the management control unit 212 may be electrically connected to the switch controller 223, and the management control unit 212 is configured to generate a selection signal and transmit the selection signal to the switch controller 223. For example, the management control unit 212 and the switch controller 223 may be electrically connected through an I2C bus. The I2C bus between the management control unit 212 and the switch controller 223 does not belong to the first-type interface group 214 and the second-type interface 215.

Based on the testing apparatus 200 provided in some embodiments above, embodiments of the present application also provide a testing method for a multi-node management board.

FIG. 11 is a flow diagram of a method of testing a multi-node management board according to some embodiments.

Referring to fig. 11, the testing method of the multi-node management board can be applied to the testing apparatus 200 provided in some embodiments above. The testing method of the multi-node management board comprises the following steps S10 to S30.

And S10, electrically connecting the plurality of second signal terminals 222 of the test device 200 with the plurality of node connecting terminals 110 of the multi-node management board 100 in a one-to-one correspondence manner.

Referring to fig. 2, in the case that one node connecting terminal 110 includes a plurality of fourth interfaces, the second signal terminal 222 includes a plurality of third interfaces. In step S10, the fourth interfaces of one node connection terminal 110 are electrically connected to the third interfaces of one second signal terminal 222 in a one-to-one correspondence.

S20, the control node 210 of the test apparatus 200 generates a test signal.

In the case where a plurality of interfaces are included in one node connection terminal 110, the test signal includes a plurality of test sub-signals, and in this case, the control node 210 may sequentially generate the plurality of test sub-signals.

S30, the switching unit 220 of the testing apparatus 200 sequentially transmits the testing signal to each node connection terminal 110 to test the plurality of node connection terminals 110 of the multi-node management board 100.

The test signal is sequentially transmitted to each node connection terminal 110, so that the plurality of node connection terminals 110 of the multi-node management board 100 sequentially complete the test.

When the test signal includes a plurality of test sub-signals, the plurality of test sub-signals are sequentially generated when one node connection terminal 110 is tested, and then the plurality of test sub-signals are sequentially transmitted to the plurality of fourth interfaces in the node connection terminal 110, so that the plurality of fourth interfaces in the node connection terminal 110 are sequentially tested.

In the testing method of the multi-node management board provided in some embodiments of the present application, the switching unit 220 may transmit the test signal to the different second signal terminals 222 in a time-sharing manner, so that the testing of the plurality of node connection terminals 110 can be completed by only setting one control node 210, thereby reducing the number of control nodes 110 and reducing the testing cost.

FIG. 12 is another flow chart of a method of testing a multi-node management board provided in accordance with some embodiments.

Referring to fig. 12 in conjunction with fig. 4, in the case that the switching unit 220 includes the switch controller 223 and at least one switch chip 224, the testing method further includes: s21, the control node 210 generates a plurality of selection signals. The plurality of selection signals are in one-to-one correspondence with the plurality of second signal terminals 222.

S30, the step of sequentially transmitting the test signal to each node connection terminal 110 by the switching unit 220 of the test apparatus 200 includes: and S3.1, controlling at least one switch chip 224 to communicate with the first signal end 221 and the second signal end 222 corresponding to the selection signal by the switch controller 223 according to the selection signal so as to transmit the test signal to the plurality of node connection ends 110 in sequence.

In some embodiments, at least one switch chip 224 is controlled by the switch controller 223, so that the test signal can be transmitted to different second signal terminals 222 in a time-sharing manner,

the control node 210 may alternately generate the selection signal and the test signal. For example, in a case that the selection signal may include a first selection signal and a second selection signal, the control node 210 may first generate the first selection signal, such that the first signal terminal 221 is electrically connected to the first second signal terminal 222A, and then the control node 210 may sequentially generate a plurality of test sub-signals, such that the plurality of test sub-signals may be transmitted to the first node connection terminal 110A through the first signal terminal 221 and the first second signal terminal 222A, and thus, the plurality of fourth interfaces in the first node connection terminal 110A may be sequentially tested. After testing the plurality of fourth interfaces in the first node connection terminal 110A, the control node 210 may generate a second selection signal, such that the first signal terminal 221 is electrically connected to the second signal terminal 222B, and then the control node 210 sequentially generates a plurality of test sub-signals again, such that the plurality of test sub-signals may be transmitted to the second node connection terminal 110B through the first signal terminal 221 and the second signal terminal 222B, so as to test the plurality of fourth interfaces in the second node connection terminal 110B.

The following describes a method for testing a plurality of fourth interfaces in the node connecting terminal 110 of the multi-node management board 100.

Fig. 13 is a block diagram of a connection structure of the test device 200, the multi-node management board 100, and the external device 300 according to some embodiments.

Referring to fig. 13, when testing the multi-node management board 100, the multi-node management board 100 may be electrically connected to the external device 300, and at this time, the testing apparatus 200 may control the external device 300 through the multi-node management board 100, so as to test the multi-node management board 100, wherein when testing different fourth interfaces on the multi-node management board 100, different external devices 300 may be used, and of course, when testing some of all the fourth interfaces, the same external device 300 may also be used.

In some examples, a plurality of patch cords are disposed on the multi-node management board 100, and the patch cords may be connected between at least a portion of the fourth interface and the external device 300.

In some examples, in the multi-node management board 100, each node connection end 110 includes a first fourth I2C interface. Correspondingly, in the testing apparatus 200, each of the second signal terminals 222 includes a first third I2C interface. The first signal terminal 221 includes a first second I2C interface, and the control node 210 includes a first I2C interface. The multi-node management board 100 is further provided with a first I2C patch cord, and one end of the first I2C patch cord is electrically connected to the first fourth I2C interface. In testing the first fourth I2C interface, the external device 300 may be a PSU (Power Supply Unit) 310. The other end of the first I2C patch cord may be electrically connected to the PSU310. At this time, the test sub-signal sent by the test apparatus 200 may be a PSU test sub-signal, and the PSU test sub-signal may be sent to the PSU310 sequentially through the first third I2C interface, the first fourth I2C interface, and the first I2C patch cord. The test signal may control the switching of the PSU310, for example, if the PSU310 can supply power or stop supplying power to other devices according to the PSU test sub-signal, it may be considered that the first fourth I2C interface passes the test. The first I2C interface may be electrically connected to the management control unit 212 (as shown in fig. 4), and in this case, the management control unit 212 is configured to generate the PSU test sub-signal and send the PSU test sub-signal to the first second I2C interface through the first I2C interface. In some examples described above, describing the testing process of the first fourth I2C interface of one node connection terminal 110, the switching unit 220 may enable the PSU test sub-signal to be switched and transmitted to the first fourth I2C interface of another node connection terminal 110, so as to test the first fourth I2C interface of another node connection terminal 110.

In some examples, in the multi-node management board 100, each node connection terminal 110 includes a second fourth I2C interface, and correspondingly, in the test apparatus 200, each second signal terminal 222 includes a second third I2C interface. The first signal terminal 221 includes a second, second I2C interface, and the control node 210 includes a second, first I2C interface. The multi-node management board 100 is further provided with a second I2C patch cord, and one end of the second I2C patch cord is electrically connected to the second fourth I2C interface. When testing the second fourth I2C interface, the external device 300 may be a hard disk backplane 320, a clock signal chip is disposed on the hard disk backplane 320, and the other end of the second I2C patch cord may be electrically connected to the clock signal chip. At this time, the test sub-signal sent by the test apparatus 200 may be a clock test sub-signal, the clock test sub-signal may be sent to the clock signal chip sequentially through the second third I2C interface, the second fourth I2C interface, and the second I2C patch cord, after the clock signal chip receives the clock test sub-signal, the clock waveform may be sent to the control node 210 through the second I2C patch cord, the second fourth I2C interface, the second third I2C interface, and the switching unit 220, and if the control node 210 can successfully receive the clock waveform, it may be considered that the second fourth I2C interface passes the test. Illustratively, the second first I2C interface may be electrically connected to the management control unit 212 (shown in fig. 4), and the management control unit 212 is configured to generate the clock test sub-signal and transmit the clock test sub-signal to the second I2C interface through the second first I2C interface. In some examples, the test procedure of the second fourth I2C interface of one node connection terminal 110 is described, and the switching unit 220 may enable the clock test sub-signal to be switched and transmitted to the second fourth I2C interface of another node connection terminal 110, so as to test the second fourth I2C interface of another node connection terminal 110.

In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth VGA interface, and correspondingly, in the test apparatus 200, each second signal terminal 222 includes a third VGA interface. The first signal terminal 221 comprises a second VGA interface and the control node 210 comprises a first VGA interface. And a VGA patch cord is further disposed on the multi-node management board 100, and one end of the VGA patch cord is electrically connected to the fourth VGA interface. When testing the fourth VGA interface, the external device 300 can be the display device 330, and the other end of the VGA patch cord can be electrically connected to the display device 330. The test sub-signal sent by the test device 200 is a VGA test sub-signal, the VGA test sub-signal can be sequentially sent to the display device 330 through the third VGA interface, the fourth VGA interface and the VGA patch cord, and if the display device 330 can display a preset picture, it can be considered that the fourth VGA interface passes the test. For example, the first VGA interface may be electrically connected to the management control unit 212 (as shown in fig. 4), and the management control unit 212 is configured to generate the VGA test sub-signal and transmit the VGA test sub-signal to the second VGA interface through the first VGA interface. In some examples, the test procedure of the fourth VGA interface of one node connection terminal 110 is described, and the switching unit 220 may enable the VGA test sub-signal to be switched and transmitted to the fourth VGA interfaces of other node connection terminals 110, so as to test the fourth VGA interfaces of other node connection terminals 110.

In some examples, in the multi-node management board 100, a fourth USB interface is included in each node connection terminal 110. Correspondingly, in the testing apparatus 200, each of the second signal terminals 222 includes a third USB interface. The first signal terminal 221 includes a second USB interface, and the control node 210 includes a first USB interface. And a USB patch cord is further disposed on the multi-node management board 100, and one end of the USB patch cord is electrically connected to the fourth USB interface. When testing the fourth USB interface, the external device 300 may be a USB disk 340, and the other end of the USB patch cord is electrically connected to the USB disk 340. The test sub-signal sent by the test apparatus 200 is a USB test sub-signal, the USB test sub-signal may sequentially pass through the third USB interface, the fourth USB interface, and the USB patch cord to be sent to the USB disk 340, and if the USB disk 340 receives the USB test sub-signal, the test apparatus 200 may successfully read information written to the USB disk 340. If the testing apparatus 200 can successfully read the information written to the USB disk 340, it may be considered that the fourth USB interface passes the test. For example, the first USB interface may be electrically connected to the management control unit 212 (as shown in fig. 4), and the management control unit 212 is configured to generate the USB test sub-signal and send the USB test sub-signal to the second USB interface through the first USB interface. In some examples described above, when the testing process of the fourth USB interface of one node connection end 110 is described, the switching unit 220 may enable the USB test sub-signal to be switched and transmitted to the fourth USB interface of another node connection end 110, so as to test the fourth USB interface of another node connection end 110.

In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth GPIO interface, and correspondingly, in the test apparatus 200, each second signal terminal 222 includes a third GPIO interface. The first signal terminal 221 includes a second GPIO interface and the control node 210 includes a first GPIO interface. And a GPIO patch cord is further disposed on the multi-node management board 100, and one end of the GPIO patch cord is electrically connected to the fourth GPIO interface. When testing the fourth GPIO interface, the external device 300 may be a hard disk backplane 320, where the hard disk backplane 320 may be used to plug multiple hard disks, and the other end of the GPIO patch cord is electrically connected to the hard disk backplane 320. The test sub-signal sent by the test device 200 is a hard disk test sub-signal, the hard disk test sub-signal may be sent to the hard disk backplane 320 sequentially through the third GPIO interface, the fourth GPIO interface, and the GPIO patch cord, and if the hard disk backplane 320 may send the in-place signal of the hard disk to the third GPIO interface through the GPIO patch cord and the fourth GPIO interface, the switching unit 220 may feed back the in-place signal to the control node 210, and it may be considered that the fourth GPIO interface passes the test. For example, the first GPIO interface may be electrically connected to the processing unit 213, and at this time, the management control unit 212 may control the processing unit 213 to generate the hard disk test sub-signal and transmit the hard disk test sub-signal to the second GPIO interface through the first GPIO interface. In some examples, the test procedure of the fourth GPIO interface of one node connection terminal 110 is described, and the switching unit 220 may enable the hard disk test sub-signal to be switched and transmitted to the fourth GPIO interfaces of other node connection terminals 110, so as to test the fourth GPIO interfaces of other node connection terminals 110.

In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth UART interface, and correspondingly, in the test apparatus 200, each second signal terminal 222 includes a third UART interface. The first signal terminal 221 includes a second UART interface, and the control node 210 includes a first UART interface. The multi-node management board 100 is further provided with a UART patch cord, and one end of the UART patch cord is electrically connected to the fourth UART interface. When testing the fourth UART interface, the external device 300 may be a right operation board 350, and the other end of the UART patch cord is electrically connected to the right operation board 350. The test sub-signal sent by the test apparatus 200 is a right operation and maintenance test sub-signal, the right operation and maintenance test sub-signal may be sent to the right operation and maintenance board through the third UART interface, the fourth UART interface and the UART patch cord in sequence, and if the right operation and maintenance test sub-signal can be successfully sent to the right operation and maintenance board 350, it may be considered that the fourth UART interface passes the test. For example, the first UAR interface may be electrically connected to the management control unit 212 (as shown in fig. 4), and the management control unit 212 is configured to generate a time right operation and maintenance test sub-signal and transmit the time right operation and maintenance test sub-signal to the second UART interface through the first UART interface. In some examples, the testing process of the fourth UART interface of one node connector 110 is described, and the switching unit 220 may enable the right operation and maintenance test sub-signal to be switched and transmitted to the fourth UART interfaces of other node connectors 110, so as to test the fourth UART interfaces of other node connectors 110.

In some examples, the multi-node management board 100 further includes a CPLD (Complex Programmable Logic Device) chip, each node connection terminal 110 further includes a third fourth I2C interface connected to the CPLD chip, and the multi-node management board 100 further includes a PWM (Pulse Width Modulation) interface connected to the CPLD chip. Correspondingly, in the testing apparatus 200, the second signal terminal 222 of the testing apparatus 200 includes a third I2C interface, and the external device 300 may be a fan 360. When the third fourth I2C interface is tested, the third I2C interface is electrically connected to the third fourth I2C interface, so that the testing device 200 is electrically connected to the CPLD chip, and the CPLD chip may be electrically connected to the fan 360 through the PWM interface. The test sub-signal sent by the test device 200 is a rotational speed test sub-signal, and the rotational speed test sub-signal can be sent to the CPLD chip through the third I2C interface and the third fourth I2C interface. If the CPLD chip can send out a corresponding pulse width modulation signal according to the rotational speed test sub-signal, and send the pulse width modulation signal to the fan 360 through the PWM interface, so as to control the rotational speed of the fan 360. The third I2C interface may be considered to pass the test. For example, the third first I2C interface may be electrically connected to the management control unit 212 (as shown in fig. 4), and the management control unit 212 is configured to generate a tachometer sub-signal and send the tachometer sub-signal to the third second I2C interface through the third first I2C interface. In some examples, the testing process of the third fourth I2C interface of one node connection terminal 110 is described, and the switching unit 220 may enable the rotation speed test sub-signal to be switched and transmitted to the third fourth I2C interfaces of other node connection terminals 110, so as to test the third fourth I2C interfaces of other node connection terminals 110.

In some examples, in the multi-node management board 100, each node connection end 110 includes a fourth JTAG interface electrically connected with the CPLD chip of the multi-node management board 100, and correspondingly, in the testing apparatus 200, each second signal end 222 includes a third JTAG interface. The first signal terminal 221 includes a second JTAG interface, and the control node 210 includes a first JTAG interface. When the fourth JTAG interface is tested, the fourth JTAG interface is electrically connected to the third JTAG interface, and at this time, the test sub-signal sent by the test apparatus 200 is a JTAG test sub-signal, which may be, for example, a test sub-program. The test subprogram sent by the test device 200 can be written into the CPLD chip through the third JTAG interface and the fourth JTAG interface, if the test subprogram is successfully written into the CPLD chip, the CPLD chip can control the fan 360 to rotate according to the test subprogram, and if the fan 360 rotates according to the test subprogram, it can be considered that the fourth JTAG interface and the CPLD chip pass the test. The CPLD chip may be electrically connected to the fan 360 through the PWM interface. For example, a first JTAG interface may be electrically connected to the processing unit 213 (as shown in fig. 4), and at this time, the management control unit 212 may control the processing unit 213 to generate JTAG test sub-signals and transmit the JTAG test sub-signals to a second JTAG interface through the first JTAG interface. In some examples described above, describing the testing process of the fourth JTAG interface of one node connection terminal 110, the switching unit 220 may enable the JTAG test sub-signal to be switched and transmitted to the fourth JTAG interfaces of other node connection terminals 110, so as to test the fourth JTAG interfaces of other node connection terminals 110.

In some examples, in the multi-node management board 100, each node connection end 110 includes a fourth I2C interface, and the fourth I2C interface is electrically connected with the CPLD chip of the multi-node management board 100. Correspondingly, in the test apparatus 200, the third interface of each second signal terminal 222 includes a fourth third I2C interface, the first signal terminal 221 includes a fourth second I2C interface, and the control node 210 includes a fourth first I2C interface. When the fourth I2C interface is tested, the external device 300 may be an operation and maintenance card, the test sub-signal sent by the test device 200 is an in-place test sub-signal, the in-place test sub-signal may be sent to the CPLD chip of the multi-node management board 100 through the fourth third I2C interface and the fourth I2C interface, and the CPLD chip of the multi-node management board 100 may obtain the in-place signal of the operation and maintenance card according to the in-place test sub-signal, and if the CPLD chip of the multi-node management board 100 can obtain the in-place signal of the operation and maintenance card, it may be determined that the fourth I2C interface passes the test. For example, the fourth first I2C interface may be electrically connected to the management control unit 212 (as shown in fig. 4), and in this case, the management control unit 212 is configured to generate the in-place test sub-signal and send the in-place test sub-signal to the fourth second I2C interface through the fourth first I2C interface. In some examples, the testing process of the fourth I2C interface of one node connection terminal 110 is described, and the switching unit 220 may enable the in-place test sub-signal to be switched and transmitted to the fourth I2C interfaces of other node connection terminals 110, so as to test the fourth I2C interfaces of other node connection terminals 110.

In some examples, the multi-node management board 100 further includes: a SW (Switch) chip and a PHY (Physical Layer) chip, wherein the SW chip and the PHY chip are electrically connected. Each node connection terminal 110 further includes a fourth MDIO interface, wherein the fourth MDIO interface may be electrically connected to the SW chip and the PHY chip, respectively. Correspondingly, in the test apparatus 200, the second signal terminal 222 includes a third MDIO interface, the first signal terminal 221 includes a second MDIO interface, and the control node 210 includes a first MDIO interface. When the fourth MDIO interface is tested, the test sub-signal sent by the test apparatus 200 is an MDIO test sub-signal, and the MDIO test sub-signal may be sequentially sent to the SW chip and the PHY chip through the third MDIO interface and the fourth MDIO interface. In this example, if the testing apparatus 200 can find the register ID of the SW chip and the register ID of the PHY chip, it may be considered that the SW chip, the PHY chip, and the fourth MDIO interface pass the test. For example, the first MDIO interface may be electrically connected to the management control unit 212 (as shown in fig. 4), and in this case, the management control unit 212 is configured to generate the MDIO test sub-signal and send the generated MDIO test sub-signal to the second MDIO interface through the first MDIO interface. In some examples, the test procedure of the fourth MDIO interface of one node connection terminal 110 is described, and the switching unit 220 may enable the MDIO test sub-signal to be switched and transmitted to the fourth MDIO interface of another node connection terminal 110, so as to test the fourth MDIO interface of another node connection terminal 110.

In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth SGMII interface electrically connected with the SW chip. At this time, the multi-node management board 100 further includes: and the network interface is electrically connected with the SW chip, wherein the network interface can be an RJ45 interface. Correspondingly, in the testing apparatus 200, each second signal terminal 222 includes a third SGMII interface. The first signal terminal 221 includes a second SGMII interface and the control node 210 includes a first SGMII interface. When testing the fourth SGMII interface and the SW chip, the used external device 300 may be the left operation and maintenance card 370, where the left operation and maintenance card has a Media Access Control (MAC) address, and the test sub-signal sent by the test device 200 may be an addressing test sub-signal, and the addressing test sub-signal may be sent to the SW chip through the third SGMII interface and the fourth SGMII interface, and the SW chip forwards the addressing test sub-signal to the left operation and maintenance card 370 through the network interface, and after receiving the addressing test sub-signal, the left operation and maintenance card 370 may send the MAC address to the test device 200, and if the test device 200 successfully finds the MAC address of the left operation and maintenance card, it may be determined that the fourth SGMII interface and the SW chip pass the test. For example, the first SGMII interface may be electrically connected to the management control unit 212, and in this case, the management control unit 212 is configured to generate the address-time test sub-signal and transmit the address-time test sub-signal to the second SGMII interface through the first SGMII interface. In some of the above examples, describing the testing procedure of the fourth SGMII interface of one node connecting terminal 110, the switching unit 220 may enable the addressing test sub-signal to be switched and transmitted to the fourth SGMII interface of the other node connecting terminal 110, so as to test the fourth SGMII interface of the other node connecting terminal 110.

In some examples, the external device 300 corresponding to each node connection end 110 in the multi-node management board 100 may be connected to the multi-node management board 100, so that when different node connection ends 110 receive a test signal, that is, when different node connection ends 110 are tested, the connection relationship of the external device 300 does not need to be changed, thereby facilitating the test of the multi-node management board 100.

The above description is only for the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can think of the changes or substitutions within the technical scope of the present application, and shall be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A testing apparatus, for testing a multi-node management board; wherein the multi-node management board comprises a plurality of node connection ends; the method comprises the following steps:

a control node for generating a test signal;

a switching unit having a first signal terminal and a plurality of second signal terminals; the first signal end is electrically connected with the control node, and the plurality of second signal ends are electrically connected with the plurality of node connecting ends in a one-to-one correspondence manner; the switching unit is used for: and receiving the test signal through the first signal end, and transmitting the test signal of the first signal end to different second signal ends in a time-sharing manner so as to test a plurality of node connecting ends of the multi-node management board.

2. The test apparatus according to claim 1, wherein the switching unit comprises: a switch controller and at least one switch chip;

any one of the switch chips is electrically connected between the first signal end and the plurality of second signal ends;

the switch controller is electrically connected with the control node, and the switch controller is electrically connected with the at least one switch chip; the control node is further configured to generate a selection signal; the switch controller is used for controlling at least one switch chip to communicate the first signal end and a second signal end corresponding to the selection signal based on the selection signal.

3. The test device of claim 2,

the types of all the switch chips in the switching unit comprise at least two;

the test signal comprises at least two different test sub-signals; one test sub-signal corresponds to one switch chip, and the same test sub-signal can be transmitted to different second signal ends in a time-sharing mode through the corresponding switch chip.

4. The test device of claim 3,

the at least one switch chip includes a first switch chip and a second switch chip; the first switch chip and the second switch chip are different in type;

the first signal end comprises a first interface group and a second interface group, and the first switch chip is electrically connected to the control node through the first interface group; the second switch chip is electrically connected to the control node through the second interface group;

each second signal terminal comprises a third interface group and a fourth interface group; the first switch chip is connected to each node connection terminal through each third interface group, and the second switch chip is connected to each node connection terminal through each fourth interface group.

5. The test device of claim 4,

the first interface group and the third interface group comprise at least one high-speed interface, and the high-speed interfaces are used for transmitting high-speed sub signals;

the second interface group and the fourth interface group both comprise at least one low-speed interface, and the low-speed interfaces are used for transmitting low-speed sub-signals.

6. The test device of claim 5,

the first interface group and the third interface group each include: at least one of an SGMII interface and a USB interface;

the second interface group and the fourth interface group each include: at least one of an I2C interface, an MDIO interface, a JTAG interface, a GPIO interface, a UART interface, and a VGA interface.

7. The test device according to any one of claims 1 to 6,

the control node comprises a management control unit and a processing unit electrically connected with the management control unit;

the control node comprises a first interface group electrically connected with the management control unit and a second interface group electrically connected with the processing unit;

the test signals comprise a first test signal and a second test signal;

the management control unit is used for generating the first test signal and outputting the first test signal by the first interface group; the management control unit is further used for controlling the processing unit to generate the second test signal and outputting the second test signal by the second type interface group.

8. The test device of claim 7,

the management control unit comprises a BMC chip;

the processing unit comprises a CPLD chip.

9. A test method of a multi-node management board is characterized by comprising the following steps:

electrically connecting a plurality of second signal terminals of the test apparatus according to any one of claims 1 to 8 to a plurality of node connection terminals of the multi-node management board in a one-to-one correspondence;

a control node of the test device generates a test signal;

and the switching unit of the test device transmits the test signals to each node connecting end in sequence so as to test the plurality of node connecting ends of the multi-node management board.

10. The test method according to claim 9,

in a case where the switching unit includes a switch controller and at least one switch chip, the test method further includes:

the control node generating a plurality of selection signals;

the step that the switching unit of the test device transmits the test signal to each node connecting end in sequence comprises the following steps:

and the switch controller controls at least one switch chip to communicate a first signal end and a second signal end corresponding to the selection signal according to the selection signal so as to sequentially transmit the test signal to the plurality of node connecting ends.