CN117539806B - Multi-point communication system - Google Patents
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- CN117539806B CN117539806B CN202410028498.6A CN202410028498A CN117539806B CN 117539806 B CN117539806 B CN 117539806B CN 202410028498 A CN202410028498 A CN 202410028498A CN 117539806 B CN117539806 B CN 117539806B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The present application relates to a multipoint communication system comprising: the UART control module, the buffer module, the summarizing module and the UART executing modules; the UART control module and the UART execution module are respectively provided with a receiving port and a transmitting port; the buffer module comprises an input end and a plurality of output ends; the input end of the buffer module is connected with the transmitting port of the UART control module, a plurality of output ends of the buffer module are respectively and correspondingly connected with the receiving ports of the UART execution modules, and the buffer module is used for dividing the data signals transmitted by the UART control module into a plurality of same data signals and respectively and correspondingly outputting the same data signals to each UART execution module; the summarizing module comprises an output end and a plurality of input ends; the input ends of the summarizing module are respectively and correspondingly connected with the transmitting ports of the UART executing modules, the output end of the summarizing module is connected with the receiving port of the UART control module, and the summarizing module is used for transmitting the data signals transmitted by the UART executing modules to the UART control module in a time-sharing manner. Accordingly, a multipoint communication mode based on UART communication is realized.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a multicast system.
Background
Within a system, there will typically be situations where a management module communicates with multiple execution modules or multiple subsystems. For example, in the case of communication between the BMC (Baseboard Manager Controller, baseboard management controller) and the motherboard CPLD (ComplexProgrammable Logic Device ) or the hard disk backplane CPLD; the BMC may send a control command to the CPLD, or the BMC may receive data from the motherboard CPLD or the hard disk backplane CPLD.
Typically, I2C (Inter-Integrated Circuit, integrated circuit bus) communication is adopted for communication between the modules, but the I2C communication has the problems of higher requirements on hardware design, unequal communication roles (typically, the I2C is divided into HOST and SLAVE roles, and the communication can only be initiated by HOST), and the like.
The conventional UART (Universal Asynchronous Receiver/Transmitter) communication has lower requirements on hardware design and peer-to-peer communication roles, but only supports a point-to-point communication mode, and if a multipoint communication mode is needed, UART interfaces of a control end (HOST) are needed, so that the hardware design requirements on the control end (HOST) are higher.
Disclosure of Invention
In view of the above, it is necessary to provide a multipoint communication system for realizing a multipoint communication system.
The application provides a multipoint communication system. The multipoint communication system includes: the UART control module, the buffer module, the summarizing module and the UART executing modules;
the UART control module and the UART execution module are respectively provided with a receiving port and a transmitting port;
the buffer module comprises an input end and a plurality of output ends, wherein the input end of the buffer module is connected with the transmitting port of the UART control module, the plurality of output ends of the buffer module are respectively and correspondingly connected with the receiving ports of the UART execution modules, and the buffer module is used for dividing the data signals transmitted by the UART control module into a plurality of same data signals and respectively and correspondingly outputting the same data signals to each UART execution module;
the collecting module comprises an output end and a plurality of input ends, wherein the plurality of input ends of the collecting module are respectively and correspondingly connected with the transmitting ports of the UART executing modules, the output end of the collecting module is connected with the receiving port of the UART control module, and the collecting module is used for transmitting data signals transmitted by the UART executing modules to the UART control module in a time-sharing mode.
In one embodiment, the UART control module is further configured with a first arbitration port, and each UART execution module is further configured with a second arbitration port;
the first arbitration ports are respectively connected with the second arbitration ports; wherein,
when a transmitting port of a target UART executing module transmits data to a receiving port of the UART control module through the summarizing module, the level state of a second arbitration port of the target UART executing module is a first state, and the level states of the second arbitration ports of other UART executing modules are changed into the first state in a following way; the target UART execution module is one of the plurality of UART execution modules.
In one embodiment, the multipoint communication system further comprises: a pull-up module;
the first end of the pull-up module is respectively connected with the first arbitration ports and the second arbitration ports, the second end of the pull-up module is used for receiving preset voltage signals, and the pull-up module is used for changing the level state of each second arbitration port to a second state under the condition that no data signal is output by the sending port of each UART execution module; wherein the second state is different from the first state.
In one embodiment, the pull-up module includes: a resistor unit; the first end of the resistance unit is the first end of the pull-up module, and the second end of the resistance unit is the second end of the pull-up module.
In one embodiment, the summarizing module further includes a first power supply terminal, and the buffering module further includes a second power supply terminal; the first power end and the second power end are respectively connected with the second end of the pull-up module.
In one embodiment, the first arbitration port and each of the second arbitration ports include a general purpose input output port, respectively.
In one embodiment, the transmitting port of the UART control module transmits the control data signal according to a first preset data format; wherein the first preset data format includes:
a first preset address header and a target data signal located after the first preset address header; the first preset address header comprises address bits and data bits positioned behind the address bits, wherein the byte number of the target data signal is equal to the data size represented by the data bits in the first preset address header.
In one embodiment, the transmitting port of the UART executing module transmits the execution data signal according to a second preset data format; wherein the second preset data format includes:
a second preset address header and a target data signal located after the second preset address header; the second preset address header includes an address bit and a data bit located after the address bit, wherein the number of bytes of the target data signal is equal to the data size represented by the data bit in the second preset address header.
In one embodiment, the summarization module includes: a first AND gate device;
the first AND gate device is configured with an output port and a plurality of input ports; wherein,
the output port of the first AND gate device is the output end of the summarizing module, and the input port of the first AND gate device is the input end of the summarizing module.
In one embodiment, the summarization module includes: n cascaded second AND gate devices;
the second AND gate device is configured with an output port and a plurality of input ports; wherein,
the output port of the second AND gate device of the nth stage is used for being connected with the receiving port of the UART control module, the output port of the second AND gate device of the ith-1 stage is connected with one input port of the second AND gate device of the ith stage, at least part of the input ports of the second AND gate devices of each stage are respectively used for being correspondingly connected with the transmitting port of the UART execution module, wherein n and i are positive integers, and n is more than or equal to i and is more than 1.
In one embodiment, the summarization module further comprises: at least one third AND gate device;
the third AND gate device is configured with an output port and a plurality of input ports; wherein,
the output port of the third AND gate device is connected with one input port of any second AND gate device, and at least part of the input ports of the third AND gate device are respectively used for correspondingly connecting with the transmitting port of one UART executing module.
In one embodiment, the buffer module includes: a first buffer device;
the first buffer device is configured with an input port and a plurality of output ports; wherein,
the input port of the first buffer device is the input end of the buffer module, and the output port of the first buffer device is the output end of the buffer module.
In one embodiment, the buffer module includes: m cascaded second buffer devices;
the second buffer device is configured with an input port and a plurality of output ports; wherein,
the input port of the second buffer device of the 1 st stage is used for being connected with the transmitting port of the UART control module, the input port of the second buffer device of the j th stage is connected with an output port of the second buffer device of the j-1 st stage, at least part of the output ports of the second buffer devices of each stage are respectively used for being correspondingly connected with the receiving port of the UART execution module, wherein m and j are positive integers, and m is more than or equal to j and is more than 1.
In one embodiment, the buffer module further comprises: at least one third buffer device;
the third buffer device is configured with an input port and a plurality of output ports; wherein,
the input port of the third buffer device is connected with an output port of any one of the second buffer devices, and at least part of the output ports of the third buffer device are respectively used for being correspondingly connected with a receiving port of the UART execution module.
The multipoint communication system comprises a UART control module, a buffer module, a summarizing module and a plurality of UART executing modules; the UART control module and the UART execution module are respectively provided with a receiving port and a sending port. The buffer module comprises an input end and a plurality of output ends, wherein the input end is connected with the transmitting port of the UART control module, the plurality of output ends are respectively and correspondingly connected with the receiving ports of the UART execution modules, based on the buffer module, the data signals transmitted by the UART control module can be divided into a plurality of same data signals, and the same data signals are respectively and correspondingly output to each UART execution module.
The summarizing module comprises an output end and a plurality of input ends, the plurality of input ends are respectively and correspondingly connected with the transmitting ports of the plurality of UART executing modules, the output end is connected with the receiving port of the UART control module, and based on the summarizing module, data signals transmitted by the UART executing modules can be transmitted to the UART control module in a time sharing mode. According to the scheme, the multipoint communication mode based on UART communication can be realized only by setting the buffer module, the summarizing module, the UART control module, the buffer module, the summarizing module and the connection relation among the plurality of UART execution modules, the hardware design requirement is lower, and the UART control module and the UART execution modules are in communication role peer-to-peer.
Drawings
Fig. 1 is a schematic structural diagram of a multicast system in one embodiment;
FIG. 2 is a schematic diagram of a first predetermined data format according to one embodiment;
FIG. 3 is a diagram illustrating a second predetermined data format according to one embodiment;
FIG. 4 is a block diagram of the summary module in one embodiment;
FIG. 5 is a block diagram of the summary module in one embodiment;
FIG. 6 is a block diagram of a buffer module in one embodiment;
FIG. 7 is a block diagram of a buffer module in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, there is provided a multipoint communication system comprising: the UART control module 110, the plurality of UART execution modules 120, the buffer module 130 and the summarization module 140.
The UART control module 110 may be understood as: within one system, a UART communication based control side (HOST) module. The UART control module 110 is configured with a transmit port (TXD) for transmitting data signals based on UART communication and a receive port (RXD) for receiving data signals based on UART communication.
The UART execution module 120 may be understood as: within one system, a UART communication based executive (SLAVE) module. The UART execution module 120 is configured with a receiving port (RXD) for receiving a data signal based on UART communication and a transmitting port (TXD) for transmitting a data signal based on UART communication. 1 UART control module 110 and 7 UART execution modules 120 are illustrated in fig. 1.
The buffer module 130 includes an input for receiving a signal and a plurality of outputs for outputting the signal. The buffer module 130 has a function of dividing a received data signal into a plurality of data signals which are identical and mutually independent and non-interfering, wherein any of the divided data signals is identical to an originally received data signal, and outputting the divided data signals.
In this embodiment, the input end of the buffer module 130 is connected to the transmitting port of the UART control module 110, and the plurality of output ends of the buffer module 130 are respectively connected to the receiving ports of the UART execution modules 120, based on which, the buffer module 130 can divide the data signal transmitted by the UART control module 110 from the transmitting port into a plurality of data signals which are identical and mutually independent and mutually noninterfere, any one of the divided data signals is identical to the data signal originally received, and the plurality of divided data signals are respectively and correspondingly output to each UART execution module 120, i.e. each of the divided data signals is output to a corresponding UART execution module 120, thereby realizing the data transmission from the UART control module 110 to the UART execution modules 120, i.e. the multipoint communication mode between the UART control module 110 and the UART execution modules 120.
The summarizing module 140 includes an output that outputs a signal and a plurality of inputs that receive the signal. The summarizing module 140 has functions of integrating, summarizing, and transmitting received data signals.
In this embodiment, the output end of the summarizing module 140 is connected to the receiving port of the UART control module 110, and the plurality of input ends of the summarizing module 140 are respectively connected to the transmitting ports of the UART executing modules 120 correspondingly, so that the summarizing module 140 can transmit the data signals sent by the UART executing modules 120 from the transmitting ports thereof to the UART control module 110 in a time-sharing manner, thereby realizing the data transmission from the UART executing modules 120 to the UART control module 110.
Compared with the multipoint communication mechanism in the related art, the scheme of the embodiment of the application does not need to add UART interfaces of a control end (HOST), but can realize the multipoint communication mode based on UART communication by only setting the buffer module 130, the summarizing module 140 and the connection relation among the UART control module 110, the buffer module 130, the summarizing module 140 and the UART execution modules 120, so that the UART control module 110 and the UART execution modules 120 have a lower requirement on hardware design, and the communication roles are equivalent, namely, the UART control module 110 can send data to the UART execution modules 120, and the UART execution modules 120 can send data to the UART control module 110. The UART control module 110 sends data to the UART execution modules 120 through the buffer module 130, and the buffer module 130 can avoid signal interference between the UART execution modules 120 and ensure high-quality transmission of the data signals sent by the UART control module 110 to the UART execution modules 120. The summarizing module 140 transmits the data signals respectively sent by the UART executing modules 120 to the UART control module 110 in a time-sharing manner, so that signal interference among the UART executing modules 120 can be avoided, and high-quality transmission of the data signals sent by the UART executing modules 120 to the UART control module 110 is ensured.
In one embodiment, as shown in fig. 1, the UART control module 110 is further configured with a first arbitration port, and each UART execution module 120 is further configured with a second arbitration port.
The first arbitration port and each of the second arbitration ports may be the same type of signal transmission port. Optionally, the first arbitration port and each of the second arbitration ports comprise a general purpose input output port (GPIO), respectively. The first arbitration port and the second arbitration port are GPIOs, so that the hardware design for realizing time-sharing transmission by the UART execution modules 120 is simple, and the hardware structure of the multicast system is simple.
The first arbitration ports of the UART control module 110 are respectively connected with the second arbitration ports of the UART execution modules 120, based on which, when the transmitting port of the target UART execution module 120 transmits data to the receiving port of the UART control module 110 through the summarizing module 140, the level state of the second arbitration port of the target UART execution module 120 is the first state, the level states of the second arbitration ports of the other UART execution modules 120 are changed to the first state, and the target UART execution module 120 is one of the UART execution modules 120.
In this embodiment, the summarizing module 140 transmits the data signals sent by the UART executing modules 120 from the transmitting ports thereof to the UART control module 110 in a time-sharing manner. That is, only one UART execution module 120 of the plurality of UART execution modules 120 may be transmitting data signals to the UART control module 110 at the same time or during the same period. In this embodiment, the target UART execution module 120 is one of the UART execution modules 120, and when the transmitting port of the target UART execution module 120 transmits data to the receiving port of the UART control module 110 through the summarizing module 140, the target UART execution module 120 can configure the level state of the second arbitration port thereof to be the first state, and the level state of the first arbitration port of the UART control module 110 is then the first state, so as to ensure that only the target UART execution module 120 is transmitting data to the UART control module 110 at this time.
The first state is, for example, a low state.
In one embodiment, as shown in fig. 1, the multicast system further includes: pull up module 150. The first end of the pull-up module 150 is connected to the first arbitration port and each second arbitration port, and the second end of the pull-up module 150 is configured to receive the preset voltage signal VCC, and the pull-up module 150 is configured to change the level state of each second arbitration port to a second state when no data signal is output from the transmitting port of each UART executing module 120, where the second state is different from the first state.
The second state is, for example, a high state.
In this embodiment, when none of the transmitting ports of each UART executing module 120 of the plurality of UART executing modules 120 outputs a data signal, the pull-up module 150 configures the level state of each second arbitration port to be the second state, and the level state of the first arbitration port of the UART control module 110 becomes the second state accordingly, and when the transmitting port of the target UART executing module 120 transmits a data signal to the receiving port of the UART control module 110 through the aggregation module 140, the target UART executing module 120 configures the level state of the second arbitration port thereof to be the first state, and the level state of the first arbitration port of the UART control module 110 becomes the first state accordingly.
For example, when the transmitting ports of the target UART execution modules 120 in the UART execution modules 120 need to transmit data signals to the receiving ports of the UART control module 110 through the summarizing module 140, the target UART execution module 120 may detect the level state of the first arbitration port of the UART control module 110, and if the detection result is a high level state, which indicates that no data signal is output from the transmitting ports of the UART execution modules 120 in the UART execution modules 120, the transmitting ports of the target UART execution modules 120 may transmit data signals to the receiving ports of the UART control module 110 through the summarizing module 140, so that the target UART execution module 120 pulls the level state of the second arbitration port thereof down to a low level state, and meanwhile, the level state of the first arbitration port of the UART control module 110 jumps to the low level state.
After the data signal is sent by the target UART executing module 120, the pull-up module 150 pulls up the level state of each second arbitration port to a high level state, and the level state of the first arbitration port of the UART control module 110 jumps to the high level state accordingly.
In the process of transmitting the data signal by the target UART execution module 120, if the transmitting port of any other UART execution module 120 needs to transmit the data signal to the receiving port of the UART control module 110 through the summarizing module 140, the UART execution module 120 will detect the level state of the first arbitration port of the UART control module 110, and the detection result is a low level state, so that the UART execution module 120 knows that the target UART execution module 120 is transmitting the data signal to the UART control module 110 at this time, and therefore the UART execution module 120 will not transmit the data signal to the UART control module 110 yet, and the UART execution module 120 will enter a waiting mode to wait for the target UART execution module 120 to transmit the data signal.
In this embodiment, the UART execution modules 120 transmit data signals to the UART control module 110 in a time-sharing and staggered manner, so that data congestion or data errors caused by the plurality of UART execution modules 120 transmitting data signals to the UART control module 110 at the same time can be avoided, thereby ensuring the quality of the UART execution modules 120 transmitting data signals to the UART control module 110, and realizing reliable transmission of data signals.
Optionally, the pull-up module 150 includes: and a resistor unit. The first end of the resistor unit is the first end of the pull-up module 150, and the second end of the resistor unit is the second end of the pull-up module 150.
Optionally, the resistor unit includes: a resistive element R. The first end of the resistor element R is the first end of the resistor unit, and the second end of the resistor element R is the second end of the resistor unit.
In this embodiment, the pull-up module 150 only includes a resistor element, so that the structure of the pull-up module 150 is simple, and further the hardware structure of the multicast system is simple.
In one embodiment, with continued reference to fig. 1, the summarization module 140 further includes a first power terminal and the buffering module 130 further includes a second power terminal, the first power terminal and the second power terminal being respectively connected to the second terminal of the pull-up module 150. I.e. the first power terminal of the summarizing module 140 and the second power terminal of the buffer module 130 may both be connected to the preset voltage signal VCC.
In this embodiment, the pull-up module 150 and the preset voltage signal VCC form an external circuit. When none of the transmitting ports of each UART executing module 120 of the plurality of UART executing modules 120 outputs a data signal, the external circuit pulls up the level state of the first arbitration port of the UART control module 110 to a high level state. When the transmitting port of the target UART executing module 120 of the plurality of UART executing modules 120 transmits a data signal to the receiving port of the UART control module 110 through the summarizing module 140, the level state of the first arbitration port of the UART control module 110 is pulled down to a low level state by the target UART executing module 120. After the target UART executing module 120 finishes transmitting the data signal, the external circuit pulls up the level state of the first arbitration port of the UART control module 110 to the high level state. In the period when the target UART execution module 120 transmits the data signal, if any other UART execution module 120 needs to transmit data to the UART control module 110, it is necessary to wait for the target UART execution module 120 to transmit the data signal.
In one embodiment, the transmit port of the UART control module 110 transmits the control data signal according to a first preset data format. The first preset data format is as follows: a first preset address header and a target data signal located after the first preset address header; the first preset address head comprises address bits and data bits positioned behind the address bits, wherein the byte number of the target data signal is equal to the data size represented by the data bits in the first preset address head.
Illustratively, referring to FIG. 3, the first preset address header includes 8 BITs (BIT), wherein the 7~5 th BIT is an address BIT and the 4~0 th BIT is a data BIT. Address bits of the 7~5 th bit may be used to represent address information of the UART execution module 120; for example, address bits of 7~5 bits are used to indicate which UART execution module 120 the control data signal sent by UART control module 110 is to be sent to which UART execution module 120. The data size represented by the 4~0 bit data bit is the byte number of the target data signal in the control data signal; for example, the data size represented by the 4~0 bit data bit is a decimal number 16, and the data amount of the target data signal in the control data signal is 16 BYTEs (BYTE). MSB represents the most significant bit; LSB represents the least significant bit; ADD represents an address interval; CNT denotes a count interval.
The number of bits of the address bits in the first preset address header may determine the number of UART execution modules 120 with which the UART control module 110 performs multicast communication. For example, if the number of bits of the address bits is 3 bits, the number of UART execution modules 120 with which the UART control module 110 performs multicast communication may be 2 3 In practical application, since the number is 8, but in practice, 000 is also needed to represent the broadcast address, the number of UART execution modules 120 with which the UART control module 110 performs multicast may be 8-1=7.
In this embodiment, when the UART control module 110 sends a data signal to the UART executing module 120, the data signal may be a control data signal. The UART control module 110 first transmits a first preset address header followed by a target data signal in the transmission control data signal. The UART control module 110 sends the control data signal to the buffer module 130, and the buffer module 130 divides the control data signal into a plurality of identical independent non-interfering control data signals and synchronously transmits the plurality of control data signals to the corresponding UART executing modules 120. When each UART executing module 120 receives the control data signal, each UART executing module 120 checks whether the address information indicated by the address bit in the received control data signal matches with the own address information, checks that the UART executing module 120 indicated by the address bit in the received control data signal matches with the own address information, confirms that the received control data signal is successful (the UART executing module 120 is the target UART executing module 120), and checks that the UART executing module 120 indicated by the address bit in the received control data signal does not match with the own address information ignores the received control data signal, and at this time, the UART controlling module 110 completes the transmission of the control data signal to the target UART executing module 120.
In one embodiment, the transmit port of the UART execution module 120 generates the execution data signal according to a second predetermined data format. The second preset data format is as follows: the second preset address head and a target data signal positioned behind the second preset address head; the second preset address header includes address bits and data bits located after the address bits, wherein the number of bytes of the execution data signal is equal to the data size represented by the data bits in the second preset address header.
Illustratively, referring to fig. 4, the second preset address header includes 8 bits, wherein the 7~5 th bit is an address bit and the 4~0 th bit is a data bit. Address bits of the 7~5 th bit may be used to represent address information of the UART execution module 120; the UART control module 110, upon receiving the execution data signal, may determine from which UART execution module 120 the execution data signal comes according to the address information represented by the 7~5 th bit address bit. The data size indicated by the 4~0 bit data bit is the number of bytes of the target data signal in the execution data signal, for example, the data size indicated by the 4~0 bit data bit is decimal number 16, and the data size of the target data signal in the execution data signal is 16 bytes.
In this embodiment, the difference between the UART executing module 120 sending the data signal to the UART control module 110 and the UART controlling module 110 sending the data signal to the UART executing module 120 is that: the UART control module 110 may directly send a data signal to the UART executing module 120 through the buffer module 130 according to a first preset data format; when a UART execution module 120 needs to send a data signal to the UART control module 110, the UART execution module 120 needs to first determine the level state of the first arbitration port of the UART control module 110, if the level state is the second state, which indicates that no UART execution module 120 is sending a data signal to the UART control module 110, the UART execution module 120 may configure the level state of the first arbitration port of the UART control module 110 to be the first state and send a data signal to the UART control module 110 according to the second preset data format, and if the level state of the first arbitration port of the UART control module 110 is determined to be the first state, which indicates that the UART execution module 120 is sending a data signal to the UART control module 110, the UART execution module 120 needs to wait until the level state of the first arbitration port of the UART control module 110 jumps to be the second state, which indicates that the UART execution module 120 can send a data signal to the UART control module 110 according to the second preset data format.
In this embodiment, the structure of the summarizing module 140 may be various, and several of them are described below as examples:
in one embodiment, the summarization module 140 includes: a first and gate device. The first AND gate device is configured with an output port and a plurality of input ports; the output port of the first and gate device is the output end of the summarizing module 140, and the input port of the first and gate device is the input end of the summarizing module 140.
In this embodiment, the summary module 140 includes a first and gate device, so that the summary module 140 has a simple structure, and further, the multicast system has a simple structure.
In one embodiment, referring to FIG. 4, the aggregation module 140 includes: n cascaded second and gate devices 1401. The second and gate device 1401 is configured with an output port and a plurality of input ports; the output port of the nth stage second and gate device 1401 is connected to the receiving port of the UART control module 110, the output port of the i-1 th stage second and gate device 1401 is connected to an input port of the ith stage second and gate device 1401, at least part of the input ports of each stage second and gate device 1401 are respectively used for correspondingly connecting to a transmitting port of a UART executing module 120, where i and n are positive integers, and n is greater than or equal to i > 1.
In this embodiment, the summarizing module 140 includes n cascaded second and gate devices 1401, so that a greater number of UART executing modules 120 in the multicast system can send data signals to the UART control module 110.
In one embodiment, referring to fig. 5, based on the above embodiment, the summarizing module 140 further includes: at least one third and gate device 1402. The third and gate device 1402 is configured with an output port and a plurality of input ports; the output port of the third and gate device 1402 is connected to an input port of any second and gate device 1401, and at least part of the input ports of the third and gate device 1402 are respectively connected to a transmitting port of a UART executing module 120.
In this embodiment, the summarizing module 140 includes n cascaded second and gate devices 1401 and at least one third and gate device 1402, so that a greater number of UART executing modules 120 in the multicast system can send data signals to the UART control module 110.
Illustratively, the first and gate device, the second and gate device 1401, and/or the third and gate device 1402 may be a chip SN74HCS21.
In this embodiment, the buffer module 130 may have various structures, and several of them are described below by way of example:
in one embodiment, the buffer module 130 includes: a first buffer device. The first buffer device is configured with an input port and a plurality of output ports; the input port of the first buffer device is an input end of the buffer module 130, and the output port of the first buffer device is an output end of the buffer module 130.
In this embodiment, the buffer module 130 includes the first buffer device, so that the structure of the buffer module 130 is simple, and further, the structure of the multicast system is simple.
In one embodiment, referring to fig. 6, the buffer module 130 includes: m cascaded second buffer devices 1301. The second buffer device 1301 is configured with an input port and a plurality of output ports; the input port of the 1 st stage second buffer device 1301 is connected with the transmitting port of the UART control module 110, the input port of the j th stage second buffer device 1301 is connected with an output port of the j-1 st stage second buffer device 1301, and at least part of the output ports of each stage second buffer device 1301 are respectively used for correspondingly connecting with the receiving port of a UART executing module 120, wherein m and j are positive integers, and m is greater than or equal to j > 1.
In this embodiment, the buffer module 130 includes m cascaded second buffer devices 1301, so that the UART control module 110 and a larger number of UART execution modules 120 in the multicast system can implement multicast.
In one embodiment, referring to fig. 7, on the basis of the above embodiment, the buffer module 130 further includes: at least one third buffer device 1302. The third buffer device 1302 is configured with an input port and a plurality of output ports; the input port of the third buffer device 1302 is connected to an output port of any one of the second buffer devices 1301, and at least part of the output ports of the third buffer device 1302 are respectively connected to a receiving port of a UART executing module 120.
In this embodiment, the buffer module 130 includes m cascaded second buffer devices 1301 and at least one third buffer device 1302, so that the UART control module 110 in the multicast system can implement multicast with a greater number of UART execution modules 120.
For example, the first, second, and/or third buffer devices 1301, 1302 may be the chip SN74HCS541.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A multi-point communication system, characterized in that the multi-point communication system comprises: the UART control module, the buffer module, the summarizing module and the UART executing modules;
the UART control module and the UART execution module are respectively provided with a receiving port and a transmitting port;
the buffer module comprises an input end and a plurality of output ends, wherein the buffer module comprises at least one buffer device, the input end of the buffer module is connected with the transmitting port of the UART control module, the plurality of output ends of the buffer module are respectively and correspondingly connected with the receiving ports of the UART execution modules, and the buffer module is used for dividing the data signals transmitted by the UART control module into a plurality of same data signals and respectively and correspondingly outputting the same data signals to each UART execution module;
the collecting module comprises an output end and a plurality of input ends, wherein the collecting module comprises at least one AND gate device, the plurality of input ends of the collecting module are respectively and correspondingly connected with the transmitting ports of the UART executing modules, the output end of the collecting module is connected with the receiving port of the UART control module, and the collecting module is used for transmitting data signals transmitted by the UART executing modules to the UART control module in a time sharing mode.
2. The multipoint communication system according to claim 1, wherein the UART control module is further configured with a first arbitration port, and each UART execution module is further configured with a second arbitration port;
the first arbitration ports are respectively connected with the second arbitration ports; wherein,
when a transmitting port of a target UART executing module transmits data to a receiving port of the UART control module through the summarizing module, the level state of a second arbitration port of the target UART executing module is a first state, and the level states of the second arbitration ports of other UART executing modules are changed into the first state in a following way; the target UART execution module is one of the plurality of UART execution modules.
3. The multipoint communication system according to claim 2, further comprising: a pull-up module;
the first end of the pull-up module is respectively connected with the first arbitration ports and the second arbitration ports, the second end of the pull-up module is used for receiving preset voltage signals, and the pull-up module is used for changing the level state of each second arbitration port to a second state under the condition that no data signal is output by the sending port of each UART execution module; wherein the second state is different from the first state.
4. The multipoint communication system according to claim 3, wherein the summary module further comprises a first power terminal and the buffer module further comprises a second power terminal;
the first power end and the second power end are respectively connected with the second end of the pull-up module.
5. The multipoint communication system according to claim 1, wherein the transmitting port of the UART control module transmits the control data signal according to a first preset data format; wherein the first preset data format includes:
a first preset address header and a target data signal located after the first preset address header; the first preset address header comprises address bits and data bits positioned behind the address bits, wherein the byte number of the target data signal is equal to the data size represented by the data bits in the first preset address header.
6. The system according to claim 1, wherein the transmitting port of the UART executing module transmits the execution data signal according to a second preset data format; wherein the second preset data format includes:
a second preset address header and a target data signal located after the second preset address header; the second preset address header includes an address bit and a data bit located after the address bit, wherein the number of bytes of the target data signal is equal to the data size represented by the data bit in the second preset address header.
7. The multipoint communication system according to claim 1, wherein the summarizing module comprises: n cascaded second AND gate devices;
the second AND gate device is configured with an output port and a plurality of input ports; wherein,
the output port of the second AND gate device of the nth stage is used for being connected with the receiving port of the UART control module, the output port of the second AND gate device of the ith-1 stage is connected with one input port of the second AND gate device of the ith stage, at least part of the input ports of the second AND gate devices of each stage are respectively used for being correspondingly connected with the transmitting port of the UART execution module, wherein n and i are positive integers, and n is more than or equal to i and is more than 1.
8. The multipoint communication system according to claim 7, wherein the summarizing module further comprises: at least one third AND gate device;
the third AND gate device is configured with an output port and a plurality of input ports; wherein,
the output port of the third AND gate device is connected with one input port of any second AND gate device, and at least part of the input ports of the third AND gate device are respectively used for correspondingly connecting with the transmitting port of one UART executing module.
9. The multipoint communication system according to claim 1, wherein the buffering module comprises: m cascaded second buffer devices;
the second buffer device is configured with an input port and a plurality of output ports; wherein,
the input port of the second buffer device of the 1 st stage is used for being connected with the transmitting port of the UART control module, the input port of the second buffer device of the j th stage is connected with an output port of the second buffer device of the j-1 st stage, at least part of the output ports of the second buffer devices of each stage are respectively used for being correspondingly connected with the receiving port of the UART execution module, wherein m and j are positive integers, and m is more than or equal to j and is more than 1.
10. The multipoint communication system according to claim 9, wherein the buffering module further comprises: at least one third buffer device;
the third buffer device is configured with an input port and a plurality of output ports; wherein,
the input port of the third buffer device is connected with an output port of any one of the second buffer devices, and at least part of the output ports of the third buffer device are respectively used for being correspondingly connected with a receiving port of the UART execution module.
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| CN110352582A (en) * | 2017-03-23 | 2019-10-18 | Lg 电子株式会社 | For supporting the uplink signal of the terminal of multiple transmission time intervals, multiple subcarrier spacings or multiple processing times to send or receive method and its equipment in a wireless communication system |
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