CN115878540A - PCIe device link training management method, management device and server - Google Patents
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Abstract
The invention relates to a PCIe device link training management method, a management device, a server, equipment and a storage medium, wherein the training management method comprises a link training failure repairing step, and comprises the following steps: acquiring a default preset initial value Px as a kth generation initial value, and performing link training on the PCIe device; judging whether the supplier ID and the equipment ID of the PCIe device can be read normally or not; if the PCIe link cannot be read normally, judging that the PCIe link training fails; acquiring a preset initial value Py as a new kth generation initial value for link retraining; after the link retraining is carried out on the PCIe device, whether the supplier ID and the equipment ID of the PCIe device can be read normally is judged again according to the first waiting time; if the PCIe link can be read normally, the PCIe link training is judged to be successful. Through the technical scheme, the problem that the key PCIe device link on the mainboard of the current server fails to train can be solved.
Description
Technical Field
The invention relates to the technical field of link training, in particular to a PCIe device link training management method, a management device and a server.
Background
On a server or a storage server based on an X86 platform, a CPU uses a PCIe high-speed bus to perform data interaction with other peripheral devices (such as a BMC chip, a network card chip, an NTB, a PCIe switch, an extensible add-in card and the like). Peripheral devices such as an NTB (network node bus) and a PCIe (peripheral component interface express) switch are generally used as key devices to be welded on a mainboard and are called onboard devices; the peripherals such as the network card, the FC card, the sas card and the like are connected through the expansion slot, and the peripheral device is called an external plug-in device.
The board carries the device because the welding on the mainboard, and PCIe walks all to solidify on the PCB board such as line, consequently will guarantee the uniformity of PCIe link SI signal on the mainboard. However, when the production quantity of the servers is large, some motherboards with poor consistency are inevitable; in addition, there may be some variation in the uniformity of the on-board devices. This results in critical devices on individual motherboards failing PCIe link training due to poor performance of the PCIe link SI.
PCIe link training is provided with a PCIe equalization technology which can perform equalization adjustment on EQ according to a PCIe Tx Preset initial value; the link training from PCIe gen1 to gen3, gen3 to gen4, gen4 to gen5 stages respectively corresponds to a plurality of PCIe sending end link equalization parameter Preset values of gen3 Tx Preset, gen4 Tx Preset and gen5 Tx Preset; each stage will make fine adjustment based on the initial value of Tx Preset;
currently, the intel platform performs 3 times of equalization adjustment for the gen3 stage, and performs more than 10 times of equalization adjustment for gen4 and gen 5; generally, in the gen3 stage, the situation that the training in the gen1 to gen3 stages cannot be completed due to unreasonable initial value setting occurs, so that the link training fails.
Disclosure of Invention
In order to solve the technical problem, the invention provides a PCIe device link training management method, a management device and a server.
In order to achieve the above object, the present invention provides a PCIe device link training management method for performing link training management on a key PCIe device on a server motherboard by a PCIe balancing technique, where the training management method includes a link training failure repair step, and includes:
acquiring a default preset initial value Px from a sending end link equalization parameter preset value set aiming at a kth generation PCIe protocol to be used as the kth generation initial value for carrying out link training on the PCIe device; the k generation initial value is an initial value of a link equalization parameter of a sending end when equalization adjustment is carried out on the k generation PCIe protocol, and k is not less than 2; the data of the preset value set of the link equalization parameters of the sending end are sequentially arranged according to the value;
after the link training is carried out on the PCIe device through the kth generation initial value, judging whether the supplier ID and the equipment ID of the PCIe device can be read normally or not;
if the PCIe link cannot be read normally, judging that the PCIe link training fails;
acquiring a preset initial value Py from the preset set of link equalization parameter of the transmitting end according to a preset value rule, and using the preset initial value Py as a new k-th generation initial value for link retraining of the PCIe device;
after the link retraining is carried out on the PCIe device, whether the supplier ID and the equipment ID of the PCIe device can be read normally is judged again according to the first waiting time;
and if the supplier ID and the equipment ID can be read normally after link retraining, judging that the PCIe link training is successful.
Further, after determining again whether the provider ID and the device ID of the PCIe device can be read normally according to the first latency, the link training failure repairing step further includes:
if the supplier ID and the equipment ID of the PCIe device can not be read normally after the link retraining, judging that the training of the PCIe link fails;
and sequentially taking values from the preset value set of link equalization parameters of the sending end according to a preset value increasing direction and/or a preset value decreasing direction in the preset value taking rule, wherein the values are used as new k-th generation initial values and are used for respectively retraining the link of the PCIe device until the PCIe link is successfully trained.
Further, the training management method further comprises a link stability checking step; the link stability checking step includes a link activity management step including:
after judging that the PCIe link training is successful, judging whether a link activity degree flag bit is 1 or not;
if the link activity flag bit is not 1, sequentially retraining the links according to preset retraining retry times; and setting the link retraining flag bit to be 1 during each link retraining, and judging whether the link activity flag bit is 1 again according to a second preset time interval.
Further, the link stability checking step further includes a link state management step, which includes:
when the link activity degree flag bit is 1, judging whether the link speed in the link state information is smaller than an expected speed value; if the speed is less than the preset speed, judging that the link speed reduction occurs; wherein the speed expected value matches a minimum specification of a maximum link speed in a link capability register;
when the link activity flag bit is 1, judging whether the link bandwidth in the link state information is smaller than a bandwidth expected value; if the number of the links is less than the preset value, judging that the link descending is generated; wherein the bandwidth expected value matches a minimum specification of a maximum link bandwidth in the link capability register.
Further, the link state management step further includes:
when the link speed reduction and/or the link channel reduction occur, the link disabling enabling operation is carried out in sequence according to the preset disabling enabling repetition times; and setting a disable bit in a link control register, setting a disable and enable time interval according to a preset operation time interval, and re-reading the link state information according to a second waiting time to judge whether the link state is normal or not.
Further, the link activity management step further includes:
if the link activity flag bit is 1, printing the preset retraining retry times and link training negotiation result information to a log, and writing the log into a CPLD register; and the link training negotiation result information comprises a new k-th generation initial value corresponding to the successful link retraining.
Further, the link state management step further includes:
and when the link state information is normal, recording a log and writing a link training success mark into the CPLD register.
Further, after determining whether the provider ID and the device ID of the PCIe device can be read normally, the training management method further includes:
and if the supplier ID and the equipment ID of the PCIe device can be read normally, judging that the PCIe link training is successful, and recording a log.
Further, after the link retraining is performed in sequence according to the preset retraining retry number, the link activity management step further includes:
and when the link retraining is carried out according to the preset retraining retry times in sequence and the link activity flag bit is not 1, printing the preset retraining retry times and the link training failure flag to a log and writing the log into a CPLD register.
Further, after the link disable enabling operation is performed in sequence according to the preset disable enabling repetition number, the link state management step further includes:
and when the link speed reduction and/or link channel reduction occurs in each retry after the link disabling operation is sequentially carried out according to the preset disabling repetition times, printing the preset disabling repetition times and the link training failure mark to a log, and writing the log into a CPLD register.
Further, after values are sequentially taken from the preset value set of link equalization parameters at the transmitting end according to the preset value increasing direction and/or the preset value decreasing direction in the preset value rule as a new kth generation initial value, the training management method further comprises:
and after traversing the values in the preset value aggregation of the link equalization parameters of the sending end in sequence according to the preset value increasing direction and/or the preset value decreasing direction in the preset value-taking rule to serve as a new k-th generation initial value, when all links fail to be retrained, recording logs and writing a link training failure mark into a CPLD register.
Further, before acquiring a default preset initial value Px from a set of preset values of link equalization parameters of a transmitting end set for a kth generation PCIe protocol as a kth generation initial value, the training management method further includes:
acquiring a preset value set of link equalization parameters of the sending end according to PCIe signal parameter characteristics of the server mainboard and large-scale sample test requirements of the server mainboard; and the preset value set of link equalization parameters at the transmitting end comprises the default preset initial value Px.
Further, after acquiring a default preset initial value Px from a set of preset values of link equalization parameters of a transmitting end set for a kth generation PCIe protocol as a kth generation initial value, the training management method further includes:
and taking the default preset initial value Px as a kth generation initial value, and performing PCIe link training on a PCIe root port of the server CPU.
Further, acquiring a default preset initial value Px from a set of preset values of link equalization parameters of a transmitting end set for a kth generation PCIe protocol, as a kth generation initial value, for performing link training on the PCIe device, specifically including:
and acquiring the default preset initial value Px from the sending end link balance parameter preset value set as a kth generation initial value, and performing link training on a CPU root port corresponding to the link where the PCIe device is located.
Further, after the link training is performed on the PCIe device through the kth-generation initial value, determining whether a vendor ID and a device ID of the PCIe device can be read normally, specifically including:
and acquiring and judging whether the supplier ID and the equipment ID of the PCIe device can be read normally through the basic input and output system firmware, and judging whether the PCIe link training of a PCIe bus and the CPU root port is successful.
Further, before acquiring a default preset initial value Px from a set of preset values of link equalization parameters of a transmitting end set for a kth generation PCIe protocol as a kth generation initial value and performing link training on the PCIe device, the training management method further includes:
and setting the preset value set of the link equalization parameters of the sending end through a register, and carrying out link training on a CPU root port corresponding to the link where the PCIe device is located.
The invention also provides a PCIe device link training management device, which is used for carrying out link training management on the key PCIe device of the server mainboard through a PCIe equalization technology, and the training management device comprises a link training failure repair unit, which comprises:
the link training unit is used for acquiring a default preset initial value Px from a transmitting end link balance parameter preset value set aiming at the kth generation PCIe protocol, taking the default preset initial value Px as the kth generation initial value and carrying out link training on the PCIe device; the k generation initial value is a transmitting end link equalization parameter initial value when equalization adjustment is carried out on the k generation PCIe protocol, and k is not less than 2; the data of the preset value set of the link equalization parameters of the sending end are sequentially arranged according to the value;
the link training judging unit is used for judging whether the supplier ID and the equipment ID of the PCIe equipment can be read normally after the PCIe equipment is subjected to link training through the kth generation initial value;
a training failure determination unit, configured to determine that PCIe link training fails when the vendor ID and the device ID cannot be read normally;
a link retraining unit, configured to obtain a preset initial value Py according to a preset value rule from the preset set of link equalization parameters at the sending end, use the preset initial value Py as a new kth-generation initial value, and perform link retraining on the PCIe device;
the link retraining judgment unit is used for judging whether the supplier ID and the equipment ID of the PCIe device can be read normally according to the first waiting time after the link retraining is carried out on the PCIe device;
and the link retraining success judging unit is used for judging that the PCIe link is trained successfully when the supplier ID and the equipment ID can be read normally after the link retraining is carried out.
The present invention further provides a computer device comprising a memory, a processor and a computer program, the computer program being stored on the memory and being executable on the processor, the processor implementing the following steps when executing the computer program:
acquiring a default preset initial value Px from a sending end link equalization parameter preset value set aiming at a kth generation PCIe protocol to be used as the kth generation initial value for carrying out link training on the PCIe device; the k generation initial value is an initial value of a link equalization parameter of a sending end when equalization adjustment is carried out on the k generation PCIe protocol, and k is not less than 2; the data of the preset value set of the link equalization parameters of the sending end are sequentially arranged according to the value;
after the link training is carried out on the PCIe device through the kth generation initial value, whether the supplier ID and the equipment ID of the PCIe device can be read normally is judged;
if the PCIe link cannot be read normally, judging that the PCIe link training fails;
acquiring a preset initial value Py from the preset set of link equalization parameter of the transmitting end according to a preset value rule, and using the preset initial value Py as a new k-th generation initial value for link retraining of the PCIe device;
after the link retraining is carried out on the PCIe device, whether the supplier ID and the equipment ID of the PCIe device can be read normally is judged again according to the first waiting time;
and if the supplier ID and the equipment ID can be read normally after link retraining, judging that the PCIe link training is successful.
The present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of:
acquiring a default preset initial value Px from a sending end link equalization parameter preset value set aiming at a kth generation PCIe protocol to be used as the kth generation initial value for carrying out link training on the PCIe device; the k generation initial value is an initial value of a link equalization parameter of a sending end when equalization adjustment is carried out on the k generation PCIe protocol, and k is not less than 2; the data of the preset value set of the link equalization parameters of the sending end are sequentially arranged according to the value;
after the link training is carried out on the PCIe device through the kth generation initial value, judging whether the supplier ID and the equipment ID of the PCIe device can be read normally or not;
if the PCIe link cannot be read normally, judging that the PCIe link training fails;
acquiring a preset initial value Py from the preset value set of the link equalization parameters of the transmitting end according to a preset value rule, and taking the preset initial value Py as a new kth generation initial value for link retraining of the PCIe device;
after the link retraining is carried out on the PCIe device, whether the supplier ID and the equipment ID of the PCIe device can be read normally is judged again according to the first waiting time;
and if the supplier ID and the equipment ID can be read normally after link retraining, judging that the PCIe link training is successful.
The invention also provides a server, which comprises a key PCIe device arranged on the mainboard, wherein the PCIe device realizes link training management through the PCIe device link training management method.
Compared with the prior art, the technical scheme of the invention has the following technical effects:
the PCIe device link training management method is used for carrying out link training management on key PCIe devices of a server mainboard through a PCIe equalization technology;
the training management method comprises a link training failure repairing step which comprises the following steps:
firstly, acquiring a default preset initial value Px as a kth generation initial value for performing link training on a PCIe device;
judging whether the supplier ID and the equipment ID of the PCIe device can be read normally or not; if the PCIe link cannot be read normally, judging that the PCIe link training fails;
then, acquiring a preset initial value Py as a new kth generation initial value for retraining a link of the PCIe device;
then judging whether the supplier ID and the equipment ID of the PCIe device can be read normally or not; if the supplier ID and the equipment ID can be read normally after the link retraining, judging that the PCIe link training is successful;
the method comprises the steps that a sending end link equalization parameter preset value set is set aiming at a kth generation PCIe protocol in advance, a default preset initial value Px can be obtained from the sending end link equalization parameter preset value set, and a preset initial value Py is obtained according to a preset value rule;
therefore, when the supplier ID and the equipment ID can be read normally, the success of PCIe link training can be judged, and the problem that the link training of key PCIe devices on the main board of the server fails is solved.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a diagram of a prior art link training 10 set of Tx presets;
FIG. 2 is a flowchart illustrating a PCIe device link training management method according to an embodiment of the present invention;
FIG. 3 is a schematic overall flow chart of a link training management method in an actual embodiment of the present invention;
fig. 4 is a block diagram of a PCIe device link training management method and apparatus according to a second embodiment of the present invention;
fig. 5 is an internal structural diagram of a computer device according to a second embodiment of the present invention.
Description of the preferred embodiment
As shown in fig. 1, in the prior art, there are 10 sets of Tx Preset values Tx Preset (i.e. Preset values of link equalization parameters at the transmitting end) at gen3, gen4, and gen5 stages of PCIe link training.
The Bios (i.e., bios firmware) boot-up phase sets a default (e.g., the initial default for the Intel xx platform is P7); however, practical tests find that the P7 preset value in the gen3 stage does not meet the requirements of the current main board PCB and the SI parameter of the key PCIe device;
performing multi-sample test on the current mainboard, and finding that the requirement of SI parameters can be better met when Tx Preset = P4 in the gen3 stage; however, the SI parameter requirements of all motherboards cannot be met when Tx Preset = P4, and when the SI parameters of individual motherboards and key PCIe devices have consistency differences, the gen3 link training still fails.
Therefore, the invention provides a PCIe device link training management method, a PCIe device link training management apparatus, and a server to solve the above problems.
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The first embodiment is as follows:
as shown in fig. 2, an embodiment of the present invention provides a PCIe device link training management method, which is used to perform link training management on a critical PCIe device on a server motherboard through a PCIe balancing technology, where the training management method includes a link training failure repair step, and includes:
s2, acquiring a default preset initial value Px from a preset value set of link equalization parameters of a transmitting end aiming at the kth generation PCIe protocol, taking the default preset initial value Px as the kth generation initial value, and performing link training on a PCIe device; the k generation initial value is an initial value of a link equalization parameter of a sending end when equalization adjustment is carried out on the k generation PCIe protocol, and k is not less than 2; data of the preset value set of link equalization parameters of the sending end are sequentially arranged according to the size of the values;
s3, after the PCIe device is subjected to link training through the kth generation initial value, judging whether the supplier ID and the equipment ID of the PCIe device can be read normally or not;
s31, if the PCIe link cannot be read normally, judging that the PCIe link training fails;
s4, acquiring a preset initial value Py from the preset value set of the link equalization parameters of the sending end according to a preset value rule, and taking the preset initial value Py as a new kth generation initial value for link retraining of the PCIe device;
s5, after retraining the link of the PCIe device, judging whether the supplier ID and the equipment ID of the PCIe device can be read normally again according to the first waiting time;
s51, if the supplier ID and the equipment ID can be read normally after the link retraining, judging that the PCIe link training is successful.
In a specific embodiment, the training management method includes a link training failure recovery step, which includes:
firstly, acquiring a default preset initial value Px as a kth generation initial value for carrying out link training on a PCIe device;
judging whether the supplier ID and the equipment ID of the PCIe device can be read normally; if the PCIe link cannot be read normally, judging that the PCIe link training fails;
then, acquiring a preset initial value Py as a new kth generation initial value for retraining a link of the PCIe device;
then judging whether the supplier ID and the equipment ID of the PCIe device can be read normally or not; if the supplier ID and the equipment ID can be read normally after link retraining, judging that the PCIe link training is successful;
the method comprises the steps that a sending end link equalization parameter preset value set is set aiming at a kth generation PCIe protocol in advance, a default preset initial value Px can be obtained from the sending end link equalization parameter preset value set, and a preset initial value Py is obtained according to a preset value rule;
therefore, when the supplier ID and the equipment ID can be read normally, the success of PCIe link training can be judged, and the problem that the link training of key PCIe devices on the main board of the server fails is solved.
In practice, PCIe stands for PCI-Express (peripheral component interconnect Express), which is a high-speed serial computer expansion bus standard.
The PCIe Tx Preset represents a PCIe transmitting end link equalization parameter Preset value. PCIe SI represents PCIe signal parameters.
PCIe gen3, gen4, gen5 represent PCIe protocol generations and may also be used to express the speed achieved after PCIe link negotiation, from gen1 to gen5, which support speeds of 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32.0GT/s, respectively.
As shown in fig. 3, in an actual embodiment, the link training management method mainly includes the following stages:
stage 1, a Bios starting stage initiates link training for PCIe, and before the link training, a gen3 Tx Preset initial value of a CPU rootPort (namely a root port) corresponding to a link where an onboard key PCIe device is located is set into a register;
wherein, the gen3 Tx Preset initial value is a Preset initial value (such as gen3 Tx Preset = P4) obtained by hardware according to PCIe SI parameter characteristics of the server mainboard and performing a large number of sample tests;
stage 3, bios determines if the PCIe link training of the PCIe bus and CPU RootPort was successful by checking if the VID (i.e., vendor ID), DID (i.e., device ID) of the onboard critical PCIe device can be read normally.
When VID and DID of onboard key PCIe devices can be read normally, judging that the link training is successful, and recording logs; continuing the bios operation;
when VID and DID of the onboard key PCIe device cannot be read, adjusting a PCIe Gen3 Tx Preset initial value of a CPU rootPort corresponding to a link where the onboard key PCIe device is located, and retrying the link, wherein the PCIe Gen3 Tx Preset initial value adjusting method is detailed in a stage 5.
Step 4, after the initial value of PCIe Gen3 Tx Preset is modified, link retraining operation is initiated on a rootport port connected with a key PCIe device, and then after 15ms, whether VID and DID of the key PCIe device can be read normally is checked;
when VID and DID of onboard key PCIe devices can be read normally, judging that the link training is successful, recording logs, and continuing the operation of bios;
otherwise, repeating the stage 4 and the stage 5;
phase 5, PCIe Gen3 Tx Preset initial value adjustment proceeds as follows:
starting from a default Preset initial value P4, firstly setting the PCIe link to the direction of increasing the Preset value once (for example: PCIe Gen3 Tx Preset = P5), and then initiating the PCIe link retraining;
if the link training is judged to be failed, setting the direction of reducing the Preset initial value once again (such as PCIe Gen3 Tx Preset = P3), and then initiating PCIe link retraining;
until the two direction preset values reach P0 and P9, respectively.
In conclusion, under the condition that the PCIe link training algorithm of the CPU end is not changed, the initial value of the gen3 stage Tx Preset is adaptively adjusted through bios according to the link training result; and then, the PCIe link training is restarted to solve the problem of the starting failure of the key PCIe device of the mainboard with poor SI consistency.
In a preferred embodiment, after S3, the training management method further includes:
s32, if the supplier ID and the equipment ID of the PCIe device can be read normally, judging that the PCIe link training is successful, and recording a log.
In an actual embodiment, when VID and DID of an onboard key PCIe device can be read normally, the success of link training is judged, and a log is recorded; bios continues to run.
In a preferred embodiment, after S5, the link training failure repairing step further includes:
s521, if the supplier ID and the equipment ID of the PCIe device cannot be read normally after the link retraining, judging that the PCIe link training fails;
and S522, sequentially taking values from the sending end link equalization parameter preset value combination in the preset value increasing direction and/or the preset value decreasing direction in the preset value taking rule as a new kth generation initial value, and respectively performing link retraining on the PCIe device until the PCIe link training succeeds.
In a specific embodiment, data of a preset value set of link equalization parameters of a sending end are sequentially arranged according to the size of the values; and values can be taken from the preset value set of the link equalization parameters of the sending end according to a preset value taking rule and taken as a kth generation initial value to carry out link training or link retraining on the PCIe device.
In an actual embodiment, in the link training management method, adaptive adjustment and link training may also be performed in a circulating manner:
step 4, after the initial value of PCIe Gen3 Tx Preset is modified, link retraining operation is initiated on a rootport port connected with a key PCIe device, and then after 15ms, whether VID and DID of the key PCIe device can be read normally is checked;
when VID and DID of on-board key PCIe devices can be read normally, judging that the link training is successful, recording logs, and continuing to operate the bios;
otherwise, repeating the stage 4 and the stage 5;
stage 5, PCIe Gen3 Tx Preset initial value adjustment is performed according to the following algorithm:
starting from a default Preset initial value P4, firstly setting the PCIe link to the direction of increasing the Preset value once (for example: PCIe Gen3 Tx Preset = P5), and then initiating the PCIe link retraining;
if the link training is judged to be failed, setting the direction of reducing the Preset initial value once again (such as PCIe Gen3 Tx Preset = P3), and then initiating PCIe link retraining;
until the two direction preset values reach P0 and P9, respectively.
Therefore, the success of the link training is ensured by circularly performing the self-adaptive adjustment and the link training.
In addition, if the link training fails, retry is not performed, a log is recorded, a link training failure mark is recorded to the CPLD, and the key PCIe device link training process is exited.
In a preferred embodiment, after S522, the training management method further includes:
s523, after traversing the values in the preset value set of the link equalization parameter at the transmitting end in the preset value increasing direction and/or the preset value decreasing direction in the preset value rule in sequence as the new k-th generation initial value, when all the links fail to be retrained again, recording the log, and writing the link training failure flag into the CPLD register.
In a practical embodiment, in phase 5 of the link training management method, the method further includes:
if the link training fails, the retry is not performed, the log is recorded, the link training failure mark is recorded to the CPLD, and the key PCIe device link training process is exited.
In a preferred embodiment, the training management method further comprises a link stability checking step; the link stability checking step includes a link activity management step including:
s6, after judging that the PCIe link training is successful, judging whether the link activity degree flag bit is 1 or not;
s61, if the link activity flag bit is not 1, sequentially retraining the links according to the preset retraining retry times; and setting the link retraining flag bit to be 1 during each link retraining, and judging whether the link activity flag bit is 1 again according to a second preset time interval.
In particular embodiments, in addition, in order to ensure that the link liveness and the link state meet expectations after the link training of the critical PCIe device, the link liveness and the link state are respectively checked during the link training process;
when the link activity degree is abnormal, the link is decelerated or the link is degraded, the PCIe link retraining and the PCIe link disabling/enabling operation are respectively initiated for many times, and the stability of the key PCIe device link is further improved.
In an actual embodiment, the link stability checking step in the link training management method includes a link activity management step, which includes:
and 6, after the key PCIe device link training is successful, performing link activity check, and checking whether a link _ status register (namely a link state register) link activity flag bit on the root port is 1 or not to judge whether the connection between the root port and the lower equipment is normal or not.
If the link activity flag bit is 1, the Bios simultaneously prints the retry times and the negotiation result to a log and writes the retry times and the negotiation result into a CPLD register;
if the flag bit of the link activity degree is not 1, writing 1 on the flag bit of the link _ control register (namely a link control register) of the root port for retraining the link, and then waiting for 15ms and checking whether the flag bit of the link activity degree is 1;
if the link activity is not 1, three link retraining retries are initiated.
In a preferred embodiment, the link activity management step further comprises:
s62, if the link activity flag bit is 1, printing the preset retraining retry times and link training negotiation result information to a log, and writing the log into a CPLD register; the link training negotiation result information comprises a new k-th generation initial value corresponding to the successful link retraining.
In a practical embodiment, in the link activity management step of phase 6, if the link activity flag bit is 1, bios prints the retry number and negotiation result to the log at the same time and writes them into the CPLD register.
In a preferred embodiment, after S61, the link activity management step further includes:
and S63, when the link retraining is carried out according to the preset retraining retry times in sequence and the link activity flag bit is not 1, printing the preset retraining retry times and the link training failure flag into a log and writing the log into a CPLD register.
In a practical embodiment, the step of managing link liveness in phase 6 further comprises:
if the link activity flag bit is not 1 after the three retries, the Bios simultaneously prints the retries and the link training failure flag into the log and writes the log into the CPLD register, and exits the key PCIe device link training process.
In a preferred embodiment, the link stability checking step further comprises a link state management step, which comprises:
s71, when the link activity degree flag bit is 1, judging whether the link speed in the link state information is smaller than an expected speed value; if the speed is smaller than the preset speed, judging that the link speed reduction occurs; wherein, the expected speed value is matched with the minimum specification of the maximum link speed in the link capacity register;
s72, when the link activity flag bit is 1, judging whether the link bandwidth in the link state information is smaller than the expected bandwidth value; if the number is less than the preset value, judging that link descending occurs; wherein the bandwidth expected value matches a minimum specification of a maximum link bandwidth in the link capability register.
In a practical embodiment, the link stability checking step in the link training management method includes a link state management step, which includes:
and 7, after the link activity of the key PCIe device is normal, checking the link state, mainly checking the link speed and the link channel width, wherein the checking method comprises the following steps of:
checking whether the negotiated bandwidth and rate in the link state of the PCIe device are equal to an expected value; the expected value is the minimum specification of the maximum link speed and the maximum link width in a link capacity register of downstream equipment on a link where the PCIe equipment is located;
if the link speed is lower than the expected value after the negotiation of the PCIe equipment, the link speed reduction is considered to occur;
if the link width is smaller than the expected value after the negotiation of the PCIe devices, the link lane dropping is considered to occur.
In a preferred embodiment, the link state managing step further includes:
and S73, when the link state information is normal, recording a log and writing a link training success mark into the CPLD register.
In an actual embodiment, in the link state management step of stage 7, if the link state check is normal (for example, if the negotiated bandwidth and rate are equal to the expected values), the log is recorded, the link training success flag is written into the CPLD register, and the critical PCIe device link training process is exited.
In a preferred embodiment, the link state managing step further comprises:
s81, when the link speed reduction and/or the link channel reduction occur, the link disabling enabling operation is carried out in sequence according to the preset disabling enabling repetition times; and setting a disable bit in a link control register, setting a disable and enable time interval according to a preset operation time interval, and re-reading link state information according to a second waiting time to judge whether the link state is normal or not.
In a practical embodiment, the link state managing step further includes:
and stage 8, when the link speed reduction or the link channel reduction occurs, initiating 3 times of link incapability and link enabling:
the method comprises the steps that a disable bit (namely an energy-losing bit) of a RootPort configuration space link _ control register (namely a link control register) is set to realize a one-time energy-losing and enabling process, the time interval of energy losing and enabling is set to be 200ms, and the value of a configuration space link state is read again after 100ms is waited;
in a preferred embodiment, after S81, the link status management step further includes:
s82, after the link disabling operation is carried out in sequence according to the preset disabling repetition times, when the link speed reduction and/or the link channel reduction occur in each retry, the preset disabling repetition times and the link training failure mark are printed to a log and written into a CPLD register.
In a practical embodiment, the link state management step in phase 8 further includes:
if the link speed reduction or the link path reduction occurs in the link failure and the link enabling retry of 3 times, the Bios simultaneously prints the retry times and the link training failure mark into a log and writes the log into a CPLD register, and the key PCIe device link training process is exited.
In a preferred embodiment, before S2, the training management method further includes:
s1, acquiring a preset value set of link equalization parameters of a sending end according to PCIe signal parameter characteristics of a server mainboard and large-scale sample test requirements of the server mainboard; the preset value set of the link equalization parameters at the transmitting end comprises a default preset initial value Px.
In a preferred embodiment, after S2, the training management method further includes:
and taking the default preset initial value Px as a kth generation initial value, and performing PCIe link training on a PCIe root port of the CPU of the server.
In a preferred embodiment, before S2, the training management method further includes:
and setting a preset value set of link equalization parameters of the sending end through a register, and carrying out link training on a CPU root port corresponding to a link where the PCIe device is located.
In a practical embodiment, the link training management method includes the following stages:
stage 1, a Bios starting stage initiates link training for PCIe, and before the link training, a gen3 Tx Preset initial value of a CPU rootPort (namely a root port) corresponding to a link where an onboard key PCIe device is located is set into a register;
the gen3 Tx Preset initial value is a Preset initial value (for example: gen3 Tx Preset = P4) obtained by hardware according to PCIe SI parameter characteristics of the server mainboard and performing a large number of sample tests.
And 2, when the PCIe root port corresponding to the CPU is trained, using a gen3 Tx Preset initial value to carry out PCIe link training.
In a preferred embodiment, S2 specifically includes:
and acquiring a default preset initial value Px from the preset value set of the link equalization parameters of the sending end as a kth generation initial value, and performing link training on a CPU root port corresponding to the link where the PCIe device is located.
In a preferred embodiment, S3 specifically includes:
and acquiring and judging whether the supplier ID and the equipment ID of the PCIe device can be read normally through the basic input and output system firmware, and judging whether the PCIe link training of the PCIe bus and the CPU root port is successful.
In addition, the link training management method also comprises the following stages:
stage 3, bios determines if the PCIe link training of the PCIe bus to CPU RootPort was successful by checking if the VID (i.e., vendor ID), DID (i.e., device ID) of the onboard critical PCIe device can be read normally.
When VID and DID of onboard key PCIe devices can be read normally, judging that the link training is successful, and recording logs; bios continues to run. In a practical embodiment, the training management method further includes:
stage 1, a Bios starting stage initiates link training for PCIe, and before the link training, a gen3 Tx Preset initial value of a CPU rootPort (namely a root port) corresponding to a link where an onboard key PCIe device is located is set into a register;
wherein, the gen3 Tx Preset initial value is a Preset initial value (such as gen3 Tx Preset = P4) obtained by hardware according to PCIe SI parameter characteristics of the server mainboard and performing a large number of sample tests;
and 2, when the corresponding CPU PCIe root port is trained, carrying out PCIe link training by using a gen3 Tx Preset initial value.
In summary, the PCIe device link training management method provided by the present invention has the following advantages:
1) By means of the bios self-adaptive adjustment of the gen3 Tx Preset initial value before the PCIe link training in the starting stage, the problem of starting failure of a key PCIe device of the mainboard with poor SI consistency is solved.
2) Meanwhile, checking the link liveness and the link state; when the link activity degree is abnormal, the link is decelerated or the link is degraded, the operations of PCIe link retraining and PCIe link disabling/enabling are respectively initiated for many times, and the stability of the key PCIe device link is further improved.
It should be noted that, although the steps in the flowchart are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a portion of the steps in the flowchart may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The second embodiment:
as shown in fig. 4, an embodiment of the present invention further provides a PCIe device link training management apparatus, configured to perform link training management on a key PCIe device on a server motherboard through a PCIe balancing technique, where the training management apparatus includes a link training failure recovery unit, and the link training failure recovery unit includes:
the link training unit is used for acquiring a default preset initial value Px from a sending end link equalization parameter preset value set aiming at a kth generation PCIe protocol, taking the default preset initial value Px as the kth generation initial value and carrying out link training on a PCIe device; the k generation initial value is an initial value of a link equalization parameter of a sending end when equalization adjustment is carried out on the k generation PCIe protocol, and k is not less than 2; data of the link equalization parameter preset value set of the sending end are sequentially arranged according to the value;
the link training judging unit is used for judging whether the supplier ID and the equipment ID of the PCIe equipment can be read normally after the PCIe equipment is subjected to link training through the kth generation initial value;
the training failure judging unit is used for judging the training failure of the PCIe link when the supplier ID and the equipment ID cannot be read normally;
the link retraining unit is used for acquiring a preset initial value Py from the preset value set of the link equalization parameters of the sending end according to a preset value rule, taking the preset initial value Py as a new kth generation initial value and performing link retraining on the PCIe device;
the link retraining judgment unit is used for judging whether the supplier ID and the equipment ID of the PCIe device can be read normally according to the first waiting time after the link retraining is carried out on the PCIe device;
and the link retraining success judging unit is used for judging that the PCIe link is trained successfully when the supplier ID and the equipment ID can be read normally after the link retraining is carried out.
In a preferred embodiment, the link training failure recovery unit further includes:
the link retraining failure determination unit is used for determining that the PCIe link training fails if the supplier ID and the equipment ID of the PCIe device cannot be read normally after the link retraining;
and the circulating link retraining unit is used for sequentially taking values from the preset value set of the link equalization parameters of the sending end according to the preset value increasing direction and/or the preset value decreasing direction in the preset value taking rule, taking the values as new kth generation initial values, and respectively retraining the link of the PCIe device until the PCIe link is successfully trained.
In a preferred embodiment, the training management device further comprises a link stability checking unit; the link stability checking unit includes a link activity management unit including:
the link activity flag bit judging unit is used for judging whether the link activity flag bit is 1 or not after judging that the PCIe link training is successful;
a link activity recovery unit, configured to perform link retraining in sequence according to preset retraining retry times if a link activity flag bit is not 1; and when the link is retrained each time, setting the link retraining flag bit to be 1, and judging whether the link activity degree flag bit is 1 again according to a second preset time interval.
In a preferred embodiment, the training management device further comprises a link state management unit, which comprises:
the link disabling operation unit is used for sequentially carrying out link disabling operation according to preset disabling repetition times when link speed reduction and/or link channel reduction occurs; and setting a disable bit in a link control register, setting a disable and enable time interval according to a preset operation time interval, and re-reading link state information according to a second waiting time to judge whether the link state is normal or not.
In a preferred embodiment, the link stability checking unit further comprises a link status management unit, which comprises:
the link speed reduction judging unit is used for judging whether the link speed in the link state information is less than an expected speed value or not when the link activity degree flag bit is 1; if the speed is less than the preset speed, judging that the link speed reduction occurs; wherein the speed expected value matches a minimum specification of a maximum link speed in a link capability register;
the link descending judging unit is used for judging whether the link bandwidth in the link state information is smaller than an expected bandwidth value or not when the link activity degree flag bit is 1; if the number of the links is less than the preset value, judging that the link descending is generated; wherein the bandwidth expected value matches a minimum specification of a maximum link bandwidth in the link capability register.
In a preferred embodiment, the link retraining success determining unit is further configured to:
if the link activity flag bit is 1, printing the preset retraining retry times and link training negotiation result information to a log, and writing the log into a CPLD register; and the link training negotiation result information comprises a new k-th generation initial value corresponding to the successful link retraining.
In a preferred embodiment, the link retraining success determining unit is further configured to:
and when the link state information is normal, recording a log and writing a link training success mark into the CPLD register.
In a preferred embodiment, the link retraining success determining unit is further configured to:
and if the supplier ID and the equipment ID of the PCIe device can be read normally, judging that the PCIe link training is successful, and recording a log.
In a preferred embodiment, the link retraining failure determining unit is further configured to:
and when the link retraining is carried out according to the preset retraining retry times in sequence and the link activity flag bit is not 1, printing the preset retraining retry times and the link training failure flag to a log and writing the log into a CPLD register.
In a preferred embodiment, the link retraining failure determining unit is further configured to:
and when the link speed reduction and/or link channel reduction occurs in each retry after the link disabling operation is sequentially carried out according to the preset disabling repetition times, printing the preset disabling repetition times and the link training failure mark to a log, and writing the log into a CPLD register.
In a preferred embodiment, the link retraining failure determining unit is further configured to:
and after traversing the values in the preset value aggregation of the link equalization parameters of the sending end in sequence according to the preset value increasing direction and/or the preset value decreasing direction in the preset value-taking rule to serve as a new k-th generation initial value, when all links fail to be retrained, recording logs and writing a link training failure mark into a CPLD register.
In a preferred embodiment, the training management device further comprises:
a default value set acquiring unit, configured to acquire a default value set of link equalization parameters of the sending end according to PCIe signal parameter characteristics of the server motherboard and a large-scale sample test requirement of the server motherboard; and the preset value set of the link equalization parameters at the transmitting end comprises the default preset initial value Px.
In a preferred embodiment, the link training unit is further configured to:
and taking the default preset initial value Px as a kth generation initial value, and performing PCIe link training on a PCIe root port of the server CPU.
For the specific limitations of the above apparatus, reference may be made to the limitations of the above method, which are not described herein again.
The modules in the above device can be implemented wholly or partially by software, hardware and their combination. The modules can be embedded in a hardware form or independent from a processor in the computer device, or can be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
As shown in fig. 5, the computer device may be a terminal including a processor, a memory, a network interface, a display screen, and an input device connected through a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
It will be appreciated that the arrangements shown in the above figures are merely block diagrams of some of the arrangements relevant to the inventive arrangements and do not constitute limitations on the computer apparatus to which the inventive arrangements may be applied, as a particular computer apparatus may comprise more or less components than those shown in the figures, or some of the components may be combined, or have a different arrangement of components.
All or part of the processes of the methods of the embodiments can be implemented by a computer program that can be stored in a non-volatile computer-readable storage medium and that, when executed, can include the processes of the embodiments of the methods.
Any reference to memory, storage, databases, or other media used in embodiments provided herein may include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (20)
1. A PCIe device link training management method is used for carrying out link training management on a key PCIe device of a server mainboard through a PCIe equalization technology, and the training management method comprises a link training failure repairing step and comprises the following steps:
acquiring a default preset initial value Px from a sending end link equalization parameter preset value set aiming at a kth generation PCIe protocol to be used as the kth generation initial value for carrying out link training on the PCIe device; the k generation initial value is an initial value of a link equalization parameter of a sending end when equalization adjustment is carried out on the k generation PCIe protocol, and k is not less than 2; the data of the preset value set of the link equalization parameters of the sending end are sequentially arranged according to the value;
after the link training is carried out on the PCIe device through the kth generation initial value, judging whether the supplier ID and the equipment ID of the PCIe device can be read normally or not;
if the PCIe link cannot be read normally, judging that the PCIe link training fails;
acquiring a preset initial value Py from the preset value set of the link equalization parameters of the transmitting end according to a preset value rule, and taking the preset initial value Py as a new kth generation initial value for link retraining of the PCIe device;
after the link retraining is carried out on the PCIe device, whether the supplier ID and the equipment ID of the PCIe device can be read normally or not is judged again according to a first waiting time;
and if the supplier ID and the equipment ID can be read normally after link retraining, judging that the PCIe link training is successful.
2. The PCIe device link training management method according to claim 1, wherein after determining again whether the vendor ID and the device ID of the PCIe device can be read normally according to the first latency, the link training failure repair step further includes:
if the supplier ID and the equipment ID of the PCIe device can not be read normally after the link retraining, judging that the training of the PCIe link fails;
and sequentially taking values from the preset value set of link equalization parameters of the sending end according to a preset value increasing direction and/or a preset value decreasing direction in the preset value taking rule, wherein the values are used as new k-th generation initial values and are used for respectively retraining the link of the PCIe device until the PCIe link is successfully trained.
3. The PCIe device link training management method as recited in claim 1 or 2, wherein said training management method further comprises a link stability checking step; the link stability checking step includes a link activity management step including:
after judging that the PCIe link training is successful, judging whether a link activity degree flag bit is 1 or not;
if the link activity flag bit is not 1, sequentially retraining the links according to preset retraining retry times; and setting the link retraining flag bit to be 1 during each link retraining, and judging whether the link activity flag bit is 1 again according to a second preset time interval.
4. The PCIe device link training management method of claim 3 wherein said link stability checking step further comprises a link state management step comprising:
when the link activity degree flag bit is 1, judging whether the link speed in the link state information is less than an expected speed value; if the speed is smaller than the preset speed, judging that the link speed reduction occurs; wherein the speed expected value matches a minimum specification of a maximum link speed in a link capability register;
when the link activity flag bit is 1, judging whether the link bandwidth in the link state information is smaller than a bandwidth expected value; if the number is less than the preset value, judging that link descending occurs; wherein the bandwidth expected value matches a minimum specification of a maximum link bandwidth in the link capability register.
5. The PCIe device link training management method of claim 4, the link state management step further comprising:
when the link speed reduction and/or the link channel reduction occur, the link disabling enabling operation is carried out in sequence according to the preset disabling enabling repetition times; and setting a disable bit in a link control register, setting a disable and enable time interval according to a preset operation time interval, and re-reading the link state information according to a second waiting time to judge whether the link state is normal or not.
6. The PCIe device link training management method of claim 3, the link liveness management step further comprising:
if the link activity flag bit is 1, printing the preset retraining retry times and link training negotiation result information to a log, and writing the log into a CPLD register; and the link training negotiation result information comprises a new kth generation initial value corresponding to the successful link retraining.
7. The PCIe device link training management method of claim 4, wherein said link state management step further comprises:
and when the link state information is normal, recording a log and writing a link training success mark into the CPLD register.
8. The PCIe device link training management method according to claim 1, wherein after determining whether the vendor ID and the device ID of the PCIe device can be read normally, the training management method further comprises:
and if the supplier ID and the equipment ID of the PCIe device can be read normally, judging that the PCIe link training is successful, and recording a log.
9. The PCIe device link training management method of claim 3, wherein after performing link retraining in order according to a preset retraining retry number, the link activity management step further comprises:
and when the link retraining is carried out according to the preset retraining retry times in sequence and the link activity flag bit is not 1, printing the preset retraining retry times and the link training failure flag to a log and writing the log into a CPLD register.
10. The PCIe device link training management method as defined in claim 5, wherein after performing the link disable operation in sequence according to a preset number of disable enabling repetitions, the link state management step further comprises:
and when the link speed reduction and/or link channel reduction occurs in each retry after the link disabling operation is sequentially carried out according to the preset disabling repetition times, printing the preset disabling repetition times and the link training failure mark to a log, and writing the log into a CPLD register.
11. The PCIe device link training management method according to claim 2, wherein after values are sequentially taken from the sending end link equalization parameter preset value set in the preset value increasing direction and/or the preset value decreasing direction in the preset value taking rule as a new kth generation initial value, the training management method further comprises:
and after traversing the values in the preset value aggregation of the link equalization parameters of the sending end in sequence according to the preset value increasing direction and/or the preset value decreasing direction in the preset value-taking rule to serve as a new k-th generation initial value, when all links fail to be retrained, recording logs and writing a link training failure mark into a CPLD register.
12. The PCIe device link training management method according to claim 2, before obtaining a default preset initial value Px from a sending-end link equalization parameter preset value set for a kth generation PCIe protocol as a kth generation initial value, the training management method further includes:
acquiring a preset value set of link equalization parameters of the sending end according to PCIe signal parameter characteristics of the server mainboard and large-scale sample test requirements of the server mainboard; and the preset value set of the link equalization parameters at the transmitting end comprises the default preset initial value Px.
13. The PCIe device link training management method according to claim 12, wherein after acquiring a default preset initial value Px from a sending-end link equalization parameter preset value set for a kth generation PCIe protocol as a kth generation initial value, the training management method further comprises:
and taking the default preset initial value Px as a kth generation initial value, and performing PCIe link training on a PCIe root port of the server CPU.
14. The PCIe device link training management method according to claim 1, wherein obtaining a default preset initial value Px from a sending end link equalization parameter preset value set for a kth-generation PCIe protocol, as a kth-generation initial value, for performing link training on the PCIe device specifically includes:
and acquiring the default preset initial value Px from the preset value set of the link equalization parameters of the transmitting end as a kth generation initial value, and performing link training on a CPU root port corresponding to the link where the PCIe device is located.
15. The PCIe device link training management method according to claim 14, wherein after performing link training on the PCIe device through the kth-generation initial value, determining whether a vendor ID and a device ID of the PCIe device can be read normally includes:
and obtaining and judging whether the supplier ID and the equipment ID of the PCIe device can be read normally through the basic input and output system firmware, and judging whether the PCIe link training of a PCIe bus and the CPU root port is successful.
16. The PCIe device link training management method according to claim 15, wherein before obtaining a default preset initial value Px from a sending-end link equalization parameter preset value set for a kth-generation PCIe protocol as a kth-generation initial value for performing link training on the PCIe device, the training management method further includes:
and setting the preset value set of the link equalization parameters of the sending end through a register, and carrying out link training on a CPU root port corresponding to the link where the PCIe device is located.
17. The utility model provides a PCIe device link training management device which characterized in that for through PCIe equalization technique to server mainboard key PCIe device link training management, training management device includes link training failure repair unit, and it includes:
the link training unit is used for acquiring a default preset initial value Px from a preset value set by a transmitting end link balance parameter aiming at a kth generation PCIe protocol, taking the default preset initial value Px as the kth generation initial value and carrying out link training on the PCIe device; the k generation initial value is an initial value of a link equalization parameter of a sending end when equalization adjustment is carried out on the k generation PCIe protocol, and k is not less than 2; the data of the preset value set of the link equalization parameters of the sending end are sequentially arranged according to the value;
the link training judging unit is used for judging whether the supplier ID and the equipment ID of the PCIe equipment can be read normally after the PCIe equipment is subjected to link training through the kth generation initial value;
a training failure determination unit, configured to determine that PCIe link training fails when the vendor ID and the device ID cannot be read normally;
a link retraining unit, configured to obtain a preset initial value Py according to a preset value rule from the preset set of link equalization parameters at the sending end, use the preset initial value Py as a new kth-generation initial value, and perform link retraining on the PCIe device;
the link retraining judgment unit is used for judging whether the supplier ID and the equipment ID of the PCIe device can be read normally according to the first waiting time after the link retraining is carried out on the PCIe device;
and the link retraining success judging unit is used for judging that the PCIe link is trained successfully when the supplier ID and the equipment ID can be read normally after the link retraining is carried out.
18. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor when executing the computer program implements the steps of the PCIe device link training management method of any one of claims 1 to 16.
19. A computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of the PCIe device link training management method of any one of claims 1 to 16.
20. A server, comprising a critical PCIe device provided on a motherboard, the PCIe device implementing link training management by the PCIe device link training management method according to any one of claims 1 to 16.
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| CN202310061710.4A Active CN115878540B (en) | 2023-01-19 | 2023-01-19 | PCIe device link training management method, management device and server |
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