CN113012043A - Method and processing system for compensating design image of workpiece - Google Patents
Method and processing system for compensating design image of workpiece Download PDFInfo
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- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformations in the plane of the image
- G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- G06F2115/00—Details relating to the type of the circuit
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Abstract
The present disclosure provides a compensation method and a processing system for a design image of a workpiece, the compensation method includes obtaining an actual image of the workpiece having a plurality of alignment points. The slope of each pair of sites is calculated. And determining the number of interpolation points between each adjacent pair of the points according to the slope of each pair of the points. The positions of a plurality of control points in a plurality of blocks defined by the registration points are obtained, each block is formed by and includes a plurality of control points in a plurality of registration points enclosed by the registration points on the actual image, and the number of control points in each block is related to the number of points of interpolation points between the registration points enclosing the block. A design image of the workpiece is compensated based on the positions of the pair of points, the interpolation points, and the control points to generate and output a mapping image for mapping on the workpiece.
Description
Technical Field
The disclosure relates to a compensation method and a processing system for a design image of a workpiece.
Background
In various industries, it is often necessary to map a designed image onto a workpiece, however, in actual manufacturing processes, the workpiece body often undergoes shrinkage and expansion due to various factors. In the case of the variation of the expansion and contraction of the workpiece, if the original design image is not compensated correspondingly, the image is directly mapped on the workpiece, and finally, the quality of the product is affected.
Taking the Printed Circuit Board (PCB) industry as an example, the current market demand is moving towards thinner and smaller, and the circuit layout of the PCB is becoming denser and the line widths are becoming smaller. The PCB substrate may expand due to moisture absorption and contract due to moisture removal during the manufacturing process, resulting in dimensional variation or distortion. At this time, in order to cope with the warpage of the PCB substrate, the original circuit pattern needs to be properly compensated to image the proper circuit pattern output on the PCB substrate.
BRIEF SUMMARY OF THE PRESENT DISCLOSURE
The present disclosure provides a compensation method and a processing system for a design image of a workpiece, which can quickly and accurately perform expansion and contraction compensation on the design image, and take manufacturing efficiency and yield of the product into consideration.
According to an embodiment of the present disclosure, a method for compensating a design image of a workpiece is disclosed, including obtaining an actual image of the workpiece, wherein the actual image has a plurality of alignment points; calculating the slope of each pair of sites; determining the number of interpolation points between each adjacent pair of the points according to the slope of each pair of the points; obtaining the positions of a plurality of control points in a plurality of blocks defined by the registration points, wherein each block of the blocks is formed by a plurality of registration points in the registration points, the actual image is surrounded by the plurality of registration points, each block comprises a plurality of control points in the control points, and the number of the control points in each block is related to the number of interpolation points between the registration points surrounding the block; compensating a design image of the workpiece according to the positions of the pair of points, the positions of the interpolation points and the positions of the control points to generate a mapping image; and outputting the mapped image, wherein the mapped image is used for mapping on the workpiece.
According to an embodiment of the present disclosure, a system for processing a design image of a workpiece is disclosed, which includes a processor, a memory, and a computing component. The processor is used for dividing a design image of the workpiece into a plurality of sub-images. The memory is coupled to the processor and is used for storing the sub-images. The computing component is coupled with the processor and compensates the sub-images according to the positions of the alignment points, the positions of the interpolation points and the positions of the control points and stores the compensated sub-images. The processor rearranges the compensated sub-images to generate a mapping image, and the processor is configured to obtain an actual image of a workpiece, wherein the actual image has the alignment points; calculating the slope of each pair of sites; determining the number of interpolation points between each adjacent pair of the interpolation points according to the slope of each pair of the interpolation points; and obtaining the positions of the control points in a plurality of blocks defined by the contraposition points, wherein each block of the blocks is formed by a plurality of contraposition points in the contraposition points, the contraposition points surround the actual image, each block comprises a plurality of control points in the control points, and the point number of the control point in each block is related to the point number of an interpolation point between the contraposition points surrounding the block.
In summary, in the compensation method and processing system for a design image of a workpiece according to the present disclosure, the geometric continuity of the curved surface of the workpiece is mainly utilized, the slope of the alignment point of the workpiece is matched by a polynomial curve equation to obtain the number of interpolation points, and further the control point is obtained according to the number of interpolation points, wherein the control point is the position where the workpiece is significantly expanded and contracted, so that the expansion and contraction compensation is performed on the design image according to the control point, and the precision of the workpiece can be maintained without increasing the burden of excessive production efficiency.
The foregoing description of the disclosure and the following detailed description are presented to illustrate and explain the spirit and principles of the disclosure and to provide further explanation of the scope of the disclosure as claimed.
Drawings
FIG. 1 is a functional block diagram of a system for processing a design image of a workpiece according to one embodiment of the present disclosure.
Fig. 2 is a flowchart illustrating a method of compensating a design image of a workpiece according to an embodiment of the disclosure.
Fig. 3 is a schematic diagram illustrating an actual image of a workpiece according to an embodiment of the disclosure.
Fig. 4A and 4B are detailed process flow diagrams of a compensation method for a design image of a workpiece according to the embodiment of fig. 2 of the present disclosure.
FIG. 5 is a schematic diagram illustrating interpolation points of an actual image of a workpiece in a horizontal direction according to one embodiment of the present disclosure.
FIG. 6 is a schematic diagram illustrating interpolation points of an actual image of a workpiece in a vertical direction according to one embodiment of the present disclosure.
FIG. 7 is a diagram illustrating control points for a block in an actual image of a workpiece according to an embodiment of the disclosure.
Fig. 8 is a flowchart illustrating a method of compensating a design image of a workpiece according to another embodiment of the present disclosure.
FIG. 9 is a schematic diagram of a design image of a workpiece according to an embodiment of the disclosure.
Fig. 10 is a partially enlarged view of a block of an actual image according to an embodiment of the disclosure.
Description of the reference numerals
1 processing system
10 first processor
12 first memory
14 arithmetic element
140 second processor
141 second memory
AP 1-AP 15 counterpoint points
E1-E8 Block
Interpolation points of PH1, PH2, PV1 and PV2
PC control point
F1-F8 subimages
BP 1-BP 15 original positioning point
SE 1-SE 4 sub-blocks
Detailed Description
The detailed features and advantages of the present disclosure are described in detail in the following detailed description, which is sufficient for any person skilled in the art to understand the technical content of the present disclosure and to implement the same, and the objects and advantages related to the present disclosure can be easily understood by any person skilled in the art from the disclosure, claims and drawings of the present specification. The following examples further illustrate the aspects of the present disclosure in detail, but are not intended to limit the scope of the disclosure in any way.
Referring to fig. 1, fig. 2 and fig. 3 together, fig. 1 is a functional block diagram of a processing system for a design image of a workpiece according to an embodiment of the present disclosure, fig. 2 is a flowchart of a method for compensating the design image of the workpiece according to an embodiment of the present disclosure, wherein the method can be performed by the processing system (hereinafter referred to as "processing system") for the design image of the workpiece of fig. 1, and fig. 3 is a schematic diagram of an actual image of the workpiece according to an embodiment of the present disclosure. As shown in fig. 1, the processing system 1 includes a first processor 10, a first memory 12 and a computing element 14, and the first memory 12 and the computing element 14 are coupled to the first processor 10. In this embodiment, the term "coupled" may mean "directly connected" or "indirectly connected". In the embodiment of the present disclosure, the Processing system 1 may be implemented by a computer system, a server system or other system having operation and Processing functions, wherein the first processor 10 may be a Central Processing Unit (CPU), the first memory 12 may be a main memory of a server or a computer system, and the operation component 14 includes a second processor 140 and a second memory 141, where the second processor 140 may be, for example, a Graphics Processing Unit (GPU), and the second memory 141 may be, for example, a memory of the GPU, but the disclosure is not limited thereto. In another embodiment, the first processor 10 may also be a graphics processor, and the second processor 140 may also be a central processing unit.
For convenience of describing the compensation method of the design image of the workpiece according to the present disclosure, the workpiece is exemplified by a Printed Circuit Board (PCB) substrate, however, the workpiece according to the present disclosure is not limited to the PCB substrate. First, in step S1, the first processor 10 obtains an actual image of the workpiece shown in fig. 3, wherein the actual image has a plurality of alignment points AP 1-AP 15. The actual image may be an image of a warped workpiece (PCB substrate) taken from an experimental or simulation bench, wherein the alignment points AP 1-AP 15 may be target holes of the workpiece (PCB substrate). In the present embodiment, the docking points are vertices of a plurality of rectangular blocks surrounded by the docking points when the workpiece is not warped, but the shapes of the rectangular blocks surrounded by the docking points may also be triangles, polygons, and the like. As shown in FIG. 3, the loci AP 1-AP 15 divide the actual image into a plurality of expansion-contraction warped patches E1-E8.
In step S2, the first processor 10 calculates the slope of each pair point. In one embodiment, the first processor 10 first obtains the coordinate positions of the respective pairs of positions AP 1-AP 15, and calculates a plurality of polynomial equations in the horizontal direction and the vertical direction according to the coordinate positions of the respective pairs of positions AP 1-AP 15, for example, the polynomial equation y in the horizontal direction is anxn+an-1xn-1+...+a2x2+a1x1+a0And a polynomial equation x in the vertical direction bnyn+bn-1yn-1+...+b2y2+b1y1+b0. The first processor 10 can calculate the slope of each pair point in the horizontal direction and the vertical direction by the polynomial equation in each of the horizontal direction and the vertical direction.
For example, the first processor 10 may calculate a polynomial equation of the horizontal direction according to the coordinate positions of the positions AP 1-AP 5, and perform a first differentiation on the polynomial equation, and substitute the polynomial equation into the coordinate positions of each of the positions AP 1-AP 5 to obtain the slope of each of the positions AP 1-AP 5 of the horizontal direction. The calculation modes of the slopes of the remaining alignment points AP 6-AP 10 and AP 11-AP 15 in the horizontal direction are similar and are not described again.
On the other hand, the first processor 10 may also calculate a polynomial equation of the vertical direction according to the coordinate positions of the positions AP1, AP6, and AP11, and perform a first differentiation on the polynomial equation, and substitute the polynomial equation into the coordinate positions of the positions AP1, AP6, and AP11 to obtain the slope of each of the positions AP1, AP6, and AP11 in the vertical direction. The slope calculation methods of the remaining alignment points AP2, AP7, AP12 and AP3, AP8, AP13 and AP4, AP9, AP14 and AP5, AP10 and AP15 in the vertical direction are similar and will not be described again.
After obtaining the slope of each pair point in the horizontal and vertical directions, in step S3, the first processor 10 determines the number of interpolation points between two adjacent pair points in the pair points according to the slope of each pair point. In step S4, the first processor 10 obtains the positions of control points in blocks defined by the alignment points. Each of the plurality of blocks is bounded in the actual image by a plurality of the docking points, e.g., block E1 is bounded by docking points AP1, AP2, AP6, and AP7, block E2 is bounded by docking points AP2, AP3, AP7, and AP8, and so on. Each block contains a plurality of control points (not shown in fig. 1) among the control points, and the number of control points in each block is related to the number of interpolation points between the pair of alignment points surrounding the block. The details of the interpolation and control point acquisition are described in detail in the subsequent paragraphs herein.
After the first processor 10 obtains the positions of the control points, in step S5, the second processor 140 of the computing unit 14 compensates the design image of the workpiece according to the positions of the pair of points, the positions of the interpolation points and the positions of the control points obtained by the first processor 10, thereby generating a mapping image. In an embodiment, the expansion/contraction positions of the PCB substrate image at the points can be represented by the coordinate positions of the pair of points, the coordinate positions of the interpolation points, and the coordinate positions of the control points, the second processor 140 of the computing unit 14 reads the design image from the first memory 12, performs position adjustment compensation on each corresponding point of the design image according to the coordinate positions of the pair of points, the coordinate positions of the interpolation points, and the coordinate positions of the control points, and stores the compensated design image in the second memory 141, so that the first processor 10 can generate the mapping image accordingly. In an embodiment, the second processor 140 of the computing element 14 may start hardware acceleration by methods such as an Open Graphics Library (OpenGL), a DirectX (DX), and the like to compensate the design image, so as to increase the instruction cycle, but the disclosure is not limited thereto. In step S6, the first processor 10 outputs a mapping image for mapping onto the workpiece. More specifically, the design image may be an original circuit pattern for mapping onto a workpiece (PCB substrate), and the mapping image is a compensation image generated through a compensation process based on the design image. That is, the mapping image is an image obtained after appropriate expansion/contraction compensation in response to the actual state of expansion/contraction warpage of the workpiece. By the compensation method, even if the circuit line width of the design image of the PCB is very dense, good precision can be achieved without consuming a large amount of time and cost. In one embodiment, the workpiece is fabricated based on the mapped image, for example, the mapped image is printed, etched and/or exposed for development to form a printed circuit board or a mask master thereof.
Fig. 4A-4B are detailed process flow diagrams of a method for compensating a design image of a workpiece according to the embodiment of fig. 2 of the present disclosure. In FIG. 4A, step S3 includes steps S31-S33. In step S31, the first processor 10 calculates the slope difference between each adjacent pair of loci in the pair of loci according to the slope of each pair of loci. In step S32, the first processor 10 obtains a non-zero minimum slope difference from the slope differences. In step S33, the first processor 10 determines the number of interpolation points between each two adjacent pairs of points according to the non-zero minimum slope difference.
In one embodiment, the first processor 10 calculates the slopes of the alignment points AP1, AP2, AP3, AP4 and AP5 as y0’、y1’、y2’、y3’、y4’。The first processor 10 further calculates the slope difference between each two adjacent pair points, for example, the slope difference between the pair points AP1 and AP2 is y0′-y1' |, the difference between the slopes of the alignment points AP2 and AP3 is | y1′-y2' |, the difference between the slopes of the alignment points AP3 and AP4 is | y2′-y3' |, the difference between the slopes of the alignment points AP4 and AP5 is | y3′-y4′|。
After obtaining the slope difference between each two adjacent pairs of points, the first processor 10 selects a non-zero minimum slope difference among the slope differences. Assume that the above-mentioned non-zero minimum slope difference is y2′-y3' |, the first processor 10 determines the number of interpolation points between each two adjacent pairs of points based on the non-zero minimum slope difference.
In one embodiment, the first processor 10 determines the number of interpolation points between each two adjacent pairs of points according to the non-zero minimum slope difference includes dividing the slope difference of each two adjacent pairs of points by the non-zero minimum slope difference to determine the number of interpolation points between each two adjacent pairs of points. In one embodiment, the first processor 10 divides the slope difference between each two adjacent pairs of points by the non-zero minimum slope difference and takes the integer of the slope difference upward to determine the number of interpolation points between the two adjacent pairs of points. For the above embodiment, if the non-zero minimum slope difference is y2′-y3' |, the first processor 10 may calculate the number of points to obtain the interpolation point between the pair of points AP1 and AP2 asNumber of points for interpolation between points AP2 and AP3Number of points for interpolation between points AP3 and AP4Number of points for interpolation between points AP4 and AP5The calculation of the remaining pairs of positions is similar to the above example and will not be described herein. The point calculation method of the interpolation points of two adjacent pairs of points in the vertical direction can also be performed with reference to the above example, and will not be described herein again.
After obtaining the number of interpolation points of each two adjacent pairs of points, the first processor 10 can further obtain the position of the control point in each block of the real image according to the number of interpolation points. More specifically, as shown in FIG. 4B, step S4 includes steps S41 through S43. In step S41, the first processor 10 obtains the number of points of the largest interpolation point in the horizontal direction and the vertical direction of the block defined by each of the adjacent four registration points. In detail, each block has two groups of points of interpolation points in the horizontal and vertical directions, for example, the block E4 has the number of points of interpolation points between the alignment points AP4 and AP5 and the number of points of interpolation points between the alignment points AP9 and AP10 in the horizontal direction, and has the number of points of interpolation points between the alignment points AP4 and AP9 and the number of points of interpolation points between the alignment points AP5 and AP10 in the vertical direction. The first processor 10 compares the number of points of two sets of interpolation points in the horizontal direction of each block itself with respect to each block unit, and compares the number of points of two sets of interpolation points in the vertical direction of each block itself, and obtains the point value of the maximum interpolation point, respectively.
The block E4 will be used to describe how to obtain the maximum interpolation point. Referring further to fig. 5 and 6, fig. 5 is a schematic diagram illustrating interpolation points of an actual image of a workpiece in a horizontal direction according to an embodiment of the disclosure, and fig. 6 is a schematic diagram illustrating interpolation points of an actual image of a workpiece in a vertical direction according to an embodiment of the disclosure. Assuming that the number of interpolation points calculated by the first processor 10 between the alignment points AP4 and AP5 is 4 and the number of interpolation points calculated by the first processor 10 between the alignment points AP9 and AP10 is 8, the first processor 10 selects the number of maximum interpolation points (i.e., 8 interpolation points) as the number of interpolation points of the block E4 in the horizontal direction, as shown in fig. 5. In other words, the number of points for the interpolation point between the alignment points AP4 and AP5 and the number of points for the interpolation point between the alignment points AP9 and AP10 of the block E4 are both 8. Based on the degree of simplification, only the interpolation points PH1 and PH2 are respectively marked in the horizontal direction of the block E4, and the rest of the interpolation points are not marked.
On the other hand, in fig. 6, assuming that the first processor 10 calculates that the number of interpolation points between the alignment points AP4 and AP9 is 3 and the number of interpolation points between the alignment points AP5 and AP10 is 4, the first processor 10 takes the number of points at which the maximum interpolation point is selected (i.e., 4 interpolation points) as the number of interpolation points of the block E4 in the vertical direction, as shown in fig. 6. That is, the number of points for the interpolation point between the alignment points AP4 and AP9 and the number of points for the interpolation point between the alignment points AP5 and AP10 of the block E4 are both 4. Similarly, only the interpolation points PV1 and PV2 are individually labeled in the vertical direction of the block E4 based on the degree of simplification of the drawing, and the rest of the interpolation points are not labeled separately.
The block E4 is used as an example, and other blocks can obtain the points of the respective horizontal and vertical interpolation points in the same way. After the first processor 10 determines the interpolation points in the horizontal and vertical directions of each block, in step S42, the first processor 10 obtains the positions of the interpolation points corresponding to the blocks defined by the adjacent four pairs of points according to the maximum number of interpolation points in the horizontal and vertical directions. In more detail, since the interpolation points in the horizontal and vertical directions of each block are evenly distributed between the two corresponding pairs of points according to the curve of the polynomial equation, the first processor 10 can obtain the coordinate positions of the interpolation points by comparing the coordinate positions of the points with the curve of the polynomial equation. For example, the eight interpolation points PH1 between the alignment points AP4 and AP5 in fig. 5 are equally divided according to the curve of the polynomial equation thereof, so that the first processor 10 can calculate the coordinate positions of the eight interpolation points PH1 by the coordinate positions of the alignment points AP4 and AP 5. On the other hand, the four interpolation points PV1 between the alignment points AP5 and AP10 in fig. 6 are equally divided according to the curve of the polynomial equation, so that the first processor 10 can calculate the coordinate positions of the four interpolation points PH1 by the coordinate positions of the alignment points AP5 and AP 10.
As mentioned above, after the first processor 10 has obtained the coordinate positions of the interpolation points in the horizontal and vertical directions of the block E4, then in step S43, the first processor 10 calculates the positions of the control points in the block defined by each adjacent four of the pair points according to the positions of the interpolation points. Further, referring to fig. 7, fig. 7 is a schematic diagram illustrating control points of a block in an actual image of a workpiece according to an embodiment of the disclosure. In this embodiment, the first processor 10 calculates a plurality of horizontal polynomial equations and a plurality of vertical polynomial equations corresponding to the blocks defined by the adjacent four pairs of points respectively according to the positions of the interpolation points.
Similarly, referring to the block E4, after obtaining the coordinate positions of the interpolation points in the horizontal direction of the block E4, the first processor 10 may obtain a plurality of vertical polynomial equations by calculation based on the coordinate positions of the interpolation points. On the other hand, after obtaining the coordinate positions of the interpolation points in the vertical direction of the block E4, the first processor 10 may obtain a plurality of horizontal polynomial equations by calculation according to the coordinate positions of the interpolation points.
Then, the first processor 10 obtains a plurality of intersections of the horizontal polynomial equation and the vertical polynomial equation by calculation, as shown in fig. 7. The positions of the intersection points are the coordinate positions of a plurality of control points (e.g., control points PC) in this block E4, where fig. 7 only indicates a single control point PC based on the simplification of the drawing, and the rest of the control points are not indicated. The above practical example is mainly described in the block E4, and the first processor 10 can obtain the coordinate positions of the control points in the remaining blocks E1-E3 and E5-E8 according to the same manner, which is not described herein again.
Referring to fig. 8 and 9 together, fig. 8 is a flowchart illustrating a method of compensating a design image of a workpiece according to another embodiment of the present disclosure, and fig. 9 is a schematic diagram illustrating the design image of the workpiece according to another embodiment of the present disclosure. Steps S1 'to S4' and steps S6 'and S7' shown in fig. 8 are the same as or similar to steps S1 to S4 and steps S5 and S6 of fig. 2, 4A and 4B, respectively. The compensation method of fig. 8 further includes step S5 ', and step S6' includes sub-steps S61 'and S62'.
In step S5', the first processor 10 divides the design image of the workpiece into a plurality of sub-images F1-F8 according to the original positioning points. Specifically, the first processor 10 may divide the design image into the sub-images F1 to F8 according to the original anchor points BP1 to BP15 using multithreading. In the present embodiment, the original positioning points are default positions of the positioning holes of the standard workpiece depicted on the design image (original circuit diagram). The first processor 10 can store the sub-images F1-F8 in the first memory 12 in a continuous storage manner, wherein the sub-images F1-F8 correspond to the blocks E1-E8 of the actual image respectively. In the embodiment of FIG. 8, step S5 'is performed after step S4'. However, in other embodiments, step S5 'may be performed before step S1' or between any two of steps S1 'to S4'.
Compensating the design image of the workpiece according to the positions of the control points to generate a mapping image in step S6 ' includes sub-steps S61 ' and S62 '. In sub-step S61', the second processor 140 compensates a corresponding one of the sub-images according to the position of each of the four neighboring registration points, the position of the interpolation point between the two neighboring registration points of each of the four neighboring registration points, and the positions of the control points in the block defined by each of the four neighboring registration points. Specifically, the second processor 140 reads the sub-images F1 to F8 from the first memory 12 sequentially, and compensates the sub-images F1 to F8 according to the control points of the blocks E1 to E8 acquired by the first processor 10, for example, the second processor 140 compensates the sub-image F4 according to the control point collocation of the block E4 in fig. 7 with the interpolation point. In more detail, since the block E4 has a total number of pairs, interpolation points and control points of 60, the block E4 may be subdivided into 45 sub-blocks in total, so that the second processor 140 further divides the sub-image F4 into 45 small images correspondingly. The second processor 140 adjusts the positions of the four points surrounding the corresponding small image in the sub-image F4 according to the positions of the four points surrounding each sub-tile in the tile E4, thereby achieving the effect of image compensation.
To describe the image compensation in detail, please further refer to fig. 10, in which fig. 10 is a partially enlarged view of a block of an actual image according to an embodiment of the disclosure. In detail, fig. 10 is a partial enlarged view of the block E4, which includes four of the 45 sub-blocks SE 1-SE 4. In this embodiment, the second processor 140 adjusts the positions of the four points of the corresponding small image in the sub-image F4 according to the four points surrounding the sub-block SE1, i.e., the pair of points AP5, the interpolation points PH1, PV1 and the control point PC.
On the other hand, the second processor 140 adjusts the positions of four points of the corresponding small image in the sub-image F4 according to four points, i.e. two interpolation points PV1 and two control points PC, surrounding the sub-block SE 2. The second processor 140 adjusts the positions of the four points of the corresponding small image in the sub-image F4 according to the four points, i.e., the two interpolation points PH1 and the two control points PC, surrounding the sub-block SE 3. The second processor 140 adjusts the positions of the four points of the corresponding small image in the sub-image F4 according to the four points, i.e., the four control points PC, surrounding the sub-image SE 4. The position adjustment of the other corresponding small images in the sub-image F4 can be performed in the manner described above, and is not described herein again.
In one embodiment, the second processor 140 may utilize hardware acceleration (e.g., OpenGL and/or DirectX) to perform the compensation of the sub-images F1-F8. The second processor 140 further stores the compensated sub-images F1-F8 in the second memory 141 in a consecutive storage manner. Next, the first processor 10 retrieves the compensated sub-images from the second memory 141, and in sub-step S62', the first processor 10 rearranges the compensated sub-images to be the mapping image.
In summary, in the compensation method and processing system for a design image of a workpiece according to an embodiment of the present disclosure, interpolation points and control points of each block are obtained by using geometric continuity of a curved surface of the workpiece and matching a slope of a corresponding point of the workpiece with a polynomial curve equation, and the sub-images of the design image are individually compensated for expansion and contraction according to the interpolation points and the control points of the blocks. By using the compensation method provided by the embodiment of the disclosure, compensation can be performed for the position of the workpiece where the workpiece has obvious expansion and contraction warpage, so that not only can high precision of the workpiece be maintained, but also production time can be saved and efficiency can be improved, thereby achieving the purpose of considering both production efficiency and precision of the workpiece.
Claims (11)
1. A method of compensating a design image of a workpiece, comprising:
obtaining an actual image of a workpiece, wherein the actual image has a plurality of alignment points;
calculating the slope of each pair of sites;
determining the number of interpolation points between each adjacent pair of the points according to the slope of each pair of the points;
obtaining the positions of a plurality of control points in a plurality of blocks defined by the registration points, wherein each block of the blocks is formed by a plurality of registration points in the registration points, the actual image is surrounded by the plurality of registration points, each block comprises a plurality of control points in the control points, and the number of the control points in each block is related to the number of interpolation points between the registration points surrounding the block;
compensating the design image of the workpiece according to the positions of the pair of points, the positions of the interpolation points and the positions of the control points to generate a mapping image; and
outputting the mapping image, wherein the mapping image is used for mapping on the workpiece.
2. The compensation method of claim 1, wherein determining a number of interpolation points between each adjacent pair of the pair of points according to the slope of each of the pair of points comprises:
calculating the slope difference of each adjacent pair of the loci according to the slope of each pair of the loci;
obtaining a non-zero minimum slope difference from the slope differences; and
and determining the number of interpolation points between each two adjacent pairs of points according to the nonzero minimum slope difference.
3. The compensation method of claim 2, wherein determining the number of interpolation points between each adjacent pair of points according to the non-zero minimum slope difference comprises:
the slope difference of each adjacent pair of loci is divided by the non-zero minimum slope difference to determine the number of interpolation points between each adjacent pair of loci.
4. The compensation method of claim 1, wherein obtaining the locations of the control points in the blocks defined by the pair of points comprises:
obtaining the number of the maximum interpolation points of the blocks defined by the adjacent four opposite points in the horizontal direction and the vertical direction;
obtaining the positions of the interpolation points corresponding to the blocks defined by the four adjacent pairs of points according to the point number of the maximum interpolation point in the horizontal direction and the vertical direction; and
and calculating the positions of the control points in the blocks defined by four adjacent pairs of the points according to the positions of the interpolation points.
5. The compensation method of claim 4, wherein calculating the positions of the control points in the block defined by four adjacent pairs of the pairs of points according to the positions of the interpolation points comprises:
respectively calculating a plurality of horizontal polynomial equations and a plurality of vertical polynomial equations corresponding to blocks defined by four adjacent opposite points according to the positions of the interpolation points; and
and taking a plurality of intersection points of the horizontal polynomial equations and the vertical polynomial equations, wherein the positions of the intersection points are the positions of the control points.
6. The compensation method of claim 1, further comprising:
dividing the design image of the workpiece into a plurality of subimages according to a plurality of original positioning points;
wherein compensating the design image of the workpiece based on the locations of the pair of points, the locations of the interpolation points, and the locations of the control points to generate the map image comprises:
compensating a corresponding sub-image in the sub-images according to the positions of the four adjacent paired points, the position of an interpolation point between the four adjacent paired points and the positions of the control points in the block defined by the four adjacent paired points; and
the compensated sub-images are rearranged to be the mapping image.
7. A system for processing a design image of a workpiece, comprising:
a processor for segmenting a design image of a workpiece into a plurality of subimages;
the memory is coupled with the processor and used for storing the sub-images; and
the computing component is coupled with the processor and compensates the sub-images according to the positions of the alignment points, the positions of the interpolation points and the positions of the control points, and stores the compensated sub-images;
wherein the processor rearranges the compensated sub-images to generate a mapped image; and the processor is configured to:
obtaining an actual image of the workpiece, wherein the actual image has the alignment points;
calculating the slope of each pair of sites;
determining the number of interpolation points between each adjacent pair of the interpolation points according to the slope of each pair of the interpolation points; and
and obtaining the positions of the control points in a plurality of blocks defined by the contraposition points, wherein each block of the blocks is formed by a plurality of contraposition points in the contraposition points, the contraposition points surround the actual image, each block comprises a plurality of control points in the control points, and the point number of the control point in each block is related to the point number of an interpolation point between the contraposition points surrounding the block.
8. The processing system of claim 7, wherein the processor calculates slope differences for adjacent pairs of the pairs of positions according to the slope of each pair of positions, and determines the number of interpolation points between the adjacent pairs of positions by obtaining a non-zero minimum slope difference from the slope differences.
9. The processing system of claim 8, wherein the processor divides the slope difference of each adjacent pair of loci by the non-zero minimum slope difference to determine the number of interpolation points between each adjacent pair of loci.
10. The processing system of claim 7, wherein the processor obtains the maximum interpolation point number in the horizontal direction and the vertical direction for each block formed by four adjacent pairs of points, and obtains the positions of the interpolation points for each block formed by four adjacent pairs of points according to the maximum interpolation point number in the horizontal direction and the vertical direction, the processor further calculates the positions of the control points in the blocks defined by four adjacent pairs of points in the pairs of points according to the positions of the interpolation points.
11. The processing system of claim 10, wherein the processor calculates a plurality of horizontal polynomial equations and a plurality of vertical polynomial equations corresponding to blocks formed by four adjacent pairs of points respectively according to the positions of the interpolation points, and takes intersections of the horizontal polynomial equations and the vertical polynomial equations, wherein the positions of the intersections are the positions of the control points.
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5495535A (en) * | 1992-01-31 | 1996-02-27 | Orbotech Ltd | Method of inspecting articles |
WO1999041703A1 (en) * | 1998-02-17 | 1999-08-19 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for interpolated pixel generation |
US6268920B1 (en) * | 1999-03-11 | 2001-07-31 | Olec Corporation | Registration of sheet materials using statistical targets and method |
CN1662051A (en) * | 2004-02-27 | 2005-08-31 | 联发科技股份有限公司 | Method for controlling interpolation direction and related device |
KR101510690B1 (en) * | 2014-03-31 | 2015-04-10 | 정태보 | Driving Circuit For Automatic Adjustment Of Grey Level Voltage Using Transfer Function And Display Device Including The Same |
EA201500468A1 (en) * | 2015-04-09 | 2016-10-31 | Белорусский Государственный Университет (Бгу) | METHOD OF DISTANCE MEASUREMENT ON DIGITAL CAMERA |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0341944A3 (en) * | 1988-05-10 | 1991-06-26 | Gec Plessey Telecommunications Limited | Improvements in or relating to methods of and apparatus for registration |
US6205364B1 (en) * | 1999-02-02 | 2001-03-20 | Creo Ltd. | Method and apparatus for registration control during processing of a workpiece particularly during producing images on substrates in preparing printed circuit boards |
US7379626B2 (en) | 2004-08-20 | 2008-05-27 | Silicon Optix Inc. | Edge adaptive image expansion and enhancement system and method |
JP2006260527A (en) * | 2005-02-16 | 2006-09-28 | Toshiba Corp | Image matching method and image interpolation method using same |
US7439083B2 (en) | 2005-04-14 | 2008-10-21 | Delphi Technologies, Inc. | Technique for compensating for substrate shrinkage during manufacture of an electronic assembly |
CN101489353B (en) | 2008-01-16 | 2011-11-16 | 富葵精密组件(深圳)有限公司 | Design method for board dimension |
TW200948248A (en) | 2008-05-01 | 2009-11-16 | Prostek Internat Inc | Method of drilling holes in a printed circuit board for a drilling machine |
KR101651810B1 (en) * | 2008-05-22 | 2016-08-30 | 마이크로닉 마이데이타 에이비 | Method and apparatus for overlay compensation between subsequently patterned layers on workpiece |
TWI381732B (en) * | 2008-10-08 | 2013-01-01 | Silicon Integrated Sys Corp | Apparatus and method for low angle interpolation |
IL194967A0 (en) * | 2008-10-28 | 2009-08-03 | Orbotech Ltd | Producing electrical circuit patterns using multi-population transformation |
CN101668389B (en) | 2009-09-04 | 2012-05-09 | 东莞美维电路有限公司 | Method for making high alignment printed circuit board |
CN102036511B (en) | 2010-12-01 | 2012-12-12 | 株洲南车时代电气股份有限公司 | Method for classifying and compensating nonlinear variation of core boards for manufacturing multilayer circuit boards |
CN103008711A (en) | 2012-12-21 | 2013-04-03 | 东莞生益电子有限公司 | Drilled hole aligning method of circuit board |
CN103747617B (en) | 2013-12-24 | 2017-02-15 | 广州兴森快捷电路科技有限公司 | PCB expansion compensation method |
RU2705014C1 (en) * | 2015-12-31 | 2019-11-01 | Шанхай Юнайтид Имиджинг Хелскеа Ко., Лтд. | Methods and systems for image processing |
CN105636345A (en) | 2016-03-18 | 2016-06-01 | 奥士康科技股份有限公司 | Multilayer PCB core material expansion and shrinkage matching method |
KR101720004B1 (en) | 2016-06-16 | 2017-03-27 | 주식회사 디이엔티 | Machining position correction apparatus and method thereof |
CN108305231B (en) | 2018-02-09 | 2021-08-27 | 西安电子科技大学 | Lens distortion correction method in maskless photoetching technology |
-
2019
- 2019-12-20 TW TW108146915A patent/TWI724705B/en active
-
2020
- 2020-02-07 CN CN202010082112.1A patent/CN113012043B/en active Active
- 2020-04-20 US US16/853,607 patent/US11341628B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5495535A (en) * | 1992-01-31 | 1996-02-27 | Orbotech Ltd | Method of inspecting articles |
WO1999041703A1 (en) * | 1998-02-17 | 1999-08-19 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for interpolated pixel generation |
US6268920B1 (en) * | 1999-03-11 | 2001-07-31 | Olec Corporation | Registration of sheet materials using statistical targets and method |
CN1662051A (en) * | 2004-02-27 | 2005-08-31 | 联发科技股份有限公司 | Method for controlling interpolation direction and related device |
KR101510690B1 (en) * | 2014-03-31 | 2015-04-10 | 정태보 | Driving Circuit For Automatic Adjustment Of Grey Level Voltage Using Transfer Function And Display Device Including The Same |
EA201500468A1 (en) * | 2015-04-09 | 2016-10-31 | Белорусский Государственный Университет (Бгу) | METHOD OF DISTANCE MEASUREMENT ON DIGITAL CAMERA |
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