CN112993072A - PERC double-sided battery and manufacturing method thereof - Google Patents

PERC double-sided battery and manufacturing method thereof Download PDF

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Publication number
CN112993072A
CN112993072A CN201911293686.7A CN201911293686A CN112993072A CN 112993072 A CN112993072 A CN 112993072A CN 201911293686 A CN201911293686 A CN 201911293686A CN 112993072 A CN112993072 A CN 112993072A
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silicon wafer
conductive paste
grids
perc
battery
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李兵
刘运宇
邓伟伟
蒋方丹
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Canadian Solar Inc
CSI Cells Co Ltd
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CSI Cells Co Ltd
Atlas Sunshine Power Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • H01L31/0516—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module specially adapted for interconnection of back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0684—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells double emitter cells, e.g. bifacial solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract

The invention discloses a PERC double-sided battery and a manufacturing method thereof, and the PERC comprises a silicon wafer, a passivation layer formed on the back of the silicon wafer, a back electric field and a back electrode, wherein the back electric field is arranged on the back of the silicon wafer and comprises a plurality of first auxiliary grids which are arranged on the back of the silicon wafer at intervals in parallel, and the first auxiliary grids are arranged discontinuously and penetrate through the passivation layer along the thickness direction of the double-sided PERC battery to form electric connection with the back of the silicon wafer; the back electrode comprises a plurality of second auxiliary grids which are arranged on the back of the passivation layer and are in one-to-one correspondence with the first auxiliary grids, and main grids which are vertically connected with the second auxiliary grids, the resistivity of the second auxiliary grids is smaller than that of the first auxiliary grids, and the second auxiliary grids are connected with the back of the corresponding first auxiliary grids so as to be connected with a plurality of parts of the corresponding first auxiliary grids at intervals in series; the PERC double-sided battery provided by the invention can effectively reduce minority carrier recombination on the back of the battery, has smaller series resistance in the application scene of a specific photovoltaic module, and can reliably improve the photoelectric conversion efficiency of the corresponding photovoltaic module.

Description

PERC double-sided battery and manufacturing method thereof
Technical Field
The invention relates to the technical field of solar photovoltaics, in particular to a PERC double-sided battery and a manufacturing method thereof.
Background
A bifacial perc cell is a photovoltaic device that can receive light on both its front and back sides to produce an electric current. The double-sided assembly made of the double-sided perc battery can generate electricity on the back, so that the total generated energy can be greatly increased compared with a single-sided battery assembly. Collecting current through an aluminum wire on the back of the double-sided perc battery, and transmitting the collected current to a back electrode; however, in the prior art, since the aluminum wire has a higher resistivity, the aluminum wire generally needs to be provided with a larger width in order to avoid affecting the series resistance of the battery cell. This great aluminium line width has reduced the effective photic area of battery piece back to a great extent, and then influences battery efficiency and the two-sided rate of two-sided subassembly.
In view of the above, it is necessary to provide a technical solution to solve the above technical problems.
Disclosure of Invention
The invention aims to solve at least one technical problem in the prior art, and in order to achieve the aim, the invention provides a double-sided perc battery which is specifically designed as follows.
A PERC double-sided battery comprises a silicon wafer and a passivation layer formed on the back of the silicon wafer, and further comprises a back electric field and a back electrode which are arranged on the back of the silicon wafer, wherein the back electric field comprises a plurality of first auxiliary grids which are arranged on the back of the silicon wafer at intervals in parallel, the first auxiliary grids are arranged discontinuously and penetrate through the passivation layer along the thickness direction of the double-sided PERC battery to form electrical connection with the back of the silicon wafer; the back electrode comprises a plurality of second auxiliary grids which are arranged on the back of the passivation layer and are in one-to-one correspondence with the first auxiliary grids and main grids which are vertically connected with the second auxiliary grids, the resistivity of the second auxiliary grids is smaller than that of the first auxiliary grids, and the second auxiliary grids are connected with the back of the corresponding first auxiliary grids so as to be connected with the corresponding parts of the first auxiliary grids at intervals in series.
Further, the maximum width of the first sub-gate in the direction perpendicular to the length direction of the first sub-gate is larger than the width of the second sub-gate.
Further, the maximum width of the first sub-gate in the direction perpendicular to the length direction of the first sub-gate ranges from 40 μm to 200 μm, and the width of the second sub-gate ranges from 20 μm to 100 μm.
Furthermore, the back electrode also comprises a plurality of bonding pads which are arranged at intervals along the length direction of the main grid and connected to the main grid.
Furthermore, a blank area is reserved in the area where the pad is located by the back electric field.
Furthermore, a plurality of parts which are arranged discontinuously on the two adjacent first auxiliary grids are distributed in a staggered manner in the length direction of the first auxiliary grids.
Furthermore, the first auxiliary grid is composed of a plurality of dot parts arranged at intervals, and the diameter range of the dot parts is 40-200 μm.
Further, the distance between centers of two adjacent dot parts of each first auxiliary grid ranges from 20 μm to 2000 μm.
Furthermore, a plurality of dot parts on each first auxiliary grid are distributed at equal intervals, and a dot part on one of two adjacent first auxiliary grids and a central point connecting line of two adjacent dot parts on the other first auxiliary grid form an equilateral triangle.
Furthermore, the first sub-grid is composed of a plurality of long strip parts which are arranged at intervals and the length direction of which is consistent with the length direction of the first sub-grid, the length range of the long strip parts is 40-10000 μm, the width range of the long strip parts is 40-200 μm, and the distance range between two adjacent long strip parts on the same first sub-grid is 20-10000 μm.
Furthermore, a groove which penetrates through the passivation layer and is used for arranging the first auxiliary grid is formed in the back surface of the silicon chip.
The invention also provides a manufacturing method of the PERC double-sided battery, which is used for manufacturing the PERC double-sided battery and comprises the following steps:
providing a silicon wafer with a passivation layer on the back surface;
printing first conductive slurry on the back of the silicon wafer;
printing second conductive paste on the back of the silicon wafer printed with the first conductive paste;
and sintering the silicon wafer with the back printed with the first conductive paste and the second conductive paste, wherein the first conductive paste printed on the back of the silicon wafer is sintered to form the back electric field, and the second conductive paste printed on the back of the silicon wafer is sintered to form the back electrode.
Further, the first conductive paste is non-fire through conductive paste, and the manufacturing method further comprises the step of forming a groove which penetrates through the passivation layer and is matched with the position of the first auxiliary grid on the back surface of the silicon wafer before the first conductive paste is printed.
Further, the first conductive paste is a fire-through conductive paste, and the passivation layer is fully distributed on the back surface of the silicon wafer.
Further, the second conductive paste is non-burn-through conductive paste.
The invention has the beneficial effects that: the back of the PERC double-sided battery provided by the invention is electrically connected with the back of the silicon wafer by adopting the intermittent first auxiliary grid, so that minority carrier recombination on the back of the battery can be effectively reduced; and then, the resistivity of the second auxiliary grid is smaller than that of the first auxiliary grid, so that the PERC double-sided battery has smaller series resistance in the application scene of a specific photovoltaic module, and the photoelectric conversion efficiency of the corresponding photovoltaic module can be reliably improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of the back electric field of a dual sided perc cell according to the present invention;
FIG. 2 is an enlarged view of a portion a of FIG. 1;
FIG. 3 is a schematic view of a double-sided perc cell according to the present invention with a back electrode formed on the back side;
FIG. 4 is an enlarged view of portion b of FIG. 3;
FIG. 5 is a schematic cross-sectional view taken at the position A-A' in FIG. 4;
FIG. 6 is another enlarged view of portion a of FIG. 1;
FIG. 7 is another enlarged view of portion b of FIG. 3;
FIG. 8 is a schematic cross-sectional view taken at the position B-B' in FIG. 7;
FIG. 9 is a schematic cross-sectional view taken at the position C-C' in FIG. 7;
fig. 10 is a schematic diagram of another arrangement of the back electric field of a double-sided perc cell of the present invention.
In the figure, 11 is a silicon wafer, 110 is a passivation layer, 12 is a first sub-grid, 120 is a blank area, 121 is a dot portion, 1211 is a first dot portion, 1212 is a second dot portion, 1213 is a third dot portion, 13 is a back electrode, 130 is a bonding pad, 131 is a second sub-grid, and 132 is a main grid.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, 2, 3, 4 and 5, the double-sided perc cell provided by the present invention includes a silicon wafer 11 and a passivation layer 110 formed on the back surface of the silicon wafer 11, and further includes a back electric field and a back electrode 13 disposed on the back surface of the silicon wafer.
Referring to fig. 1, the back electric field includes a plurality of first sub-gates 12 disposed in parallel at intervals on the back surface of the silicon wafer 11, and further referring to fig. 4, 5, 7, and 8, the first sub-gates 12 are disposed intermittently and penetrate through the passivation layer 110 along the thickness direction of the double-sided perc cell to form an electrical connection with the back surface of the silicon wafer 11.
As shown in fig. 4, 5, 7, and 8, the back electrode 13 includes a plurality of second sub-gates 131 disposed on the back of the passivation layer 110 and corresponding to the first sub-gates 12 one by one, and a main gate 132 vertically connected to the second sub-gates 131, wherein the resistivity of the second sub-gates 131 is smaller than that of the first sub-gates 12, and the second sub-gates 131 are connected to the back of the corresponding first sub-gates 12 to connect in series a plurality of spaced portions of the corresponding first sub-gates 12.
In some embodiments, the back electric field is specifically set to an aluminum back field, and the back electrode 13 may be specifically set to one of a silver electrode, a silver aluminum electrode, a copper electrode, and a silver copper electrode.
The invention also provides a photovoltaic module with the double-sided perc cell.
In the specific implementation process, the back surface of the PERC double-sided battery provided by the invention is electrically connected with the back surface of the silicon wafer 11 by adopting the intermittent first auxiliary grid 12, so that minority carrier recombination on the back surface of the battery can be effectively reduced. In addition, because the resistivity of the second auxiliary grid 131 is smaller than that of the first auxiliary grid 12, in a specific application scenario where the first auxiliary grid 12 is an aluminum grid and the second auxiliary grid 131 is a silver grid, a mode that the first auxiliary grid 12 and the second auxiliary grid 131 are matched to collect current on the back of the double-sided perc battery has a smaller series resistance than a traditional mode that the aluminum wire current collection is adopted on the back of the double-sided perc battery, and therefore the photoelectric conversion efficiency of the corresponding photovoltaic module can be reliably improved.
As a preferred embodiment of the present invention, in a specific implementation process, the maximum width of the first sub-gate 12 in a direction perpendicular to the length direction thereof is greater than the width of the second sub-gate 131. Referring to fig. 4 and 7, the second sub-grid 131 has a narrower width relative to the first sub-grid 12, which reduces the shading area on the back of the cell compared to the prior art, and thus the corresponding photovoltaic module has a higher double-sided ratio.
Referring to fig. 3, the back electrode 13 according to the present invention further includes a plurality of pads 130 spaced apart along the length of the main grid 132 and connected to the main grid 132.
The double-sided perc cell of the present invention may also be a half cell, and as shown in fig. 3, the entire double-sided perc cell of this embodiment may be split along the middle split line O-O' into two half double-sided perc cells in which the area of the land 130 near the end region of the main grid 132 is greater than the area of the land 130 away from the end region of the main grid 132. Therefore, in the welding and assembling process of the photovoltaic module, the probability of welding deviation caused by position deviation between the welding strip and the main grid 132 can be effectively reduced.
As a preferred embodiment of the present invention, as shown in fig. 3 and 10, the back electric field according to the present embodiment has a blank region 121 left in the region where the pad 130 is located. That is, the first sub-grid 12 does not extend to the region where the bonding pad 130 is located, so that the bonding pad 130 formed in the region is more flat, and the bonding strength between the bonding strip and the bonding pad 130 in the photovoltaic module can be further improved.
In some preferred embodiments of the present invention, as shown in fig. 2 and fig. 6, a plurality of intermittently disposed portions of two adjacent first sub-grids 12 are disposed in a staggered manner in the length direction of the first sub-grids 12.
More specifically, referring to fig. 2, 4 and 5, in this embodiment, the first sub-grid 12 is composed of a plurality of dot portions 121 arranged at intervals, wherein the diameter r of the dot portions 121 is in the range of 40 μm to 200 μm. At this time, the maximum width of the first sub-grid 12 in the direction perpendicular to the longitudinal direction thereof coincides with the diameter r of the dot portion 121.
Further, in the present embodiment, the center-to-center distance between two adjacent dots 121 of each first sub-grid 12 ranges from 20 μm to 2000 μm. Referring to fig. 2, two adjacent dot portions 121 on one first sub-grid 12 include a first dot portion 1211 and a second dot portion 1212, wherein a center-to-center distance between the first dot portion 1211 and the second dot portion 1212 is 20 μm-2000 μm.
As a preferred implementation structure of this embodiment, the dot parts 121 on each first sub-grid 12 are distributed at equal intervals, and a connecting line of center points of one dot part 121 on one of two adjacent first sub-grids 12 and two adjacent dot parts 121 on the other one forms an equilateral triangle. Specifically, as shown in fig. 2, one of the two adjacent first sub-grids 12 has a first dot portion 1211 and a second dot portion 1212 that are adjacent to each other, and the other has a third dot portion 1213, and a connection line of center points of the first dot portion 1211, the second dot portion 1212, and the third dot portion 1213 forms an equilateral triangle. Based on this, when the PERC double-sided battery operates, the current on the back surface of the silicon wafer 11 has a better transmission path.
In another embodiment of the present invention, referring to fig. 6, 7, 8 and 9, the first sub-grid 12 is composed of a plurality of long bars 122 arranged at intervals and having a length direction consistent with the length direction of the first sub-grid 12, the length L of the long bars 122 ranges from 40 μm to 10000 μm, the width d ranges from 40 μm to 200 μm, and the distance L' between two adjacent long bars 122 on the same first sub-grid 12 ranges from 20 μm to 10000 μm. At this time, the maximum width of the first subgrid 12 in the direction perpendicular to the longitudinal direction thereof coincides with the width d of the long portion 122.
In the above embodiments, the maximum width of the first sub-gate 12 perpendicular to the length direction thereof is in the range of 40 μm to 200 μm, and accordingly, the width D of the second sub-gate 131 in the present invention is in the range of 20 μm to 100 μm, and preferably, the width D of the second sub-gate 131 is in the range of 30 μm to 50 μm.
It is understood that in the implementation of the present invention, the first sub-gate 12 penetrates the passivation layer 110 along the thickness direction of the double-sided perc cell to form an electrical connection with the back side of the silicon wafer 11 can be implemented by the following two embodiments.
In one embodiment, the conductive paste for back-field printing is a non-fire through paste, and referring to fig. 5, a groove (not shown) is formed on the back surface of the silicon wafer 11 to penetrate the passivation layer 110 to form the first sub-gate 12. Typically, the non-fire through paste is printed to completely fill the groove and have a portion extending beyond the edge of the groove.
In another embodiment, the passivation layer 110 is spread over the entire back surface of the silicon wafer 11, and the conductive paste for back electric field printing is a fire-through paste, so that during the subsequent sintering process of the double-sided perc cell, the fire-through paste reacts with the passivation layer 110 to penetrate through the passivation layer 110 to form the first sub-gate 12 electrically connected to the back surface of the silicon wafer 11.
In order to better understand the invention, the invention also provides a manufacturing method of the PERC double-sided battery, which is used for manufacturing the PERC double-sided battery and comprises the following steps: providing a silicon wafer 11 with a passivation layer arranged on the back surface; printing first conductive paste on the back of the silicon wafer 11; printing second conductive paste on the back of the silicon wafer 11 printed with the first conductive paste; and sintering the silicon wafer with the back printed with the first conductive paste and the second conductive paste, wherein the first conductive paste printed on the back of the silicon wafer 11 is sintered to form a back electric field, and the second conductive paste printed on the back of the silicon wafer 11 is sintered to form a back electrode 13.
In a more specific embodiment, the specific manufacturing steps of the PERC double-sided battery include:
texturing: and (3) alkaline texturing is carried out on the P-type silicon wafer with the resistivity of 0.5-3.0 omega-cm to form a textured surface with the pyramid size of 1-3 mu m.
Diffusion: under the condition that the diffusion temperature is 750-950 ℃, a POCl3 gas source is adopted to carry out diffusion doping on the silicon wafer to form a front emitter, and the sheet resistance range of a diffusion doping region is 110-160 omega/sq.
Heavy doping: and forming a local heavily doped region on the front surface of the silicon wafer through laser, wherein the sheet resistance range of the heavily doped region is 50-90 omega/sq.
Etching: the back side reamed region and edge junctions were removed using a HF/HNO3 mixture.
Front passivation: growing 2-6 nm silicon oxide on the front surface by a thermal oxidation mode.
Back passivation: depositing a back passivation layer by using an ALD (atomic layer deposition) mode, wherein the deposition temperature is 180-280 ℃, the passivation layer is Al2O3, and the thickness of aluminum oxide is 5-20 nm;
forming an antireflection film: and depositing an anti-reflection film on the front surface and the back surface of the silicon wafer by PECVD, wherein the anti-reflection film can be a silicon nitride laminated film, the thickness of the anti-reflection film on the front surface and the back surface is 60-90 nm, and the deposition temperature is 300-550 ℃.
Laser grooving: and forming a plurality of grooves penetrating through the back passivation layer on the back of the silicon wafer by using laser, wherein the positions of the grooves are matched with the positions of the first auxiliary grid 12 as shown in fig. 4 and 5, and in the embodiment shown in fig. 4 and 5, the diameter of the grooves formed by using the laser is 30-40 μm.
Back electric field printing: printing first conductive paste on the back surface of the silicon wafer according to the pattern of the back electric field by using a first screen printing plate, wherein in the embodiment, the first conductive paste is non-burn-through conductive paste, specifically non-burn-through aluminum paste, and drying operation is performed after the printing of the first conductive paste is completed.
Back electrode printing: printing second conductive paste on the back surface of the silicon wafer according to the pattern of the back electrode by using a second screen printing plate, wherein in the embodiment, the second conductive paste is non-burn-through conductive paste, specifically non-burn-through silver paste, and drying operation is performed after the second conductive paste is printed; it is understood that the second conductive paste may also be a conductive paste such as silver aluminum paste, copper paste or silver clad copper paste.
Positive electrode printing: and printing a third conductive paste on the front surface of the silicon wafer according to the pattern of the positive electrode by using a third screen printing plate, wherein in the embodiment, the third conductive paste is a burn-through conductive paste, specifically a burn-through silver paste, and drying operation is performed after the third conductive paste is printed.
And (3) sintering: and sintering the silicon wafer printed with the first conductive paste, the second conductive paste and the third conductive paste in an environment with a sintering peak temperature of 650-850 ℃ to form the PERC double-sided battery.
Annealing: and carrying out electrical injection annealing treatment on the sintered PERC double-sided battery.
In another embodiment of the present invention, a specific manufacturing method of the PERC double-sided battery has the following differences from the above embodiments, which does not include the "laser grooving step" after the "forming the antireflection film" step, and specifically, which modifies the "back electric field printing step" after removing the "laser grooving step" to:
back electric field printing: printing first conductive paste on the back surface of the silicon wafer according to the pattern of the back electric field by using a first screen printing plate, wherein in the embodiment, the first conductive paste is burn-through conductive paste, specifically, burn-through aluminum paste, and drying operation is performed after the printing of the first conductive paste is completed. Referring to fig. 8 and 9, since the first conductive paste is a fire-through conductive paste, in the subsequent sintering step, the first conductive paste reacts with the passivation layer 110 to penetrate the passivation layer 110 to form the first sub-gate 12 electrically connected to the back surface of the silicon wafer 11.
In addition, it can be understood that, in the specific manufacturing process of the double-sided perc battery according to the present invention, the back electric field and the back electrode 13 are printed with the corresponding conductive paste by using different printing screens, and in order to avoid the position deviation between the first sub-grid 12 of the back electric field and the second sub-grid 131 of the back electrode 13, the first printing screen and the second printing screen are both provided with positioning patterns, which are not further developed herein.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.

Claims (15)

1. A PERC double-sided battery comprises a silicon wafer and a passivation layer formed on the back of the silicon wafer, and is characterized in that the PERC double-sided battery further comprises a back electric field and a back electrode which are arranged on the back of the silicon wafer, the back electric field comprises a plurality of first auxiliary grids which are arranged on the back of the silicon wafer at intervals in parallel, and the first auxiliary grids are arranged discontinuously and penetrate through the passivation layer along the thickness direction of the double-sided PERC battery to form electrical connection with the back of the silicon wafer; the back electrode comprises a plurality of second auxiliary grids which are arranged on the back of the passivation layer and are in one-to-one correspondence with the first auxiliary grids and main grids which are vertically connected with the second auxiliary grids, the resistivity of the second auxiliary grids is smaller than that of the first auxiliary grids, and the second auxiliary grids are connected with the back of the corresponding first auxiliary grids so as to be connected with the corresponding parts of the first auxiliary grids at intervals in series.
2. The PERC bifacial battery of claim 1, wherein a maximum width of said first secondary grid perpendicular to its length direction is greater than a width of said second secondary grid.
3. The PERC double sided battery of claim 2, wherein said first sub-grid has a maximum width perpendicular to its length in the range of 40 μm to 200 μm, and said second sub-grid has a width in the range of 20 μm to 100 μm.
4. The PERC bifacial battery of claim 1, wherein said back electrode further comprises a plurality of bonding pads spaced along the length of said primary grid and connected to said primary grid.
5. The PERC double-sided battery of claim 4, wherein the back electric field is provided with a blank area in the area where the bonding pad is located.
6. The PERC double sided battery of any of claims 1-5, wherein a plurality of intermittently disposed portions of adjacent first secondary grids are offset in a longitudinal direction of the first secondary grids.
7. The PERC double sided battery of any of claims 1 to 5, wherein said first secondary grid is comprised of a plurality of spaced dots, said dots having a diameter in the range of 40 μm to 200 μm.
8. The PERC double sided battery of claim 7, wherein a center-to-center distance between two adjacent dot portions of each first secondary grid is in a range of 20 μm to 2000 μm.
9. The PERC double-sided battery of claim 6, wherein said dots on each of said first sub-grids are equally spaced, and a line connecting center points of one dot on one of two adjacent first sub-grids and two adjacent dots on the other dot forms an equilateral triangle.
10. The PERC double sided battery according to any one of claims 1 to 5, wherein said first subgrid is formed of a plurality of elongated portions spaced apart and having a length direction coinciding with a length direction of said first subgrid, said elongated portions having a length in a range of 40 μm to 10000 μm and a width in a range of 40 μm to 200 μm, and a distance between two adjacent elongated portions on the same first subgrid is in a range of 20 μm to 10000 μm.
11. The PERC double sided battery of any of claims 1-5, wherein the back side of the silicon wafer is recessed through the passivation layer for the placement of the first sub-gate.
12. A method for manufacturing a PERC double-sided battery, for manufacturing the PERC double-sided battery of any one of claims 1 to 10, comprising the steps of:
providing a silicon wafer with a passivation layer on the back surface;
printing first conductive slurry on the back of the silicon wafer;
printing second conductive paste on the back of the silicon wafer printed with the first conductive paste;
and sintering the silicon wafer with the back printed with the first conductive paste and the second conductive paste, wherein the first conductive paste printed on the back of the silicon wafer is sintered to form the back electric field, and the second conductive paste printed on the back of the silicon wafer is sintered to form the back electrode.
13. The method of claim 12, wherein the first conductive paste is a non-fire through conductive paste, and the method further comprises forming a groove in the back surface of the silicon wafer, the groove penetrating the passivation layer and matching the position of the first sub-gate, before printing the first conductive paste.
14. The method of claim 12, wherein the first conductive paste is a fire-through conductive paste, and the passivation layer is applied over the back surface of the silicon wafer.
15. The method of any one of claims 12-14, wherein the second conductive paste is a non-fire-through conductive paste.
CN201911293686.7A 2019-12-12 2019-12-12 PERC double-sided battery and manufacturing method thereof Withdrawn CN112993072A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113793877A (en) * 2021-09-29 2021-12-14 上饶捷泰新能源科技有限公司 Photovoltaic cell and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113793877A (en) * 2021-09-29 2021-12-14 上饶捷泰新能源科技有限公司 Photovoltaic cell and manufacturing method thereof

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Application publication date: 20210618