CN112992964A - Light emitting diode structure and manufacturing method thereof - Google Patents

Light emitting diode structure and manufacturing method thereof Download PDF

Info

Publication number
CN112992964A
CN112992964A CN202110317555.9A CN202110317555A CN112992964A CN 112992964 A CN112992964 A CN 112992964A CN 202110317555 A CN202110317555 A CN 202110317555A CN 112992964 A CN112992964 A CN 112992964A
Authority
CN
China
Prior art keywords
semiconductor layer
layer
led
doped semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110317555.9A
Other languages
Chinese (zh)
Other versions
CN112992964B (en
Inventor
庄永漳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Laiyu Optoelectronic Technology Suzhou Co ltd
Original Assignee
Laiyu Optoelectronic Technology Suzhou Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/162,515 external-priority patent/US20210320145A1/en
Application filed by Laiyu Optoelectronic Technology Suzhou Co ltd filed Critical Laiyu Optoelectronic Technology Suzhou Co ltd
Publication of CN112992964A publication Critical patent/CN112992964A/en
Application granted granted Critical
Publication of CN112992964B publication Critical patent/CN112992964B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

The application discloses a light emitting diode structure and a manufacturing method thereof. The light emitting diode structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes: a bonding layer formed on the substrate; a first doping type semiconductor layer formed on the bonding layer; a second doped semiconductor layer formed on the first doped semiconductor layer; a passivation layer formed on the second doping type semiconductor layer and on a portion of the first doping type semiconductor layer; and an electrode layer formed on a portion of the passivation layer and in contact with the second doping type semiconductor layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first doping type semiconductor layer of the first LED unit horizontally extends to the first doping type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are separately operable LED units.

Description

Light emitting diode structure and manufacturing method thereof
Cross Reference to Related Applications
THE present application claims priority from U.S. provisional patent application No. 63/007,829 entitled "Semiconductor Array AND Method of Monolithic Integration," filed on 9/4/2020, AND priority from U.S. official patent application No. 17/162,515 entitled "light emitting DIODE STRUCTURE AND Method of MANUFACTURING SAME" (LIGHT EMITTING DIODE STRUCTURE AND Method FOR MANUFACTURING SAME), filed on 29/1/29/2021, THE disclosure of which is hereby incorporated by reference in its entirety.
Technical Field
The present invention relates to a Light Emitting Diode (LED) structure and a method of manufacturing the same, and more particularly, to an LED structure having a plurality of LED units that can be individually operated while sharing a doped layer, and a method of manufacturing the same.
Background
In recent years, LEDs have become popular in lighting applications. As a light source, LEDs have many advantages, including higher light efficiency, lower power consumption, longer lifetime, smaller size, and faster switching speed.
Micro LED displays have an array of micro LEDs (micro-LEDs) with a plurality of single pixel elements. The pixels may be tiny illuminated areas on the display screen and the image may be composed of many pixels. In other words, a pixel may be a small discrete element that together make up an image on a display. Pixels are typically arranged in a two-dimensional (2D) matrix and are represented using dots, squares, rectangles, or other shapes. A pixel may be a basic unit of a display or a digital image and has geometrical coordinates.
When fabricating micro-LEDs, a process such as dry etching or wet etching is often used to electrically isolate the individual micro-LEDs. To create a plurality of fully isolated functional micro LED pixels, conventional processes typically completely etch away the continuous functional epitaxial layers. However, when transferring conventional micro LED pixels onto a substrate (such as a driving circuit substrate) or after transfer, the fully isolated functional micro LED pixels may be easily peeled off from the substrate due to weak adhesion of the micro LED pixels. This problem becomes more severe as the micro LED pixels become smaller. Furthermore, during conventional etching processes to isolate the micro LED pixels, the sidewalls of the micro LED pixels may be damaged and affect the optical and electrical properties of the LED structure.
Embodiments of the present application address the above-mentioned problems by providing an LED structure having a plurality of LED units that can be individually operated while sharing a doping layer or a bonding layer, and a method of manufacturing the same.
Disclosure of Invention
Embodiments of an LED structure and method of forming the same are disclosed.
In one embodiment, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes: a bonding layer formed on the substrate; a first doping type semiconductor layer formed on the bonding layer; a second doped semiconductor layer formed on the first doped semiconductor layer; a passivation layer formed on the second doping type semiconductor layer and on a portion of the first doping type semiconductor layer; and an electrode layer formed on a portion of the passivation layer and in contact with the second doping type semiconductor layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first doped semiconductor layer of the first LED unit extends horizontally and is physically connected to the first doped semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are separately operable LED units.
In another embodiment, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes: a p-n diode layer formed on the substrate; a passivation layer formed on the p-n diode layer; and an electrode layer formed on the passivation layer and in contact with the p-n diode layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first and second LED units have a common anode, and the first and second LED units are individually operable LED units.
In a further embodiment, a method for fabricating an LED structure is disclosed, comprising:
forming a semiconductor layer on a first substrate, the semiconductor layer including a first doped semiconductor layer and a second doped semiconductor layer;
performing a first etching operation to remove a portion of the second doped semiconductor layer and expose a portion of the first doped semiconductor layer;
performing a second etching operation to remove a portion of the first doped semiconductor layer and expose a portion of the first substrate having the pixel circuit contacts;
forming a passivation layer on the second doped semiconductor layer and the exposed first doped semiconductor layer;
performing a third etching operation to form a first opening on the passivation layer on the second doped semiconductor layer and a second opening on the passivation layer on the first substrate having the pixel circuit contact;
and forming an electrode layer on the passivation layer covering the first opening and contacting the second doped semiconductor layer and covering the second opening and contacting the second doped semiconductor layer.
Drawings
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present application and, together with the description, further serve to explain the application and to enable a person skilled in the pertinent art to make and use the application.
Fig. 1 shows a top view of an illustrative LED structure according to some embodiments of the present application.
Fig. 2 shows a cross-sectional view of an illustrative LED structure according to some embodiments of the present application.
Fig. 3 shows another cross-sectional view of an illustrative LED structure according to some embodiments of the present application.
Fig. 4 shows another top view of an illustrative LED structure according to some embodiments of the present application.
Fig. 5 shows a top view of another illustrative LED structure according to some embodiments of the present application.
Fig. 6A-6H show cross-sectional views of illustrative LED structures at different stages of a fabrication process, according to some embodiments of the present application.
Fig. 7 is a flow chart of an illustrative method for fabricating an LED structure according to some embodiments of the present application.
Embodiments of the present application will be described below with reference to the drawings.
Detailed Description
While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of the present application. Moreover, the present application may also be employed in a variety of other applications. The functional and structural features described in this application can be combined, adapted and modified in various ways with each other and not specifically shown in the drawings, so that these combinations, adaptations and modifications are within the scope of the present application.
In general, terms may be understood based at least in part on contextual usage. For example, the term "one or more" as used herein may be used to describe any element, structure, or feature in the singular or may be used to describe a combination of elements, structures or features in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "… -based" may be understood as not necessarily intended to convey an exclusive set of factors, but may instead allow for the presence of additional factors that are not necessarily explicitly described, depending at least in part on the context.
It should be readily understood that the meaning of "on …", "above …" and "above …" in this application should be interpreted in the broadest sense such that "on …" means not only "directly on something", but also "on something" including the presence of an intermediate component or layer therebetween, and "on something" or "above something" means not only "on something" or "above something", but also the meaning of "on something" or "above something" without an intermediate component or layer therebetween.
Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90. or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.
The term "layer" as used herein refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a lesser extent than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure or therebetween. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may be of the same or different materials.
The term "substrate" as used herein refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.
The term "micro" LED, "micro" p-n diode, or "micro" device as used herein refers to descriptive dimensions of certain devices or structures according to embodiments of the present application. The term "micro" device or structure as used herein is intended to mean a scale of 0.1 to 100 μm. However, it should be understood that embodiments of the present application are not necessarily limited thereto, and that certain aspects of the embodiments may be applicable to larger and possibly smaller size scales.
Embodiments of the present application describe LED structures or micro LED structures and a method for manufacturing the same. To fabricate a micro LED display, the epitaxial layers are bonded to a receiving substrate. The receiving substrate may be, for example, but not limited to, a display substrate including a CMOS backplane or a TFT glass substrate. The epitaxial layer then forms a micro LED array on the receiving substrate. When the micro LED is formed on the receiving substrate, since the adhesion of the fine functional pixels on the receiving substrate is weak and is proportional to the pixel size, a plurality of fine functional pixels may be peeled off from the receiving substrate, thereby causing a display failure (a failed pixel) during the manufacturing process. To solve the above problem, the present application introduces a solution in which the functional epitaxial layer is partially patterned/etched and allows the remaining of a thin continuous functional layer and bonding layer to avoid potential functional pixel lift-off. In addition, the manufacturing method described in the present application can further reduce the sidewall physical damage of the functional pixel, reduce the damage of the quantum well structure as the light emitting region of the LED, and improve the optical and electrical properties of the functional pixel.
Fig. 1 shows a top view of an illustrative LED structure 100 according to some embodiments of the present application, and fig. 2 shows a cross-sectional view of the illustrative LED structure 100 along line a-a' according to some embodiments of the present application. To better explain the present application, a top view of the LED structure 100 in fig. 1 and a cross-sectional view of the LED structure 100 in fig. 2 will be described together. The LED structure 100 includes a first substrate 102 and a plurality of LED units 116 (e.g., LED units 116-1, 116-2, 116-3, and 116-4 as shown in fig. 2). The LED unit 116 is bonded on the first substrate 102 through the bonding layer 104. In some embodiments, the first substrate 102 may include a semiconductor material, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide. In some embodiments, the first substrate 102 may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. In some embodiments, the first substrate 102 may have a driving circuit formed therein, and the first substrate 102 may be a CMOS backplane or a TFT glass substrate. The driving circuit supplies an electric signal to the LED unit 116 to control the brightness. In some embodiments, the driver circuit may comprise an active matrix driver circuit, wherein each individual LED unit 116 corresponds to a separate driver. In some embodiments, the driving circuit may include a passive matrix driving circuit in which a plurality of LED units 116 are arranged in an array and connected to data lines and scan lines driven by the driving circuit.
The bonding layer 104 is an adhesive material layer formed on the first substrate 102 to bond the first substrate 102 and the LED unit 116. In some embodiments, bonding layer 104 may include a conductive material, such as a metal or metal alloy. In some embodiments, bonding layer 104 may include Au, Sn, In, Cu, or Ti. In some embodiments, bonding layer 104 may include a non-conductive material, such as Polyimide (PI), Polydimethylsiloxane (PDMS). In some embodiments, bonding layer 104 may include a photoresist, such as SU-8 photoresist. In some embodiments, bonding layer 104 may be Hydrogen Silsesquioxane (HSQ) or divinylsiloxane-bis-benzocyclobutene (DVS-BCB). It is to be understood that the description of the material of bonding layer 104 is exemplary only, and not limiting, and that variations may be made as desired by those skilled in the art, all of which are within the scope of the present application.
Referring to fig. 2, each LED unit 116 includes a portion of the bonding layer 104, the first doped semiconductor layer 106, and the second doped semiconductor layer 108. A first doped semiconductor layer 106 is formed on the bonding layer 104. In some embodiments, the first doped semiconductor layer 106 and the second doped semiconductor layer 108 may include one or more layers based on II-VI materials (such as ZnSe or ZnO) or III-V nitride materials (such as GaN, AlN, InN, InGaN, GaP, AlInGaP, AlGaAs, and alloys thereof).
In some embodiments, the first doped semiconductor layer 106 may be a p-type semiconductor layer extending across a plurality of LED units 116 (e.g., four LED units 116 as shown in fig. 2) and forming a common anode of the LED units 116. For example, the first doped semiconductor layer 106 of the LED unit 116-2 extends to its neighboring LED units 116-1 and 116-3, and similarly, the first doped semiconductor layer 106 of the LED unit 116-3 extends to its neighboring LED units 116-2 and 116-4. In some embodiments, the first doped semiconductor layer 106 extending across the LED cells may be relatively thin. In some embodiments, the thickness of the first doped semiconductor layer 106 may be between about 0.05 μm to about 1 μm. In some other embodiments, the thickness of the first doped semiconductor layer 106 may be between about 0.05 μm to about 0.7 μm. In some alternative embodiments, the thickness of the first doped semiconductor layer 106 may be between about 0.05 μm and about 0.5 μm. By having a continuous thin layer of the first doping type semiconductor on each LED unit, the bonding region between the substrate 102 and the plurality of LED units 116 is not limited to the region under the second doping type semiconductor layer 108, but extends to the region between each LED unit. In other words, the area of bonding layer 104 is increased by having a thin layer of continuous first doping type semiconductor 106. Therefore, the bonding strength between the substrate 102 and the plurality of LED units 116 is enhanced, and the risk of peeling of the LED structure 100 can be reduced.
In some embodiments, the first doped semiconductor layer 106 may be p-type GaN. In some embodiments, the first doped semiconductor layer 106 may be formed by doping magnesium (Mg) in GaN. In some embodiments, the first doped semiconductor layer 106 may be p-type InGaN. In some embodiments, the first doped semiconductor layer 106 may be a p-type AlInGaP. Each LED unit 116 has an anode and a cathode connected to a driving circuit, for example, formed in the substrate 102 (the driving circuit is not explicitly shown in the figure). For example, each LED unit 116 has an anode connected to a constant voltage source and has a cathode connected to the source/drain of the driving circuit. In other words, by forming a continuous first doped semiconductor 106 across the individual LED cells 116, the plurality of LED cells 116 have a common anode formed by the first doped semiconductor layer 106 and the bonding layer 104.
In some embodiments, the second doped semiconductor layer 108 may be an n-type semiconductor layer and form the cathode of each LED unit 116. In some embodiments, the second doped semiconductor layer 108 may be n-type GaN. In some embodiments, the second doped semiconductor layer 108 may be n-type InGaN. In some embodiments, the second doped semiconductor layer 108 may be n-type AlInGaP. The second doped semiconductor layers 108 of different LED units 116 are electrically isolated so that each LED unit 116 can have a cathode with a different voltage level than the other units. As a result of the disclosed embodiments, a plurality of individually operable LED units 116 are formed, with their first doped semiconductor layers 106 extending horizontally across adjacent LED units, and with their second doped semiconductor layers 108 electrically isolated between adjacent LED units.
Each LED unit 116 further includes a Multiple Quantum Well (MQW) layer 110 formed between the first doped semiconductor layer 106 and the second doped semiconductor layer 108. MQW layer 110 is the active region of LED unit 116. In some embodiments, the thickness of the first doped semiconductor layer 106 and the second doped semiconductor layer 108 may be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness of the layer including the first doped semiconductor layer 106, the MQW layer 110, and the second doped semiconductor layer 108 may be between about 0.4 μm and about 4 μm. In some alternative embodiments, the thickness of the layer including the first doped semiconductor layer 106, the MQW layer 110, and the second doped semiconductor layer 108 may be between about 0.5 μm and about 3 μm.
As shown in fig. 2, a passivation layer 112 is formed on the second doping type semiconductor layer 108 and a portion of the first doping type semiconductor layer 106. The passivation layer 112 may serve to protect and isolate the LED cells 116. In some embodiments, passivation layer 112 may include SiO2、Al2O3SiN, or other suitable material. In some embodiments, the passivation layer 112 may comprise a polyimideImine, SU-8 photoresist, or other photo-patternable polymer. The electrode layer 114 is formed on a portion of the passivation layer 112, and the electrode layer 114 is electrically connected to the second doping type semiconductor layer 108 through an opening on the passivation layer 112. In some embodiments, the electrode layer 114 may be a conductive material such as Indium Tin Oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge, or Ni.
Fig. 3 shows another cross-sectional view of an illustrative LED structure 100 along line B-B' according to some embodiments of the present application. The first substrate 102 has a driving circuit formed therein for driving the LED unit 116. A contact 118 of the driving circuit is exposed between the two LED units 116, and the contact 118 is electrically connected to the second doping type semiconductor layer 108 through the electrode layer 114. In other words, the electrical connection of the second doped semiconductor layer 108 and the contact 118 of the driving circuit is completed by the electrode layer 114. As described above, the second doped semiconductor layer 108 forms the cathode of each LED unit 116, and thus the contact 118 supplies a driving voltage to the cathode of each LED unit 116 from the driving circuit to the second doped semiconductor layer 108 through the electrode layer 114.
Fig. 4 illustrates another top view of an LED structure 100 according to some embodiments of the present application. In fig. 4, layers under the electrode layer 114 and the passivation layer 112 are shown with dotted lines for the purpose of explanation. In fig. 4, the LED structure 100 includes 16 LED units 116. Each LED cell 116 includes a p-n diode layer formed by the first and second doped semiconductor layers 106 and 108 and the multiple quantum well 110. A passivation layer 112 is formed on the p-n diode, and an electrode layer 114 is formed on the passivation layer 112.
An opening 120 is formed on the passivation layer 112 exposing the second doped semiconductor layer 108 and an opening 122 is formed on the passivation layer 112 exposing the contact 118. The electrode layer 114 is formed on a portion of the passivation layer 112 covering the opening 120 and the opening 122, and thus, the electrode layer 114 is electrically connected to the second doping type semiconductor layer 108 and the contact 118. As illustratively shown in fig. 4, the opening 120 is located at the center of each LED unit 116, and the opening 122 is located at the gap of the adjacent LED units 116. It is understood that the location and design (such as shape and size) of the openings 120, 122 and electrode layer 114 may deviate from the example shown in fig. 4 based on requirements and is not limited thereto.
In fig. 4, the LED structure 100 includes 16 LED units 116, and each LED unit 116 can be operated independently. The first doped semiconductor layer 106 is located under the second doped semiconductor layer 108 and the passivation layer 112, and the first doped semiconductor layer 106 is a common anode of the 16 LED units 116. According to the present application, when the first doping type semiconductor layers 106 of the LED units (e.g., 16 LED units 16) are electrically connected not only during the manufacturing process of forming the LED structure 100 but also after the manufacturing process, and each LED unit can be independently driven by different driving circuits, the LED units are referred to as being "independently operable".
Fig. 5 illustrates a top view of another LED structure 500 according to some embodiments of the present application. In the top view in fig. 5, the shape of the second doped semiconductor layer 108 is circular, which is different from the shape of the second doped semiconductor layer 108 in the top view of the LED structure 100 shown in fig. 4. It is to be understood that in some embodiments, the position and shape of the second doped semiconductor layer 108 in the top view may vary according to various designs or applications, and the shape of the second doped semiconductor layer 108 or the LED unit 116 in the top view is not limited thereto. In some embodiments, the location and shape of the openings 120, openings 122, electrode layer 114, or contacts 118 in the top view may also vary according to various designs and applications, and is not limited thereto.
Fig. 6A-6H show cross-sectional views of an illustrative LED structure 100 during a fabrication process, according to some embodiments of the present application, and fig. 7 is a flow chart of an illustrative method 700 for fabricating the LED structure 100, according to some embodiments of the present application. To better explain the present application, fig. 6A to 6H and the flowchart in fig. 7 will be described together. In fig. 6A, a driving circuit is formed in the first substrate 102, and the driving circuit includes a contact 118. For example, the driver circuit may comprise a CMOS device fabricated on a silicon wafer, and some wafer level packaging layers or fan-out structures are stacked on the CMOS device to form contacts 118. For another example, the driver circuit may include TFTs fabricated on a glass substrate, and some wafer level packaging layers or fan-out structures are stacked on the TFTs to form contacts 118. The semiconductor layer is formed on the second substrate 124 and includes a first doped semiconductor layer 106, a second doped semiconductor layer 108, and a MQW layer 110.
In some embodiments, the first substrate 102 or the second substrate 124 may include a semiconductor material, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide. In some embodiments, the first substrate 102 or the second substrate 124 may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. In some embodiments, the first substrate 102 may have a driving circuit formed therein, and the first substrate 102 may include a CMOS backplane or a TFT glass substrate. In some embodiments, the first doped semiconductor layer 106 and the second doped semiconductor layer 108 may include one or more layers based on II-VI materials (such as ZnSe or ZnO) or III-V nitride materials (such as GaN, AlN, InN, InGaN, GaP, AlInGaP, AlGaAs, and alloys thereof). In some embodiments, the first doped semiconductor layer 106 may include a p-type semiconductor layer, and the second doped semiconductor layer 108 may include an n-type semiconductor layer.
In fig. 6B, a bonding layer 104 is formed on the first substrate 102. In some embodiments, bonding layer 104 may include a conductive material, such as a metal or metal alloy. In some embodiments, bonding layer 104 may include Au, Sn, In, Cu, or Ti. In some embodiments, bonding layer 104 may include a non-conductive material, such as Polyimide (PI), Polydimethylsiloxane (PDMS). In some embodiments, bonding layer 104 may include a photoresist, such as SU-8 photoresist. In some embodiments, bonding layer 104 may be Hydrogen Silsesquioxane (HSQ) or divinylsiloxane-bis-benzocyclobutene (DVS-BCB). In some embodiments, the conductive layer 126 may form a common electrode covering the first doped semiconductor layer 106. In some embodiments, the conductive layer 126 may form an ohmic contact on the first doped semiconductor layer 106. In some embodiments, the conductive layer 126 and the bonding layer 104 may be collectively referred to as one layer in a later operation.
Referring to fig. 6C and operation 702 of fig. 7, the second substrate 124 and the semiconductor layers including the first doped semiconductor layer 106, the second doped semiconductor layer 108, and the MQW layer 110 are flipped and bonded to the first substrate 102 through the bonding layer 104 and the conductive layer 126. Then, the second substrate 124 may be removed from the semiconductor layer. Fig. 6C shows the bonding layer 104 between the first substrate 102 and the first doped semiconductor layer 106. However, in some embodiments, bonding layer 104 may include one or more layers to bond first substrate 102 and first doped semiconductor layer 106. For example, bonding layer 104 may include a single conductive or non-conductive layer. For another example, bonding layer 104 may include an adhesive material and a conductive or non-conductive layer. In some embodiments, bonding layer 104 and conductive layer 126 may be collectively referred to as one layer after operation 702. It is to be understood that the description of the material of bonding layer 104 is illustrative only and not limiting, and that variations may be made as desired by those skilled in the art, all of which are within the scope of the present application.
In fig. 6D, a thinning operation may be performed on the second doped semiconductor layer 108 to remove a portion of the second doped semiconductor layer 108. In some embodiments, the thinning operation may include a dry etching or wet etching operation. In some embodiments, the thinning operation may include a Chemical Mechanical Polishing (CMP) operation. In some embodiments, the thickness of the layer including the first doped semiconductor layer 106, the MQW layer 110, and the second doped semiconductor layer 108 may be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness of the layer including the first doped semiconductor layer 106, the MQW layer 110, and the second doped semiconductor layer 108 may be between about 0.4 μm and about 4 μm. In some alternative embodiments, the thickness of the layer including the first doped semiconductor layer 106, the MQW layer 110, and the second doped semiconductor layer 108 may be between about 0.5 μm and about 3 μm.
Referring to fig. 6E and operation 704 of fig. 7, a first etch operation may be performed to remove a portion of the second doped semiconductor layer 108 and expose a portion of the first doped semiconductor layer 106. A portion of the first doped semiconductor layer 106 is exposed until a predefined thickness of the first doped semiconductor layer 106 remains on the first substrate 102. In some embodiments, the remaining first doped semiconductor layer 106 extends horizontally across a plurality of LED units 116 (such as the four LED units 116 shown in fig. 6E) in the LED structure 100. In some embodiments, the predefined thickness of the first doped semiconductor layer 106 may be between about 0.05 μm to about 1 μm. In some embodiments, the predefined thickness of the first doped semiconductor layer 106 may be between about 0.05 μm to about 0.7 μm. In some alternative embodiments, the predefined thickness of the first doped semiconductor layer 106 may be between about 0.05 μm to about 0.5 μm. After operation 704, the second doping type semiconductor layer 108 and the MQW layer 110 of each LED unit 116 may be electrically separated, and the first doping type semiconductor layers 106 of adjacent LED units 116 (such as LED units 116-1, 116-2, 116-3, and 116-4) may be electrically connected.
In some embodiments, during operation 704, a first etch operation may be performed to remove a portion of second doped semiconductor layer 108 and expose a portion of MQW layer 110. A portion of the MQW layer 110 is exposed until a predefined thickness of the first doped semiconductor layer 106 and the MQW layer 110 remains on the first substrate 102. In some embodiments, the remaining first doped semiconductor layer 106 and MQW layer 110 extend horizontally across a plurality of LED units 116 (such as the four LED units 116 shown in fig. 6E) in the LED structure 100. In some embodiments, the predefined thickness of first doping type semiconductor layer 106 and MQW layer 110 may be between about 0.05 μm to about 1 μm. In some embodiments, the predefined thickness of first doping type semiconductor layer 106 and MQW layer 110 may be between about 0.05 μm to about 0.7 μm. In some alternative embodiments, the predefined thickness of first doping type semiconductor layer 106 and MQW layer 110 may be between about 0.05 μm to about 0.5 μm. After operation 704, the second doped semiconductor layer 108 of each LED unit 116 may be electrically separated, and the first doped semiconductor layer 106 and the MQW layer 110 of adjacent LED units 116 (such as LED units 116-1, 116-2, 116-3, and 116-4) may be electrically connected.
Referring to fig. 6F, a second etching operation may be performed to remove a portion of the first doped semiconductor layer 106 and expose the contact 118. The second etching operation may be a dry etching or wet etching operation. In the dry etching operation or the wet etching operation, a hard mask (e.g., photoresist) may be formed on the second doping type semiconductor layer 108 and a portion of the first doping type semiconductor layer 106 through a photolithography process. Then, the uncovered portion of the first doping type semiconductor layer 106 is removed by dry etching plasma or a wet etching solution to expose the contact 118.
Referring to fig. 6G and operation 706 of fig. 7, a passivation layer 112 is formed on the second doped semiconductor layer 108, the exposed first doped semiconductor layer 106, and the exposed contact 118. In some embodiments, passivation layer 112 may include SiO2、Al2O3SiN, or other suitable material for isolation and protection. In some embodiments, the passivation layer 112 may comprise polyimide, SU-8 photoresist, or other photo-patternable polymer. In operation 708 of fig. 7, as shown in fig. 6G, openings 120 and 122 are formed. The opening 120 exposes a portion of the second doped semiconductor layer 108 and the opening 122 exposes the contact 118. In some embodiments, operation 708 may be performed by a third etch operation to remove a portion of passivation layer 112 and form opening 120 and opening 122. In some further embodiments, where the provided passivation layer 112 is formed by a photosensitive material (e.g., polyimide, SU-8 photoresist, or other photo-patternable polymer), operation 708 may be performed by a photolithography operation to pattern the passivation layer 112 and expose the openings 120 and 122.
Referring to fig. 6H and operation 710 of fig. 7, an electrode layer 114 is formed on the passivation layer 112 covering the openings 120 and 122. Accordingly, the electrode layer 114 electrically connects the second doped semiconductor layer 108 and the contact 118, and forms an electrical path to connect the LED unit with a driving circuit in the substrate 102. The driver circuit may control the voltage and current levels of the second doped semiconductor layer 108 through the contact 118 and the electrode layer 114. In some embodiments, the electrode layer 114 may include a conductive material such as Indium Tin Oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge, or Ni, among others.
The present application provides an LED structure and a method for fabricating the same, wherein functional epitaxial layers, such as a first doped semiconductor layer 106 and a second doped semiconductor layer 108, are partially patterned/etched to allow a thin continuous functional layer (such as the first doped semiconductor layer 106) to remain free from potential lift-off. In addition, the present application provides another option to leave the MQW layer on the first doped semiconductor layer 106. In addition, the fabrication methods introduced in the present application may further reduce physical damage to the sidewalls of functional pixels (such as LED unit 116), reduce damage to the quantum well structure as the LED light emitting area, and improve the optical and electrical properties of the functional pixels.
According to one aspect of the present application, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit comprises a bonding layer formed on a substrate, a first doping type semiconductor layer formed on the bonding layer, a second doping type semiconductor layer formed on the first doping type semiconductor layer, and a passivation layer formed on the second doping type semiconductor layer and a part of the first doping type semiconductor layer; and an electrode layer formed on a portion of the passivation layer and in contact with the second doping type semiconductor layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first doping type semiconductor layer of the first LED unit horizontally extends to the first doping type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are separately operable LED units.
In some embodiments, the second doped semiconductor layer of the first LED unit is electrically isolated from the second doped semiconductor layer of the second LED unit. In some embodiments, each LED unit further includes a Multiple Quantum Well (MQW) layer formed between the first doped semiconductor layer and the second doped semiconductor layer.
In some embodiments, the first doped semiconductor layer is a p-type semiconductor layer and is a common anode of the first LED unit and the second LED unit. In some embodiments, the second doped semiconductor layer is an n-type semiconductor layer and is a cathode of the first LED unit and the second LED unit.
In some embodiments, the substrate includes a driving circuit to drive the plurality of LED units. In some embodiments, the electrode layer of each LED unit is connected to the driving circuit through an opening on the first doping type semiconductor layer.
In accordance with another aspect of the present application, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit comprises a p-n diode layer formed on a substrate, a passivation layer formed on the p-n diode layer, and an electrode layer formed on the passivation layer and in contact with the p-n diode layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first and second LED units have a common anode, and the first and second LED units are individually operable LED units.
In some embodiments, the p-n diode layer includes a p-doped layer, an n-doped layer, and a Multiple Quantum Well (MQW) layer formed between the p-doped layer and the n-doped layer. In some embodiments, the p-doped layer is a common anode of the first LED unit and the second LED unit. In some embodiments, the n-doped layers of the first and second LED units are electrically isolated.
In some embodiments, each LED cell further includes a bonding layer formed between the substrate and the p-n diode layer. In some embodiments, the substrate includes a driving circuit to drive the plurality of LED units. In some embodiments, the electrode layer of each LED unit is connected to the driver circuit through an opening in the p-n diode layer.
According to a further aspect of the present application, a method for fabricating an LED structure is disclosed. A semiconductor layer is formed on a first substrate. The semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer. A first etching operation is performed to remove a portion of the second doped semiconductor layer and expose a portion of the first doped semiconductor layer. A passivation layer is formed on the second doped semiconductor layer and the exposed first doped semiconductor layer. A first opening is formed in the passivation layer. An electrode layer is formed on the passivation layer covering the first opening and contacting the second doped semiconductor layer.
In some embodiments, performing the first etching operation further includes removing a portion of the second doped semiconductor layer and exposing a portion of the first doped semiconductor layer until a predefined thickness of the first doped semiconductor layer remains on the first substrate. The remaining first doped semiconductor layer extends horizontally across the plurality of LED cells of the LED structure.
In some embodiments, forming the semiconductor layer on the first substrate further comprises bonding the semiconductor layer to the first substrate through a bonding layer. In some embodiments, forming the semiconductor layer on the first substrate further comprises: forming a driving circuit in a first substrate; forming a semiconductor layer on a second substrate; bonding the semiconductor layer to the first substrate through the bonding layer; and removing the second substrate.
In some embodiments, forming the first opening on the passivation layer further includes forming a second opening on the passivation layer to expose a contact of the driving circuit. In some embodiments, forming an electrode layer on the passivation layer covering the first opening and contacting the second doping type semiconductor layer further includes forming an electrode layer on the passivation layer covering the first opening and the second opening to electrically connect the second doping type semiconductor layer and a contact of the driving circuit.
The foregoing description of the specific embodiments may be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.
The breadth and scope of the present application should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents.

Claims (20)

1. A light emitting diode structure, comprising:
a substrate; and
a plurality of LED units formed on the substrate, each LED unit including:
a bonding layer formed on the substrate;
a first doped semiconductor layer formed on the bonding layer;
a second doping type semiconductor layer formed on the first doping type semiconductor layer;
a passivation layer formed on the second doped semiconductor layer and on a portion of the first doped semiconductor layer; and
an electrode layer formed on a portion of the passivation layer and in contact with the second doping type semiconductor layer,
wherein the plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit, wherein the first doped semiconductor layer of the first LED unit horizontally extends to the first doped semiconductor layer of the second LED unit adjacent to the first LED unit, and the first and second LED units are separately operable LED units.
2. The LED structure of claim 1, wherein the second doped semiconductor layer of the first LED unit is electrically isolated from the second doped semiconductor layer of the second LED unit.
3. The LED structure of claim 1, wherein each LED unit further comprises a multi-quantum well layer formed between the first doped semiconductor layer and the second doped semiconductor layer.
4. The LED structure of claim 1, wherein the first doped semiconductor layer is a p-type semiconductor layer and is a common anode of the first LED unit and the second LED unit.
5. The LED structure of claim 1, wherein the second doped semiconductor layer is an n-type semiconductor layer and is a cathode of the first LED unit and the second LED unit.
6. The LED structure of claim 1, wherein said substrate comprises a driver circuit to drive said plurality of LED units.
7. The LED structure of claim 6, wherein the electrode layer of each LED unit is connected to the driver circuit through an opening in the first doped semiconductor layer.
8. A light emitting diode structure, comprising:
a substrate; and
a plurality of LED units formed on the substrate, each LED unit including:
a p-n diode layer formed on the substrate;
a passivation layer formed on the p-n diode layer; and
an electrode layer formed on the passivation layer and in contact with the p-n diode layer,
wherein the plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit, wherein the first and second LED units have a common anode, and the first and second LED units are individually operable LED units.
9. The LED structure of claim 8, wherein the p-n diode layer comprises a p-doped layer, an n-doped layer, and a multi-quantum well layer formed between the p-doped layer and the n-doped layer.
10. The LED structure of claim 9, wherein said p-doped layer is a common anode of said first LED unit and said second LED unit.
11. The LED structure of claim 9, wherein said n-doped layers of said first LED unit and said second LED unit are electrically isolated.
12. The LED structure of claim 8, wherein each LED unit further comprises:
a bonding layer formed between the substrate and the p-n diode layer.
13. The LED structure of claim 8, wherein said substrate comprises a driver circuit to drive said plurality of LED units.
14. The LED structure of claim 13, wherein said electrode layer of each LED unit is connected to said driver circuitry through an opening in said p-n diode layer.
15. A method for fabricating a light emitting diode structure, comprising:
forming a semiconductor layer on a first substrate, the semiconductor layer including a first doped semiconductor layer and a second doped semiconductor layer;
performing a first etching operation to remove a portion of the second doped semiconductor layer and expose a portion of the first doped semiconductor layer;
forming a passivation layer on the second doped semiconductor layer and the exposed first doped semiconductor layer;
forming a first opening on the passivation layer; and
and forming an electrode layer on the passivation layer covering the first opening and contacting the second doped semiconductor layer.
16. The method of claim 15, wherein performing the first etch operation further comprises:
removing a portion of the second doped semiconductor layer; and
exposing a portion of the first doped semiconductor layer until a predefined thickness of the first doped semiconductor layer remains on the first substrate,
wherein the remaining first doped semiconductor layer extends horizontally across a plurality of LED cells of the LED structure.
17. The method of claim 15, wherein forming the semiconductor layer on the first substrate further comprises:
bonding the semiconductor layer to the first substrate through a bonding layer.
18. The method of claim 17, wherein forming the semiconductor layer on the first substrate further comprises:
forming a driving circuit on the first substrate;
forming the semiconductor layer on a second substrate;
bonding the semiconductor layer to the first substrate through the bonding layer; and
and removing the second substrate.
19. The method of claim 18, wherein forming the first opening on the passivation layer further comprises:
forming a second opening on the passivation layer to expose a contact of the driving circuit.
20. The method of claim 19, wherein forming the electrode layer on the passivation layer covering the first opening and contacting the second doped semiconductor layer further comprises:
forming the electrode layer on the passivation layer covering the first and second openings to electrically connect the second doping type semiconductor layer with a contact of the driving circuit.
CN202110317555.9A 2020-04-09 2021-03-25 Light emitting diode structure and manufacturing method thereof Active CN112992964B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063007829P 2020-04-09 2020-04-09
US63/007,829 2020-04-09
US17/162,515 US20210320145A1 (en) 2020-04-09 2021-01-29 Light Emitting Diode Structure and Method for Manufacturing the Same
US17/162,515 2021-01-29

Publications (2)

Publication Number Publication Date
CN112992964A true CN112992964A (en) 2021-06-18
CN112992964B CN112992964B (en) 2023-07-07

Family

ID=76333624

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110317555.9A Active CN112992964B (en) 2020-04-09 2021-03-25 Light emitting diode structure and manufacturing method thereof

Country Status (4)

Country Link
EP (1) EP4133536A1 (en)
JP (1) JP2023525439A (en)
KR (1) KR20220139993A (en)
CN (1) CN112992964B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114023861A (en) * 2021-11-01 2022-02-08 镭昱光电科技(苏州)有限公司 Micro-LED chip structure and manufacturing method thereof
CN114497333A (en) * 2021-12-21 2022-05-13 镭昱光电科技(苏州)有限公司 Micro-LED Micro display chip and manufacturing method thereof
CN114628563A (en) * 2022-05-12 2022-06-14 镭昱光电科技(苏州)有限公司 Micro LED display chip and preparation method thereof
CN114759130A (en) * 2022-06-15 2022-07-15 镭昱光电科技(苏州)有限公司 Micro-LED display chip and preparation method thereof

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005039041A (en) * 2003-07-14 2005-02-10 Sanyo Electric Co Ltd Light emitting diode array and optical print head
US20080113462A1 (en) * 2006-11-14 2008-05-15 Samsung Electronics Co., Ltd Method of manufacturing vertical light emitting device
CN202332853U (en) * 2011-10-19 2012-07-11 贵州大学 Large-power inverse array LED (Light-Emitting Diode) chip
US20120223875A1 (en) * 2009-12-09 2012-09-06 Nano And Advanced Materials Institute Limited Monolithic full-color led micro-display on an active matrix panel manufactured using flip-chip technology
WO2014017427A1 (en) * 2012-07-27 2014-01-30 株式会社ブイ・テクノロジー Semiconductor light-emitting device
US20150076528A1 (en) * 2013-09-16 2015-03-19 LuxVue Technology Corporation Adhesive wafer bonding with sacrificial spacers for controlled thickness variation
US20170373228A1 (en) * 2015-01-30 2017-12-28 Apple Inc. Micro-light emitting diode with metal side mirror
US20180190712A1 (en) * 2016-12-30 2018-07-05 Fang Xu Semiconductor LED Display Devices
CN108598104A (en) * 2018-06-25 2018-09-28 广东省半导体产业技术研究院 A kind of micro- LED array of parallel connection and preparation method thereof
US20180308420A1 (en) * 2017-04-21 2018-10-25 Lumens Co., Ltd. Micro led display device and method of fabricating the same
US20180358340A1 (en) * 2017-06-09 2018-12-13 Syndiant Inc. Micro LED Display Module Having Light Transmissive Substrate and Manufacturing Method Thereof
CN109216397A (en) * 2017-07-05 2019-01-15 格芯公司 For the cmos driver wafer of micro-display and the component of LED wafer
CN109417082A (en) * 2016-03-18 2019-03-01 Lg伊诺特有限公司 Semiconductor devices and display device including semiconductor devices
CN109713089A (en) * 2018-12-28 2019-05-03 映瑞光电科技(上海)有限公司 GaN base LED white light thin-film LED and preparation method thereof
CN109920814A (en) * 2019-03-12 2019-06-21 京东方科技集团股份有限公司 Display base plate and manufacturing method, display device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005039041A (en) * 2003-07-14 2005-02-10 Sanyo Electric Co Ltd Light emitting diode array and optical print head
US20080113462A1 (en) * 2006-11-14 2008-05-15 Samsung Electronics Co., Ltd Method of manufacturing vertical light emitting device
US20120223875A1 (en) * 2009-12-09 2012-09-06 Nano And Advanced Materials Institute Limited Monolithic full-color led micro-display on an active matrix panel manufactured using flip-chip technology
CN202332853U (en) * 2011-10-19 2012-07-11 贵州大学 Large-power inverse array LED (Light-Emitting Diode) chip
WO2014017427A1 (en) * 2012-07-27 2014-01-30 株式会社ブイ・テクノロジー Semiconductor light-emitting device
US20150076528A1 (en) * 2013-09-16 2015-03-19 LuxVue Technology Corporation Adhesive wafer bonding with sacrificial spacers for controlled thickness variation
US20170373228A1 (en) * 2015-01-30 2017-12-28 Apple Inc. Micro-light emitting diode with metal side mirror
CN109417082A (en) * 2016-03-18 2019-03-01 Lg伊诺特有限公司 Semiconductor devices and display device including semiconductor devices
US20180190712A1 (en) * 2016-12-30 2018-07-05 Fang Xu Semiconductor LED Display Devices
US20180308420A1 (en) * 2017-04-21 2018-10-25 Lumens Co., Ltd. Micro led display device and method of fabricating the same
US20180358340A1 (en) * 2017-06-09 2018-12-13 Syndiant Inc. Micro LED Display Module Having Light Transmissive Substrate and Manufacturing Method Thereof
CN109216397A (en) * 2017-07-05 2019-01-15 格芯公司 For the cmos driver wafer of micro-display and the component of LED wafer
CN108598104A (en) * 2018-06-25 2018-09-28 广东省半导体产业技术研究院 A kind of micro- LED array of parallel connection and preparation method thereof
CN109713089A (en) * 2018-12-28 2019-05-03 映瑞光电科技(上海)有限公司 GaN base LED white light thin-film LED and preparation method thereof
CN109920814A (en) * 2019-03-12 2019-06-21 京东方科技集团股份有限公司 Display base plate and manufacturing method, display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114023861A (en) * 2021-11-01 2022-02-08 镭昱光电科技(苏州)有限公司 Micro-LED chip structure and manufacturing method thereof
WO2023071910A1 (en) * 2021-11-01 2023-05-04 镭昱光电科技(苏州)有限公司 Micro-led chip structure and manufacturing method therefor
CN114497333A (en) * 2021-12-21 2022-05-13 镭昱光电科技(苏州)有限公司 Micro-LED Micro display chip and manufacturing method thereof
CN114628563A (en) * 2022-05-12 2022-06-14 镭昱光电科技(苏州)有限公司 Micro LED display chip and preparation method thereof
CN114628563B (en) * 2022-05-12 2022-09-09 镭昱光电科技(苏州)有限公司 Micro LED display chip and preparation method thereof
CN114759130A (en) * 2022-06-15 2022-07-15 镭昱光电科技(苏州)有限公司 Micro-LED display chip and preparation method thereof

Also Published As

Publication number Publication date
KR20220139993A (en) 2022-10-17
CN112992964B (en) 2023-07-07
EP4133536A1 (en) 2023-02-15
JP2023525439A (en) 2023-06-16

Similar Documents

Publication Publication Date Title
CN112864290B (en) Miniature LED display and manufacturing method thereof
CN112992964B (en) Light emitting diode structure and manufacturing method thereof
US11410978B2 (en) Process for fabrication of an optoelectronic device comprising a plurality of diodes
US8557616B2 (en) Method for manufacturing a monolithic LED micro-display on an active matrix panel using flip-chip technology and display apparatus having the monolithic LED micro-display
US20190131343A1 (en) Method for producing an optoelectronic device comprising a plurality of gallium nitride diodes
CN114628563B (en) Micro LED display chip and preparation method thereof
WO2023103606A1 (en) Micro-display led chip structure and manufacturing method therefor
CN114284419B (en) Micro light-emitting diode display device and manufacturing method thereof
CN114188459B (en) Micro light-emitting diode display device and manufacturing method thereof
CN115498089B (en) Micro-display device and preparation method
CN114497333A (en) Micro-LED Micro display chip and manufacturing method thereof
JP7442671B2 (en) Full color light emitting diode structure and its manufacturing method
WO2022217648A1 (en) Light emitting diode structure and method for manufacturing thereof
US20210320234A1 (en) Light emitting diode structure and method for manufacturing the same
US11817535B2 (en) Light emitting diode structure and method for manufacturing the same
US20210320145A1 (en) Light Emitting Diode Structure and Method for Manufacturing the Same
JP2024059811A (en) Light emitting diode structure and method of manufacture thereof
CN116565103B (en) Micro LED micro display chip and manufacturing method thereof
US20220140217A1 (en) Light emitting diode structure and method for manufacturing the same
US20230369552A1 (en) Light emitting diode structure and method for manufacturing the same
CN114566515A (en) Micro light-emitting diode display chip and preparation method thereof
CN114784034A (en) Micro-LED Micro display chip and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant