JP2024059811A - Light emitting diode structure and method of manufacture thereof - Google Patents

Abstract

An LED structure with a plurality of individually operable LED units is provided. The light emitting diode (LED) structure includes a substrate 102 and a plurality of LED units 116 formed on the substrate. Each LED unit includes a bonding layer 104 formed on the substrate, a first doping type semiconductor layer 106, a second doping type semiconductor layer 108, a passivation layer 112, and an electrode layer 114 in contact with the second doping type semiconductor layer. The plurality of LED units includes a first LED unit 116-1 and a second LED unit 116-2 adjacent to the first LED unit. The first doping type semiconductor layer of the first LED unit extends horizontally to the first doping type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are individually operable LED units. [Selected Figure]

Description

CROSS-REFERENCES RELATED TO THE APPLICATION This application claims priority to U.S. Provisional Application No. 63/007,829, entitled "Semiconductor Array and Method of Monolithic Integration," filed April 9, 2020, and non-provisional U.S. Application No. 17/162,515, entitled "Light Emitting Diode Structure and Method for Manufacturing the Same," filed January 29, 2021, the contents of which are incorporated herein by reference in their entireties.

The present disclosure relates to a light emitting diode (LED) structure and a method for manufacturing the LED structure, and more specifically to an LED structure having multiple independently functioning LED units sharing a doping layer and a method for manufacturing the same.

In recent years, LEDs have become popular for lighting applications. As a light source, LEDs offer many advantages, including improved luminous efficiency, reduced energy consumption, longer life, smaller size, and faster switching speeds.

Displays with micro-scale LEDs are known as micro-LEDs. Micro-LED displays have an array of micro-LEDs that form individual pixel elements. A pixel is one of many areas that make up an image and may be a tiny area of light on a display screen. In other words, a pixel may be a small individual element that makes up an image on a display. Pixels are usually arranged in a two-dimensional (2D) matrix and are represented using dots, squares, rectangles, or other shapes. Pixels are the basic building blocks of a display or digital image and may have geometric coordinates.

When manufacturing micro-LEDs, etching processes, such as dry etching and wet etching processes, are frequently used to electrically isolate individual micro-LEDs. To generate multiple fully isolated functional micro-LED mesas, conventional processes typically completely etch away a continuous and functional epitaxy layer. However, due to the weak adhesion of the micro-LED mesa, the fully isolated functional micro-LED mesa may easily peel off from the substrate during or after the transfer of the conventional micro-LED mesa to a substrate such as a driving circuit board. This problem becomes even more severe as the micro-LED mesa becomes even smaller. Furthermore, during the conventional etching process to isolate the micro-LED mesa, the sidewalls of the micro-LED mesa may be damaged, affecting the optical and electrical properties of the LED structure.

The disclosed embodiments address the above problems by providing an LED structure with multiple individually functional LED units, showing doping or bonding layers and methods for fabricating the same.

Embodiments of LED structures and methods for forming LED structures are disclosed herein.

In one example, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a bonding layer formed on the substrate, a first doped type semiconductor layer formed on the bonding layer, a second doped type semiconductor layer formed on the first doped type semiconductor layer, a passivation layer formed on a portion of the first doped type semiconductor layer and on the second doped type semiconductor layer, and an electrode layer formed on a portion of the passivation layer and in contact with the second doped type semiconductor layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first doped type semiconductor layer of the first LED unit extends horizontally and is physically connected to the first doped type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are individually functioning LED units.

In another example, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a p-n diode layer formed on the substrate, a passivation layer formed on the p-n diode layer, and an electrode layer formed on the passivation layer and in contact with the p-n diode layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first LED unit and the second LED unit have a common anode, and the first LED unit and the second LED unit are individually functioning LED units.

In a further example, a method for manufacturing an LED structure is disclosed. A semiconductor layer is formed on a first substrate. The semiconductor layer includes a first doping type semiconductor layer and a second doping type semiconductor layer. A first etching operation is performed to expose a portion of the first doping type semiconductor layer and remove a portion of the second doping type semiconductor layer. A second etching operation is performed to remove a portion of the first doping type semiconductor layer and expose a portion of the first substrate with a pixel circuit contact. A passivation layer is formed on the second doping type semiconductor layer and the exposed first doping type semiconductor layer. A third etching operation is performed to form a first opening in the passivation layer of the second doping type semiconductor layer and a second opening in the passivation layer of the first substrate in contact with the pixel circuit. An electrode layer covers the first opening formed on the passivation layer in contact with the second doping type semiconductor layer and the second opening in contact with the pixel circuit and in contact with the first substrate.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the practice of the present disclosure and, together with the description in this specification, further explain the present disclosure and enable one of ordinary skill in the relevant art to practice the present disclosure.

1 shows a plan view of an exemplary LED structure according to some embodiments of the present disclosure. 1 shows a cross-sectional view of an exemplary LED structure according to some embodiments of the present disclosure. 2 shows another cross-sectional view of an exemplary LED structure according to some embodiments of the present disclosure. 2 illustrates another plan view of an exemplary LED structure, according to some embodiments of the present disclosure. 1 shows a top view of another example LED structure, according to some embodiments of the present disclosure. 1A-1D illustrate cross sections of an exemplary LED structure at different stages of a manufacturing process according to some embodiments of the present disclosure. 1A-1D illustrate cross sections of an exemplary LED structure at different stages of a manufacturing process according to some embodiments of the present disclosure. 1A-1D illustrate cross sections of an exemplary LED structure at different stages of a manufacturing process according to some embodiments of the present disclosure. 1A-1D illustrate cross sections of an exemplary LED structure at different stages of a manufacturing process according to some embodiments of the present disclosure. 1A-1D illustrate cross sections of an exemplary LED structure at different stages of a manufacturing process according to some embodiments of the present disclosure. 1A-1D illustrate cross sections of an exemplary LED structure at different stages of a manufacturing process according to some embodiments of the present disclosure. 1A-1D illustrate cross sections of an exemplary LED structure at different stages of a manufacturing process according to some embodiments of the present disclosure. 1A-1D illustrate cross sections of an exemplary LED structure at different stages of a manufacturing process according to some embodiments of the present disclosure. 1 is a flowchart of an exemplary method for fabricating an LED structure according to some embodiments of the present disclosure.

Embodiments of the present disclosure are described with reference to the accompanying drawings.

While particular configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be used for a variety of other applications. The functional and structural features described in the present disclosure can be combined, coordinated, and modified with one another in ways not specifically shown in the drawings, such that such combinations, coordination, and modifications are within the scope of the present disclosure.

Generally, terms can be understood at least in part from their usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to indicate either the singular use or the plural use, depending at least in part on the context. Furthermore, the term "based on" may be understood not to be necessarily intended to indicate exclusive factors, but instead may allow for the existence of additional factors not necessarily explicitly described, depending at least in part on the context.

It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest manner, such that "on" does not only mean "directly on" something, but also includes the meaning of "on" something with intermediate features or layers between them, and "above" or "over" does not only mean "above" or "over" something, but also includes the meaning of "above" or "over" something without intermediate features or layers (i.e., directly on something).

In addition, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like, may be used to describe the relationship of one element to another element and function as shown in the drawings for ease of description. Spatially relative terms are intended to encompass various orientations of the device during use or operation in addition to the orientation shown in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be interpreted accordingly.

As used herein, the term "layer" refers to a portion of material that includes a region of thickness. A layer can extend across an underlying or overlying structure, or it can have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be disposed between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces above it. A layer can extend along horizontal, vertical, and/or tapered surfaces. A substrate can be a layer and can include one or more layers therein and/or have one or more layers above and/or below it. A layer can include multiple layers. For example, a semiconductor layer can include one or more doped or undoped semiconductor layers and can have the same or different materials.

As used herein, the term "substrate" refers to a material to which a subsequent layer of material is added. The substrate itself can be patterned. The material added onto the substrate can be patterned or left unpatterned. Additionally, the substrate can include a wide range of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made from a non-conductive material, such as glass, plastic, or a sapphire wafer. Additionally, the substrate can alternatively have semiconductor devices or circuits formed therein.

As used herein, the term "micro" LED, "micro" p-n diode or "micro" device refers to a descriptive dimension of a particular device or structure according to the practice of the present disclosure. As used herein, the term "micro" device or structure is meant to refer to a dimension of 0.1 to 100 μm. However, it should be understood that the practice of the present disclosure is not necessarily so limited and that certain aspects of the practice may be applicable to larger and possibly smaller dimension scales.

The implementation of the present invention describes an LED or micro LED structure and a method for fabricating the structure. To fabricate a micro LED display, an epitaxy layer is bonded to a receiving substrate. The receiving substrate may be a display substrate, including, for example, but not limited to, a CMOS backplane or a TFT glass substrate. The epitaxy layer is then formed with an array of micro LEDs on the receiving substrate. When forming micro LEDs on the receiving substrate, the adhesion of the small functional mesas to the receiving substrate is weak and proportional to the size of the mesa, so that multiple small functional mesas may peel off from the receiving substrate and cause display failures (dead pixels) during the fabrication process. To address the aforementioned problem, the present disclosure introduces a solution that allows the functional epitaxy layer to be partially patterned/etched, leaving a thin continuous functional layer and bonding layer to avoid potential peeling. Furthermore, the fabrication method described in the present disclosure can further reduce physical damage to the sidewalls of the functional mesas, reduce damage to the quantum well structure, which is the light emitting region of the LED, and improve the optical and electrical properties of the functional mesas.

FIG. 1 shows a plan view of an exemplary LED structure 100 according to some embodiments of the present disclosure, and FIG. 2 shows a cross-sectional view of the exemplary LED structure 100 along line A-A' according to some embodiments of the present disclosure. To better explain the present disclosure, the plan view of the LED structure 100 in FIG. 1 and the cross-sectional view of the LED structure 100 in FIG. 2 are described together. The LED structure 100 includes a first substrate 102 and a plurality of LED units 116 (e.g., LED units 116-1, 116-2, 116-3, and 116-4 as shown in FIG. 2). The LED units 116 are bonded onto the first substrate 102 via a bonding layer 104. In some embodiments, the first substrate 102 may include a semiconductor material such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, or the like. In some embodiments, the first substrate 102 may be made of a non-conductive material such as glass, plastic, or a sapphire wafer. In some embodiments, the first substrate 102 may have a driving circuit formed therein, and the first substrate 102 may be a CMOS backplane or a TFT glass substrate. The driving circuit provides electronic signals to the LED units 116 to control brightness. In some embodiments, the driving circuit may include an active matrix driving circuit in which each LED unit 116 corresponds to an independent driver. In some embodiments, the driving circuit may include a passive matrix driving circuit in which a plurality of LED units 116 are arranged in an array and connected to data lines and scan lines that are driven by the driving circuit.

The bonding layer 104 is a layer of adhesive formed on the first substrate 102 to bond the first substrate 102 and the LED unit 116. In some embodiments, the bonding layer 104 may include a conductive material such as a metal or a metal alloy. In some examples, the bonding layer 104 may include gold, tin, indium, copper, or titanium. In some embodiments, the bonding layer 104 may include a non-conductive material such as polyimide (PI), polydimethylsiloxane (PDMS), etc. In some embodiments, the bonding layer 104 may include a photoresist such as SU-8 photoresist. In some embodiments, the bonding layer 104 may be hydrosilsesquioxane (HSQ) or divinylsiloxane-bis-benzocyclobutene (DVS-BCB). It is understood that the description of the material of the bonding layer 104 is merely exemplary and not limiting, and can be modified as required by those skilled in the art, all of which are within the scope of the present application.

Referring to FIG. 2, each LED unit 116 includes its portion of the bonding layer 104, a first doped type semiconductor layer 106, and a second doped type semiconductor layer 108. The first doped type semiconductor layer 106 is formed on the bonding layer 104. In some embodiments, the first doped type semiconductor layer 106 and the second doped type semiconductor layer 108 may include one or more layers based on II-VI materials such as ZnSe and ZnO, or III-V nitride materials such as GaN, AlN, InN, InGaN, GaP, AlInGaP, AlGaAs, and alloys thereof.

In some embodiments, the first doped type semiconductor layer 106 may be a p-type semiconductor layer that spans multiple LED units 116 (e.g., four LED units 116 as shown in FIG. 2) and forms a common anode for these LED units 116. For example, the first doped type semiconductor layer 106 of LED unit 116-2 extends to adjacent LED units 116-1 and 116-3, and similarly, the first doped type semiconductor layer 106 of LED unit 116-3 extends to adjacent LED units 116-2 and 116-4. In some embodiments, the first doped type semiconductor layer 106 that extends across the LED units may be relatively thin. In some embodiments, the thickness of the first doped type semiconductor layer 106 may be between about 0.05 μm and about 1 μm. In other embodiments, the thickness of the first doped type semiconductor layer 106 may be between about 0.05 μm and about 0.7 μm. In some alternative embodiments, the thickness of the first doped type semiconductor layer 106 may be between about 0.05 μm and about 0.5 μm. By having a continuous thin layer of the first doped type semiconductor throughout the individual LED units, the bonding area between the first substrate 102 and the plurality of LED units 116 is not limited to the area under the second doped type semiconductor layer 108, but also extends to the area between the individual LED units. In other words, by having a continuous thin layer of the first doped type semiconductor, the area of the bonding layer 104 is increased. Thus, the bonding strength between the first substrate 102 and the plurality of LED units 116 is enhanced, and the risk of delamination of the LED structure 100 can be reduced.

In some embodiments, the first doped type semiconductor layer 106 may be p-type GaN. In some embodiments, the first doped type semiconductor layer 106 may be formed by doping GaN with magnesium (Mg). In some embodiments, the first doped type semiconductor layer 106 may be p-type InGaN. In some embodiments, the first doped type semiconductor layer 106 may be p-type AlInGaP. Each of the LED units 116 has an anode and a cathode connected to a driving circuit, for example, formed on the first substrate 102 (driving circuit not explicitly shown). For example, each LED unit 116 has an anode connected to a constant voltage source and a cathode connected to the source/drain electrodes of the driving circuit. In other words, by forming a continuous first doped type semiconductor layer 106 across the individual LED units 116, the multiple LED units 116 have a common anode formed by the first doped type semiconductor layer 106 and the bonding layer 104.

In some embodiments, the second doped type semiconductor layer 108 may be an n-type semiconductor layer and forms the cathode of each LED unit 116. In some embodiments, the second doped type semiconductor layer 108 may be n-type GaN. In some embodiments, the second doped type semiconductor layer 108 may be n-type InGaN. In some embodiments, the second doped type semiconductor layer 108 may be n-type AlInGaP. The second doped type semiconductor layers 108 of different LED units 116 are electrically isolated, and thus each LED unit 116 has a cathode that can have a different voltage level than the other units. As a result of the disclosed implementations, a plurality of individually functional LED units 116 are formed with the first doped type semiconductor layer 106 extending horizontally across adjacent LED units and the second doped type semiconductor layer 108 being electrically isolated between adjacent LED units.

Each LED unit 116 further includes a multiple quantum well (MQW) layer 110 formed between the first doped type semiconductor layer 106 and the second doped type semiconductor layer 108. The MQW layer 110 is the active region of the LED unit 116. In some embodiments, the thickness including the first doped type semiconductor layer 106, the MQW layer 110, and the second doped type semiconductor layer 108 may be between about 0.3 μm and about 5 μm. In other embodiments, the thickness including the first doped type semiconductor layer 106, the MQW layer 110, and the second doped type semiconductor layer 108 may be between about 0.4 μm and about 4 μm. In some alternative embodiments, the thickness including the first doped type semiconductor layer 106, the MQW layer 110, and the second doped type semiconductor layer 108 may be between about 0.5 μm and about 3 μm.

As shown in FIG. 2, a passivation layer 112 is formed on the second doped type semiconductor layer 108 and a portion of the first doped type semiconductor layer 106. The passivation layer 112 may be used to protect and isolate the LED units 116. In some embodiments, the passivation layer 112 may include SiO ₂ , Al ₂ O ₃ , SiN, or other suitable materials. In some embodiments, the passivation layer 112 may include polyimide, SU-8 photoresist, or other photopatternable polymers. An electrode layer 114 is formed on a portion of the passivation layer 112, and the electrode layer 114 is in electrical communication with the second doped type semiconductor layer 108 through an opening on the passivation layer 112. In some embodiments, the electrode layer 114 may be a conductive material such as indium tin oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge, or Ni.

3 shows another cross-sectional view of the exemplary LED structure 100 along line B-B' according to some embodiments of the present disclosure. The first substrate 102 has a driving circuit formed therein to drive the LED units 116. A contact 118 of the driving circuit is exposed between the two LED units 116, and the contact 118 is electrically connected to the second doped type semiconductor layer 108 through the electrode layer 114. In other words, the electrical connection between the second doped type semiconductor layer 108 and the contact 118 of the driving circuit is achieved by the electrode layer 114. As described above, the second doped type semiconductor layer 108 forms the cathode of each LED unit 116, and thus the contact 118 provides the driving voltage of the cathode of each LED unit 116 from the driving circuit to the second doped type semiconductor layer 108 through the electrode layer 114.

Figure 4 shows another plan view of an LED structure 100 according to some embodiments of the present disclosure. In Figure 4, the layers below the electrode layer 114 and the passivation layer 112 are shown with dashed lines for illustration purposes. In Figure 4, the LED structure 100 includes 16 LED units 116. Each LED unit 116 includes a p-n diode layer formed by a first doped type semiconductor layer 106 and a second doped type semiconductor layer 108 and a multiple quantum well 110. The passivation layer 112 is formed on the p-n diode layer, and the electrode layer 114 is formed on the passivation layer 112.

The opening 120 is formed on the passivation layer 112 exposing the second doped type semiconductor layer 108, and the opening 122 is formed on the passivation layer 112 exposing the contact portion 118. The electrode layer 114 is formed on a portion of the passivation layer 112 covering the opening 120 and the opening 122. Thus, the electrode layer 114 electrically connects with the second doped type semiconductor layer 108 and the contact portion 118. In the example shown in FIG. 4, the opening 120 is disposed at the center of each LED unit 116, and the opening 122 is disposed in the space between adjacent LED units 116. It is understood that the positions and designs (such as shapes and sizes) of the opening 120, the opening 122, and the electrode layer 114 may deviate from the example shown in FIG. 4 based on requirements and are not limited thereto.

In FIG. 4, the LED structure 100 includes 16 LED units 116, each of which can function individually. The first doped type semiconductor layer 106 is located under the second doped type semiconductor layer 108 and the passivation layer 112, and the first doped type semiconductor layer 106 is a common anode for these 16 LED units 116. When the first doped type semiconductor layers 106 of these LED units (e.g., the 16 LED units 116) are electrically connected not only during the manufacturing process to form the LED structure 100 but also after the manufacturing process, throughout this disclosure, the multiple LED units are said to be "individually functional", and each LED unit 116 can be driven individually by a different driving circuit.

5 shows a plan view of another LED structure 500 according to some embodiments of the present disclosure. The shape of the second doped type semiconductor layer 108 in the plan view of FIG. 5 is circular, which is different from the shape of the second doped type semiconductor layer 108 in the plan view of the LED structure 100 shown in FIG. 4. In some embodiments, the position and shape of the second doped type semiconductor layer 108 in the plan view can be changed according to various designs or applications, and it is understood that the shape of the second doped type semiconductor layer 108 or the LED unit 116 in the plan view is not limited thereto. In some embodiments, the position and shape of the opening 120, the opening 122, the electrode layer 114, or the contact 118 in the plan view can also be changed according to various designs and applications, and is not limited thereto.

Figures 6A-6H show cross-sections of an exemplary LED structure 100 during a manufacturing process according to some embodiments of the present disclosure. Figure 7 is a flowchart of an exemplary manufacturing method 700 for manufacturing an LED structure 100 according to some embodiments of the present disclosure. To better explain the present disclosure, Figures 6A-6I and the flowchart of Figure 7 are described together. In Figure 6A, a driving circuit is formed on a first substrate 102, and the driving circuit includes a contact portion 118. For example, the driving circuit may include a CMOS device fabricated on a silicon wafer, and several wafer-level packaging layers or fan-out structures are stacked on the CMOS device to form the contact portion 118. As another example, the driving circuit may include a TFT fabricated on a glass substrate, and several wafer-level packaging layers or fan-out structures are stacked on the TFT to form the contact portion 118. A semiconductor layer is formed on a second substrate 124, and the semiconductor layer includes a first doping type semiconductor layer 106, a second doping type semiconductor layer 108, and an MQW layer 110.

In some embodiments, the first substrate 102 or the second substrate 124 may include a semiconductor material such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. In some embodiments, the first substrate 102 or the second substrate 124 may be made of a non-conductive material such as glass, plastic, or a sapphire wafer. In some embodiments, the first substrate 102 may have driving circuitry formed therein, and the first substrate 102 may include a CMOS backplane or a TFT glass substrate. In some embodiments, the first doped semiconductor layer 106 and the second doped semiconductor layer 108 may include one or more layers based on II-VI materials such as ZnSe and ZnO, or III-V nitride materials such as GaN, AlN, InN, InGaN, GaP, AlInGap, AlGaAs, and alloys thereof. In some embodiments, the first doped type semiconductor layer 106 may include a p-type semiconductor layer and the second doped type semiconductor layer 108 may include an n-type semiconductor layer.

In FIG. 6B, a bonding layer 104 is formed on the first substrate 102. In some embodiments, the bonding layer 104 may include a conductive material such as a metal or metal alloy. In some embodiments, the bonding layer 104 may include Au, Sn, In, Cu, or Ti. In some embodiments, the bonding layer 104 may include a non-conductive material such as polyimide (PI), polydimethylsiloxane (PDMS), or the like. In some embodiments, the bonding layer 104 may include a photoresist such as SU-8 photoresist. In some embodiments, the bonding layer 104 may include hydrosilsesquioxane (HSQ) or divinylsiloxane-bis-benzocyclobutene (DVS-BCB). In some embodiments, a conductive layer 126 may be formed on the first doped semiconductor layer 106. In some embodiments, the conductive layer 126 may form a common electrode over the first doped semiconductor layer 106. In some embodiments, the conductive layer 126 may form an ohmic contact on the first doped semiconductor layer 106. In some embodiments, the conductive layer 126 and the bonding layer 104 may be collectively referred to as one layer in subsequent operations.

6C and 7, the second substrate 124 and semiconductor layers including the first doped semiconductor layer 106, the second doped semiconductor layer 108, and the MQW layer 110 are flipped over and bonded to the first substrate 102 via the bonding layer 104 and the conductive layer 126. The second substrate 124 is then removed from the semiconductor layers. FIG. 6C shows the bonding layer 104 between the first substrate 102 and the first doped semiconductor layer 106. However, in some embodiments, the bonding layer 104 may include one or more layers for bonding the first substrate 102 and the first doped semiconductor layer 106. For example, the bonding layer 104 may include a single conductive or non-conductive layer. As another example, the bonding layer 104 may include an adhesive and a conductive or non-conductive layer. In some embodiments, the bonding layer 104 and the conductive layer 126 may be collectively referred to as one layer after the operation 702. The description of the materials for the bonding layer 104 is merely illustrative and not limiting, and those skilled in the art can make modifications as required, all of which are understood to be within the scope of this application.

6D, a thinning operation may be performed on the second doped type semiconductor layer 108 to remove a portion of the second doped type semiconductor layer 108. In some embodiments, the thinning operation may include a dry etching or wet etching operation. In some embodiments, the thinning operation may include a chemical mechanical polishing (CPM) operation. In some embodiments, the thickness including the first doped type semiconductor layer 106, the MQW layer 110, and the second doped type semiconductor layer 108 may be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness including the first doped type semiconductor layer 106, the MQW layer 110, and the second doped type semiconductor layer 108 may be between about 0.4 μm and about 4 μm. In some other embodiments, the thickness including the first doped type semiconductor layer 106, the MQW layer 110, and the second doped type semiconductor layer 108 may be between about 0.5 μm and about 3 μm.

6E and 7, a first etching operation may be performed to remove a portion of the second doped type semiconductor layer 108 and expose a portion of the first doped type semiconductor layer 106. The portion of the first doped type semiconductor layer 106 is exposed until a predetermined thickness of the first doped type semiconductor layer 106 remains on the first substrate 102. In some embodiments, the remaining first doped type semiconductor layer 106 extends horizontally across a plurality of LED units 116 (such as the four LED units 116 shown in FIG. 6E) of the LED structure 100. In some embodiments, the predetermined thickness of the first doped type semiconductor layer 106 may be between about 0.05 μm and about 1 μm. In other embodiments, the predetermined thickness of the first doped type semiconductor layer 106 may be between about 0.05 μm and about 0.7 μm. In some alternative embodiments, the predetermined thickness of the first doped type semiconductor layer 106 may be between about 0.05 μm and about 0.5 μm. After operation 704, the second doped type semiconductor layer 108 and the MQW layer 110 of each LED unit 116 may be electrically isolated, and the first doped type semiconductor layers 106 of adjacent LED units 116 (such as LED units 116-1, 116-2, 116-3, and 116-4) may be electrically connected.

In some embodiments, during operation 704, a first etching operation is performed to remove a portion of the second doped type semiconductor layer 108 to expose a portion of the MQW layer 110. The portion of the MQW layer 110 is exposed until a predetermined thickness of the first doped type semiconductor layer 106 and the MQW layer 110 remains on the first substrate 102. In some embodiments, the remaining first doped type semiconductor layer 106 and the MQW layer 110 extend horizontally across a plurality of LED units 116 (such as the four LED units 116 shown in FIG. 6E) of the LED structure 100. In some embodiments, the predetermined thickness of the first doped type semiconductor layer 106 and the MQW layer 110 may be between about 0.05 μm and about 1 μm. In other embodiments, the predetermined thickness of the first doped type semiconductor layer 106 and the MQW layer 110 may be between about 0.05 μm and about 0.7 μm. In some alternative embodiments, the predetermined thickness of the first doped type semiconductor layer 106 and the MQW layer 110 may be between about 0.05 μm and about 0.5 μm. After operation 704, the second doped type semiconductor layer 108 of each LED unit 116 may be electrically isolated, and the first doped type semiconductor layer 106 and the MQW layer 110 of adjacent LED units 116 (LED units 116-1, 116-2, 116-3, 116-4, etc.) may be electrically connected.

Referring to FIG. 6F, a second etching operation may be performed to remove a portion of the first doped type semiconductor layer 106 to expose the contact 118. The second etching operation may be a dry etching or wet etching operation. In the dry etching or wet etching operation, a hard mask (e.g., photoresist) may be formed on the second doped type semiconductor layer 108 and a portion of the first doped type semiconductor layer 106 by a photolithography process. Then, the uncovered portion of the first doped type semiconductor layer 106 is removed by a dry etching plasma or a wet etching solution to expose the contact 118.

6G and operation 706 of FIG. 7, a passivation layer 112 is formed over the second doped type semiconductor layer 108, the exposed first doped type semiconductor layer 106, and the exposed contact 118. In some embodiments, the passivation layer 112 may include SiO2, Al2O3, SiN, or other suitable materials for isolation and protection. In some embodiments, the passivation layer 112 may include polyimide, SU-8 photoresist, or other photopatternable polymer. In operation 708 of FIG. 7, an opening 120 and an opening 122 are formed, as shown in FIG. 6G. The opening 120 exposes a portion of the second doped type semiconductor layer 108, and the opening 122 exposes the contact 118. In some embodiments, the operation 708 may be done by a third etching operation to remove a portion of the passivation layer 112 to form the opening 120 and the opening 122. In some further embodiments, when the provided passivation layer 112 is formed of a photosensitive material (e.g., polyimide, SU-8 photoresist, or other photopatternable polymer), the operation of 708 may be performed by a photolithography operation to pattern the passivation layer 112, exposing the openings 120 and 122.

6H and operation 710 of FIG. 7, the electrode layer 114 is formed on the passivation layer 112 to cover the opening 120 and the opening 122. Thus, the electrode layer 114 electrically connects the second doped type semiconductor layer 108 and the contact 118, forming an electrical path for connecting the LED unit with a driving circuit of the first substrate 102. The driving circuit may control the voltage and current levels of the second doped type semiconductor layer 108 through the contact 118 and the electrode layer 114. In some embodiments, the electrode layer 114 may include a conductive material such as indium tin oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge, or Ni.

The present disclosure provides an LED structure and a method for manufacturing the LED structure in which the functional epitaxy layers, such as the first doped semiconductor layer 106 and the second doped semiconductor layer 108, are partially patterned/etched to leave a thin continuous functional layer (such as the first doped semiconductor layer 106) avoiding potential peeling. In addition, the present disclosure also provides another option for leaving the MQW layer on the first doped semiconductor layer 106. The manufacturing method introduced in the present disclosure can also further reduce physical damage to the sidewalls of the functional mesa (such as the LED unit 116), reduce damage to the quantum well structure, which is the light-emitting region of the LED, and improve the optical and electrical properties of the functional mesa.

According to one aspect of the present disclosure, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a bonding layer formed on the substrate, a first doped type semiconductor layer formed on the bonding layer, a second doped type semiconductor layer formed on the first doped type semiconductor layer, a passivation layer formed on the second doped type semiconductor layer and a portion of the first doped type semiconductor layer, and an electrode layer formed on a portion of the passivation layer and in contact with the second doped type semiconductor layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first doped type semiconductor layer of the first LED unit extends horizontally to the first doped type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are individually functioning LED units.

In some embodiments, the second doped type semiconductor layer of the first LED unit is electrically insulated from the second doped type semiconductor layer of the second LED unit. In some embodiments, each LED unit further includes a multiple quantum well (MQW) layer formed between the first doped type semiconductor layer and the second doped type semiconductor layer.

In some embodiments, the first doped semiconductor layer is a p-type semiconductor layer and is a common anode of the first LED unit and the second LED unit. In some embodiments, the second doped semiconductor layer is an n-type semiconductor layer and is a cathode of the first LED unit and the second LED unit.

In some embodiments, the substrate includes a drive circuit for driving the plurality of LED units. In some embodiments, the electrode layer of each LED unit is connected to the drive circuit through an opening in the first doped semiconductor layer.

According to another aspect of the present disclosure, an LED structure is disclosed. The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a p-n diode layer formed on the substrate, a passivation layer formed on the p-n diode layer, and an electrode layer formed on the passivation layer and in contact with the p-n diode layer. The plurality of LED units includes a first LED unit and a second LED unit adjacent to the first LED unit. The first LED unit and the second LED unit have a common anode, and the first LED unit and the second LED unit are individually functioning LED units.

In some embodiments, the p-n diode layer includes a p-doped layer, an n-doped layer, and a multiple quantum well (MQW) layer formed between the p-doped layer and the n-doped layer. In some embodiments, the p-doped layer is a common anode of the first LED unit and the second LED unit. In some embodiments, the n-doped layers of the first LED unit and the second LED unit are electrically isolated.

In some embodiments, each LED unit further includes a bonding layer formed between the substrate and the p-n diode layer. In some embodiments, the substrate includes a drive circuit for driving the plurality of LED units. In some embodiments, the electrode layer of each LED unit is connected to the drive circuit through an opening in the p-n diode layer.

According to a further aspect of the present disclosure, a method for fabricating an LED structure is disclosed. A semiconductor layer is formed on a first substrate. The semiconductor layer includes a first doping type semiconductor layer and a second doping type semiconductor layer. A first etching operation is performed to remove a portion of the second doping type semiconductor layer to expose a portion of the first doping type semiconductor layer. A passivation layer is formed on the second doping type semiconductor layer and the exposed first doping type semiconductor layer. A first opening is formed on the passivation layer. An electrode layer is formed on the passivation layer to cover the first opening and contact the second doping type semiconductor layer.

In some embodiments, performing the first etching operation further comprises removing a portion of the second doping type semiconductor layer and exposing a portion of the first doping type semiconductor layer until a predetermined thickness of the first doping type semiconductor layer remains on the first substrate. The remaining first doping type semiconductor layer extends horizontally across multiple LED units of the LED structure.

In some embodiments, forming the semiconductor layer on the first substrate further includes bonding the semiconductor layer onto the first substrate via a bonding layer. In some embodiments, forming the semiconductor layer on the first substrate further includes forming a drive circuit on the first substrate, forming a semiconductor layer on a second substrate, bonding the semiconductor layer onto the first substrate via a bonding layer, and removing the second substrate.

In some embodiments, forming a first opening on the passivation layer further includes forming a second opening on the passivation layer to expose a contact of the drive circuit. In some embodiments, forming an electrode layer on the passivation layer covering the first opening and in contact with the second doped type semiconductor layer further includes forming an electrode layer on the passivation layer covering the first opening and the second opening to electrically connect the second doped type semiconductor layer to the contact of the drive circuit.

The foregoing description of specific embodiments may be readily modified and/or adapted for a variety of applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance disclosed herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (16)

A light emitting diode (LED) structure including a substrate and a plurality of LED units formed on the substrate,
a bonding layer is formed on the substrate, and a first doped semiconductor layer is formed on the bonding layer, the first doped semiconductor layer forming a common electrode of the plurality of LED units;
Each LED unit further includes:
a second doped type semiconductor layer formed on the first doped type semiconductor layer;
A contact portion formed on the substrate;
an electrode layer in contact with the contact portion and the second doped type semiconductor layer;
the second doped type semiconductor layer constitutes the other electrode of the LED unit, and the contact portion is configured to provide a driving voltage to the LED unit through the electrode layer so that the plurality of LED units can function individually. 2. The light emitting diode structure of claim 1, wherein the second doping type semiconductor layer of any one of the plurality of LED units is electrically insulated from the second doping type semiconductor layer of an adjacent LED unit. 10. The light emitting diode structure of claim 1, wherein each LED unit further comprises a multiple quantum well (MQW) layer formed between the first doped type semiconductor layer and the second doped type semiconductor layer. 2. The light emitting diode structure of claim 1, wherein the first doping type semiconductor layer is a p-type semiconductor layer and the second doping type semiconductor layer is an n-type semiconductor layer . Each LED unit further includes a passivation layer formed on a portion of the first doped type semiconductor layer and the second doped type semiconductor layer;
2. The light emitting diode structure of claim 1, wherein the electrode layer is formed on a portion of the passivation layer. 2. The light emitting diode structure of claim 1, wherein the substrate includes a driving circuit configured to drive the plurality of LED units through the contacts . 7. The light emitting diode structure of claim 6 , wherein the first doping type semiconductor layer is provided with a plurality of openings to expose the contacts, and the electrode layer is connected to the contacts through the openings. the bonding layer is made of a conductive material; and/or
2. The light emitting diode structure as claimed in claim 1, further comprising a conductive layer disposed between the bonding layer and the first doped type semiconductor layer and in ohmic contact with the first doped type semiconductor layer. Bonding a semiconductor layer onto a first substrate by a bonding layer , the semiconductor layer including a first doped type semiconductor layer and a second doped type semiconductor layer disposed sequentially in a direction away from the bonding layer ;
performing a first etching operation to remove a portion of the second doped type semiconductor layer to form a plurality of second doped type semiconductor mesas electrically insulated from each other and to expose a portion of the first doped type semiconductor layer between adjacent second doped type semiconductor mesas , wherein the first doped type semiconductor layer constitutes a common electrode of a plurality of LED units and each second doped type semiconductor mesa constitutes the other electrode of one LED unit;
performing a second etching operation to form a plurality of openings in the exposed portion of the first doped type semiconductor layer to expose a plurality of contacts in the first substrate, the plurality of contacts having a one-to-one correspondence with the plurality of second doped type semiconductor mesas, each contact being configured to provide a voltage to one LED unit;
forming an electrode layer for each LED unit, the electrode layer simultaneously contacting a second doping type semiconductor mesa and a corresponding contact portion of the LED unit, whereby the second doping type semiconductor mesa and the contact portion are connected to enable the LED units to function individually. Before forming the electrode layer of each LED unit, the manufacturing method includes:
forming a passivation layer over the semiconductor layer;
10. The method of claim 9, further comprising: forming a first opening in the passivation layer over each second doping type semiconductor mesa to expose a portion of the second doping type semiconductor mesa; and forming a second opening in the passivation layer over each contact to expose the contact. The first etching operation is performed by:
thinning the exposed portion of the first doped type semiconductor layer to a predetermined thickness ;
The method of claim 9 , wherein the first doping type semiconductor layer of predetermined thickness extends horizontally between the plurality of LED units. Prior to bonding the semiconductor layer onto the first substrate by the bonding layer, the method further comprises:
forming a drive circuit comprising the plurality of contacts on the first substrate;
forming the semiconductor layer on a second substrate ;
After bonding the semiconductor layer onto the first substrate by the bonding layer, the method further comprises:
The method of claim 9 further comprising removing the second substrate. After forming the semiconductor layer on the second substrate, the method further comprises:
forming a conductive layer on the semiconductor layer, the conductive layer covering the first doped type semiconductor layer and in ohmic contact with the first doped type semiconductor layer;
The bonding of the semiconductor layer onto the first substrate by the bonding layer may include:
The method of claim 12 , further comprising bonding the semiconductor layer onto the first substrate through the bonding layer and the conductive layer. The method according to claim 9 or 13, wherein the bonding layer is made of a conductive material. 10. The method of claim 9, wherein the semiconductor layer further comprises a multiple quantum well layer formed between the first doped type semiconductor layer and the second doped type semiconductor layer. 10. The method of claim 9, wherein the first doping type semiconductor layer is a p-type semiconductor layer and the second doping type semiconductor layer is an n-type semiconductor layer.