CN112992834A - Advanced diode packaging structure with indirect electrical connection of source and grid - Google Patents
Advanced diode packaging structure with indirect electrical connection of source and grid Download PDFInfo
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- CN112992834A CN112992834A CN202110177369.XA CN202110177369A CN112992834A CN 112992834 A CN112992834 A CN 112992834A CN 202110177369 A CN202110177369 A CN 202110177369A CN 112992834 A CN112992834 A CN 112992834A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/0905—Shape
- H01L2224/09051—Bonding areas having different shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/4909—Loop shape arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Abstract
The invention discloses an advanced diode packaging structure with source-grid indirect electric connection, which comprises a semiconductor device chip, a cathode metal sheet, an anode metal sheet and a plastic package body, wherein the cathode metal sheet is arranged on the semiconductor device chip; a source bonding pad and a grid bonding pad are arranged on the first surface of the semiconductor device chip; a drain electrode bonding pad is arranged on the second surface of the semiconductor device chip; the source electrode and the grid electrode of the semiconductor device chip are not directly short-circuited; when the source electrode bonding pad and the grid electrode bonding pad are directly in short circuit, the semiconductor device chip is an MOS type advanced diode; the source electrode bonding pad and the grid electrode bonding pad are respectively bonded with the anode metal sheet through the electric connectors. The invention utilizes the packaging electrical connection resistor, introduces an extra voltage drop between the source electrode and the grid electrode when the advanced diode works in the forward direction, promotes the opening of a channel and maintains the leakage current IRThe forward breakover voltage V of the device is reduced under the condition of constant or lower voltageFThe performance of the advanced diode is improved; the complexity of the device is not increased, and the method has wide applicability.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to an advanced diode packaging structure with source and gate indirect electric connection.
Background
The conventional silicon diode with PN junction structure forms an internal electric field due to the attraction and constraint action among particles of PN junction region, thereby realizing the forward conduction voltage (V)F) Usually around 0.7V. With the current technical development, various advanced diodes with different structures break through the limitation, the forward conduction voltage is further reduced on the premise of lower reverse leakage current, the forward conduction voltage can be as low as 0.4V, and the diode has other excellent performances. The advanced diode with the MOS structure region is widely applied by utilizing the advantages of low forward conducting voltage, high switching speed, less turn-off leakage, excellent high-temperature characteristic and the like of channel control of the MOS structure region.
In the prior art, since the semiconductor device chip of the advanced diode generally has a front electrode and a back electrode, the two electrodes need to be led to the same face through the package so as to be electrically connected with other parts of the circuit. Fig. 1 illustrates a conventional packaging method in the prior art, in which a bare chip is disposed on a cathode metal sheet, a back electrode of the bare chip is bonded to the cathode metal sheet, and a front electrode of the bare chip is bonded to an anode metal sheet through a lead and then is subjected to plastic packaging. The equivalent circuit is shown in fig. 2, and the front electrode is obtained by directly shorting a source electrode and a grid electrode on a chip.
For advanced diodes, if the channel can be kept on at a lower forward voltage, the forward conduction voltage V isFAnd will be correspondingly lower, further reducing energy losses. In the prior art, for example, a document with a publication number of CN102904421B provides an alternative circuit scheme for controlling a gate voltage of a MOS transistor by using a control circuit to open a channel at a low voltage, but the scheme has many components, a complex structure, and high switching speed and high temperature characteristicsThe method is limited in energy and cannot be universally applied to various high-power application scenes.
Disclosure of Invention
The invention aims to provide a method for indirectly and electrically connecting a source electrode and a grid electrode in an advanced diode, which utilizes a packaging electric connection resistor to introduce an extra voltage drop between the source electrode and the grid electrode when the advanced diode works in the forward direction so as to promote the opening of a channel of an MOS structure region in the advanced diode and improve the leakage current IRLowering the forward pass voltage V unchanged or lowerFAnd the overall performance of the advanced diode is improved.
In order to achieve the above object, the present invention provides an advanced diode package structure with source-gate indirect electrical connection, comprising a semiconductor device chip, a cathode metal sheet, an anode metal sheet, and a plastic package body;
a source bonding pad and a grid bonding pad are arranged on the first surface of the semiconductor device chip; a drain electrode bonding pad is arranged on the second surface of the semiconductor device chip; the semiconductor device chip comprises an active region with a MOS structure region; threshold voltage V of the MOS structure regionthLess than 0.7V, further, VthLess than 0.4V; the source electrode and the grid electrode of the semiconductor device chip are not directly short-circuited; when the source electrode bonding pad and the grid electrode bonding pad are directly short-circuited, the semiconductor device chip is an advanced diode, and the forward conducting voltage V of the advanced diodeFLess than 0.7V; the performance of the present invention is correspondingly better when the performance of the advanced diode is better, the advanced diode has VFV of the invention at a low of 0.4VFCan be as low as 0.3V.
The semiconductor device chip is arranged on the cathode metal sheet; the drain electrode bonding pad is bonded with the cathode metal sheet; the source electrode bonding pad and the grid electrode bonding pad are respectively bonded with the anode metal sheet through electric connection pieces;
the plastic package body coats the semiconductor device chip, the cathode metal sheet, the anode metal sheet and the electric connecting piece; one end of the cathode metal sheet and one end of the anode metal sheet are respectively a cathode pin and an anode pin; the cathode pin and the anode pin are respectively exposed outside the plastic package body.
Preferably, the electric connector is a lead or a conductive metal sheet; preferably, the conductive metal sheet is a metal copper sheet.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention utilizes the packaging electrical connection resistor, introduces an extra voltage drop between the source electrode and the grid electrode when the advanced diode works in the forward direction, promotes the opening of a channel and maintains the leakage current IRThe forward breakover voltage V of the device is reduced under the condition of constant or lower voltageFThe performance of the advanced diode is improved.
2. The invention can improve the performance of the advanced diode only by slightly changing the chip and the packaging structure of the semiconductor device, does not increase the complexity of the device and has wide applicability.
Drawings
FIG. 1 is a diagram of an advanced diode package in the prior art;
FIG. 2 is an equivalent circuit diagram of an advanced diode package structure in the prior art;
fig. 3 is a schematic cross-sectional view of a semiconductor device chip according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating a package structure according to a first embodiment of the present invention;
FIG. 5 is an equivalent circuit diagram of the present invention;
FIG. 6 is a diagram illustrating a package structure according to a second embodiment of the present invention;
FIG. 7 is a diagram illustrating a package structure according to a third embodiment of the present invention;
in the figure: 1. a semiconductor device chip; 2. a front electrode; 21. a source pad; 22. a gate pad; 3. a cathode metal sheet; 31. a cathode pin; 4. an anode metal sheet; 41. an anode pin; 5. molding the body; 6. a lead wire; 61. a source lead; 62 a gate lead; 7. a conductive metal sheet; r, packaging the electric connection resistor; r1, source electrode electric connection resistance; r2, grid electric connection resistance; s, a source electrode; G. a gate electrode; D. a drain electrode; I. operating current; i isSA source current; i isGA gate current; 11An N + type substrate; 12. an N-type epitaxial layer; 13. a P-doped body region; 14. a trench gate fill region; 15. and (4) a gate oxide layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
First embodiment
Fig. 3 shows a cross-sectional structure of a semiconductor device chip 1 of the present embodiment, which includes an active region, the active region includes a plurality of device cell units connected in parallel, each device cell unit includes an N + -type substrate 11 disposed on a second surface of the active region, and an N-type epitaxial layer 12 disposed on the N + -type substrate 11, a trench is disposed in the N-type epitaxial layer 12, and the trench extends from a first surface of the active region to an inside of the N-type epitaxial layer 4; a trench gate filling region 14 of polycrystalline silicon is arranged in the trench; a gate oxide layer 15 is isolated between the trench gate filling region 14 and the side and bottom walls of the trench; a P doped body region 13 is also arranged on the N-type epitaxial layer 4; the P-doped body region 13 is in contact with the outer side wall of the trench; the depth of the trench gate fill region 14 is greater than the depth of the P-doped body region 13.
The structure of the semiconductor device chip 1 in the present embodiment is shown as an example only; in other embodiments, the semiconductor device chip 1 may have other structures, such as the semiconductor device structure described in patent documents with publication numbers CN211743165U and CN111987170A, which is limited in that the semiconductor device structure includes an active region having a MOS structure whose V is greater than VthBelow 0.7V.
Fig. 1 shows a package structure of an advanced diode in the prior art. Taking a semiconductor device chip 1 with the same structure as an example, in the prior art, a front electrode 2 is arranged on a first surface to short a P-doped body region 13 and a trench gate filling region 14, and an advanced diode is formed after packaging, wherein the forward conduction voltage of the advanced diode is 0.4V.
Fig. 4 shows a package structure of the present embodiment, which includes a semiconductor device chip 1, a cathode metal sheet 3, an anode metal sheet 4, and a plastic package body 5;
a source pad 21 and a gate pad 22 are provided on the first surface of the semiconductor device chip 1; a drain pad is arranged on the second surface of the semiconductor device chip 1; the source pad 21 is electrically connected to the P-doped body region 13; gate pad 22 is electrically connected to trench gate fill region 14; the drain pad is electrically connected to the N + -type substrate 11;
the semiconductor device chip 1 is disposed on the cathode metal sheet 3; the drain pad faces the cathode metal sheet 3 and is bonded; the source pad 21 and the gate pad 22 are bonded to the anode metal sheet 4 through a source lead 61 and a gate lead 62, respectively;
the plastic package body 5 covers the semiconductor device chip 1, the cathode metal sheet 3, the anode metal sheet 4, the source lead 61 and the grid lead 62; one ends of the cathode metal sheet 3 and the anode metal sheet 4 are respectively a cathode pin 31 and an anode pin 41; the cathode lead 31 and the anode lead 41 are exposed outside the plastic package body 5.
Preferably, more than one source lead 61 is provided, so that the current distribution is more uniform and the heat dissipation performance is improved; the area of the source pad 21 is larger than that of the gate pad 22; those skilled in the art can adjust the length, cross-sectional area and number of the source leads 61 as required to adjust the size of the equivalent source electrical connection resistor R1.
Fig. 5 shows an equivalent circuit diagram of the present invention, in contrast to the equivalent circuit diagram of the prior art shown in fig. 2, in the present invention, the source (S) and the gate (G) are not directly shorted but electrically connected through the source lead 61, the anode metal piece 4, and the gate lead 62, wherein the resistance of the anode metal piece 4 is negligible with respect to the source electrical connection resistance R1 and the gate electrical connection resistance R2.
In the forward operation of the present embodiment, the operating current I flows from the anode to the source and the gate through the leads respectively to form a source current ISAnd a gate current IGIf I is equal to IG+ISAnd a gate-source voltage difference VGS＝-IG·R2+ISR1. Due to the gate current IGIs approximately equal to 0 and is far less than the working current I and the source current ISIt can be known that I ≈ ISAnd VGS≈I·R1>0 which can cause the channel to open, thereby reducing the forward conduction voltage VF. In the present embodiment, the forward conduction voltage VFCan be reduced from 0.4V of the prior art to 0.3V. In the reverse operation of this embodiment, similarly, the gate-source voltage difference VGS<0, further promoting the channel to be closed, and reducing the leakage current IR. In summary, the present embodiment further reduces the forward voltage V under the condition of small structural variation and unchanged or better performanceFThe overall performance of the advanced diode is improved.
It should be noted that, in the forward operation of the embodiment of the present invention, the voltage difference between the source and the drain (D) is VSDWhen, VF≈I·R1+VSDThe larger the source electrical connection resistor R1 is, the more the resistance difference loss is to the forward conduction voltage VFThe greater the effect of (c). Therefore, those skilled in the art need to optimize the specific value of the source electrical connection resistor R1 according to the practical application requirements and the performance parameters of the semiconductor device chip 1 itself to achieve a better forward-conducting voltage VF. The skilled person can optimize the preferred resistance under certain conditions by software simulation, which is a common measure of the skilled person and will not be described in detail herein.
Second embodiment
As shown in fig. 6, the present embodiment is different from the first embodiment in that the source pad 21 is bonded to the anode metal sheet 4 through the conductive metal sheet 7. Those skilled in the art can adjust the length, width and thickness of the conductive metal sheet 7 as required to adjust the size of the equivalent source electrical connection resistor R1.
Third embodiment
As shown in fig. 7, the present embodiment is different from the first embodiment in that the source pad 21 and the gate pad 22 are bonded to the anode metal sheet 4 through the conductive metal sheet 7, respectively.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (6)
1. An advanced diode packaging structure with source-grid indirect electric connection is characterized by comprising a semiconductor device chip, a cathode metal sheet, an anode metal sheet and a plastic package body;
a source bonding pad and a grid bonding pad are arranged on the first surface of the semiconductor device chip; a drain electrode bonding pad is arranged on the second surface of the semiconductor device chip; the semiconductor device chip comprises an active region with a MOS structure region; the source electrode and the grid electrode of the semiconductor device chip are not directly short-circuited; when the source bonding pad and the grid bonding pad are directly short-circuited, the semiconductor device chip is an advanced diode,
the semiconductor device chip is arranged on the cathode metal sheet; the drain electrode bonding pad is bonded with the cathode metal sheet; the source electrode bonding pad and the grid electrode bonding pad are respectively bonded with the anode metal sheet through electric connection pieces;
the plastic package body coats the semiconductor device chip, the cathode metal sheet, the anode metal sheet and the electric connecting piece; one end of the cathode metal sheet and one end of the anode metal sheet are respectively a cathode pin and an anode pin; the cathode pin and the anode pin are respectively exposed outside the plastic package body.
2. The advanced diode package structure with indirect source-gate electrical connection of claim 1, wherein the MOS structure region has a threshold voltage VthLess than 0.7V.
3. The advanced diode package structure with indirect source-gate electrical connection of claim 2, wherein the MOS structure region has a threshold voltage VthLess than 0.4V.
4. The advanced diode package structure with indirect source-gate electrical connection of claim 1, wherein the forward conducting voltage V of the advanced diodeFLess than 0.7V.
5. The advanced diode package structure with indirect source-gate electrical connection of claim 1, wherein the electrical connection is a lead or a conductive metal sheet.
6. The advanced diode package structure with indirect source-gate electrical connection of claim 5, wherein the conductive metal sheet is a metal copper sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110177369.XA CN112992834B (en) | 2021-02-09 | 2021-02-09 | Advanced diode packaging structure with indirect electrical connection of source and grid |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110177369.XA CN112992834B (en) | 2021-02-09 | 2021-02-09 | Advanced diode packaging structure with indirect electrical connection of source and grid |
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| CN112992834A true CN112992834A (en) | 2021-06-18 |
| CN112992834B CN112992834B (en) | 2022-02-18 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1453864A (en) * | 2002-04-25 | 2003-11-05 | 台湾通用器材股份有限公司 | Power semiconductor device produced with package in chip size |
| CN102064201A (en) * | 2010-10-22 | 2011-05-18 | 深圳市芯威科技有限公司 | Shallow-slot metal oxide semiconductor diode |
| CN103441151A (en) * | 2013-08-27 | 2013-12-11 | 无锡市芯茂微电子有限公司 | Low forward voltage drop diode |
| CN103972303A (en) * | 2013-01-25 | 2014-08-06 | 三星电子株式会社 | Diode, ESD protection circuit and method of manufacturing the same |
| CN109119487A (en) * | 2018-08-22 | 2019-01-01 | 电子科技大学 | A kind of super barrier diode component |
| US20190296008A1 (en) * | 2018-03-22 | 2019-09-26 | Kabushiki Kaisha Toshiba | Semiconductor device and semiconductor package |
| CN110310944A (en) * | 2019-08-03 | 2019-10-08 | 捷捷半导体有限公司 | A kind of large power semiconductor device with failure open circuit feature |
| CN111433897A (en) * | 2017-12-11 | 2020-07-17 | 罗姆股份有限公司 | Semiconductor rectifier |
-
2021
- 2021-02-09 CN CN202110177369.XA patent/CN112992834B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1453864A (en) * | 2002-04-25 | 2003-11-05 | 台湾通用器材股份有限公司 | Power semiconductor device produced with package in chip size |
| CN102064201A (en) * | 2010-10-22 | 2011-05-18 | 深圳市芯威科技有限公司 | Shallow-slot metal oxide semiconductor diode |
| CN103972303A (en) * | 2013-01-25 | 2014-08-06 | 三星电子株式会社 | Diode, ESD protection circuit and method of manufacturing the same |
| CN103441151A (en) * | 2013-08-27 | 2013-12-11 | 无锡市芯茂微电子有限公司 | Low forward voltage drop diode |
| CN111433897A (en) * | 2017-12-11 | 2020-07-17 | 罗姆股份有限公司 | Semiconductor rectifier |
| US20190296008A1 (en) * | 2018-03-22 | 2019-09-26 | Kabushiki Kaisha Toshiba | Semiconductor device and semiconductor package |
| CN109119487A (en) * | 2018-08-22 | 2019-01-01 | 电子科技大学 | A kind of super barrier diode component |
| CN110310944A (en) * | 2019-08-03 | 2019-10-08 | 捷捷半导体有限公司 | A kind of large power semiconductor device with failure open circuit feature |
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| CN112992834B (en) | 2022-02-18 |
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