CN112992828A

CN112992828A - Packaging structure

Info

Publication number: CN112992828A
Application number: CN202110162317.5A
Authority: CN
Inventors: 周学轩; 范家杰; 王程麒; 王冠人
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2016-12-30
Filing date: 2017-09-01
Publication date: 2021-06-18
Also published as: CN108269745A; CN108269745B

Abstract

The invention provides a packaging structure which comprises a rewiring layer, a welding layer and an electronic element. The rewiring layer is provided with a first wiring area and an adjacent second wiring area, a joint electrode and a test electrode are arranged on the first surface of the rewiring layer, wherein the joint electrode is overlapped with the first wiring area, the test electrode is overlapped with the second wiring area, the welding layer is positioned on the second surface of the rewiring layer and is provided with a plurality of mutually separated conductive pads, and each conductive pad is electrically connected with one of the joint electrode and the test electrode. The redistribution layer further includes a plurality of dielectric layers having a plurality of vias, and a plurality of patterned conductive layers partially disposed in the vias. The bonding electrodes are electrically connected with the corresponding conductive pads by the corresponding patterned conductive layers to form redistribution leads, the testing electrodes are electrically connected with the corresponding conductive pads by the corresponding patterned conductive layers to form testing leads, and the electronic element is electrically connected with the bonding electrodes.

Description

Packaging structure

Filing date, application number and invention creation title of original application

The application is a divisional application of an invention patent application with the application date of 09 month and 01 year 2017, the application number of 201710779909.5 and the name of 'packaging structure and manufacturing method thereof'.

Technical Field

The present invention relates to a package structure and a method for fabricating the same, and more particularly, to a panel-level package structure and a method for fabricating the same.

Background

In the electronic device packaging technology, a fan-out package (FOWLP) is a wafer-level package structure in which an electronic device is fabricated on a wafer and then packaged and diced. However, since the diameter of the common large-sized wafer is only about 300 millimeters (mm), the number of electronic devices that can be simultaneously packaged on the wafer is limited, and the industry still needs to actively develop a technology to replace the wafer-level package.

Furthermore, in the conventional fan-out package structure, the mature technology is to first dispose the electronic device on the carrier such as the wafer, and then dispose the redistribution layer on the electronic device. In order to increase the yield of products, the defective electronic components are generally removed during the manufacturing process, and then the qualified electronic components are used to manufacture the package, and a redistribution layer is formed on the electronic components. However, if defects occur in the subsequent processes, the packaged acceptable electronic components must be discarded together with the whole package body, which results in waste of raw materials and components and increased manufacturing cost.

Disclosure of Invention

The invention aims to: the packaging structure is provided to solve the technical problems in the prior art.

In order to achieve the purpose, the invention adopts the technical scheme that:

a package structure, comprising:

a redistribution layer having a first wiring region and a second wiring region adjacent to the first wiring region;

at least one bonding electrode arranged on a first surface of the redistribution layer; and

at least one test electrode arranged on the first surface;

wherein the bonding electrode overlaps the first wiring region, and the test electrode overlaps the second wiring region.

The package structure, wherein, still include:

a bonding layer on a second surface of the redistribution layer, the second surface being disposed opposite to the first surface, the bonding layer including a plurality of conductive pads separated from each other;

at least one of the conductive pads is electrically connected to one of the bonding electrode and the testing electrode.

The package structure, wherein, still include:

a plurality of solder balls electrically connected to the plurality of conductive pads.

The package structure, wherein, still include:

an electronic component electrically connected to the bonding electrode.

The package structure, wherein, still include:

a bonding material disposed between the electronic component and the bonding electrode.

The package structure, wherein the redistribution layer further includes:

the dielectric layer is provided with a plurality of through holes, and part of the patterned conductive layer is positioned in the through holes.

A package structure, comprising:

a redistribution layer having a first surface, a second surface opposite to the first surface, and at least one sidewall connecting the first surface and the second surface;

at least one bonding electrode disposed on the first surface of the redistribution layer; and

a bonding layer disposed on the second surface of the redistribution layer, the bonding layer including a plurality of conductive pads separated from each other;

wherein the sidewall of the redistribution layer exposes at least one of the plurality of conductive pads.

The package structure, wherein, still include:

an electronic component electrically connected to the bonding electrode.

The package structure, wherein, still include:

The package structure, wherein the redistribution layer further includes:

A method for manufacturing a package structure includes:

providing a substrate having a width of at least 400 millimeters (mm) in either direction;

forming a release layer on the substrate;

forming a patterned soldering layer on the release layer, the soldering layer including a plurality of conductive pads separated from each other;

forming a rewiring layer on the release layer and the plurality of conductive pads, wherein the rewiring layer is provided with a first surface, the first surface is positioned on one side of the rewiring layer relative to the release layer, and the rewiring layer is provided with at least one bonding electrode on the first surface;

bonding at least one electronic element on the first surface of the redistribution layer, wherein the electronic element is electrically connected with the bonding electrode;

forming a sealing adhesive layer on the first surface of the redistribution layer;

performing a separation step to separate the release layer and the substrate from the redistribution layer and the solder layer; and

a solder ball is formed on each of the plurality of pads.

The manufacturing method of the packaging structure further comprises the step of contacting the bonding electrode with a probe to test the redistribution layer after the redistribution layer is formed and before the electronic element is bonded.

The manufacturing method of the packaging structure comprises the step of arranging at least one testing electrode on the first surface of the redistribution layer, wherein the at least one testing electrode is arranged adjacent to the at least one bonding electrode, and at least part of the at least one bonding electrode is overlapped with the electronic element.

The manufacturing method of the packaging structure further comprises the step of respectively contacting the bonding electrode and the testing electrode by using a probe for testing after the redistribution layer is formed and before the electronic element is bonded.

The manufacturing method of the packaging structure further comprises the step of electrically connecting the test electrode by a probe for testing after the electronic element is jointed and before the sealant layer is formed.

In the manufacturing method of the package structure, the at least one test electrode is removed after the release layer and the substrate are separated from the redistribution layer and the solder layer.

The manufacturing method of the packaging structure further comprises a step of performing a cutting process to form at least one packaging structure after the solder balls are formed, wherein the cutting process enables the testing electrode and the part of the rewiring layer provided with the testing electrode to be separated from the packaging structure, and exposes part of the conductive pad in the side wall of the packaging structure.

The manufacturing method of the packaging structure comprises the step of carrying out a cutting process to form at least one packaging structure after the tin balls are formed, wherein the packaging structure comprises a plurality of electronic elements with different or same integrated circuits.

The manufacturing method of the packaging structure comprises the following steps of:

forming a dielectric layer on the release layer;

forming a plurality of vias in the dielectric layer;

forming a conductive layer on the dielectric layer, wherein the conductive layer is filled into the plurality of through holes; and

a patterning process is performed on the conductive layer to form the patterned conductive layer.

Compared with the prior art, the invention has the beneficial effects that: the invention relates to a packaging structure and a manufacturing method thereof, which manufacture a panel-level packaging body (FOPLP) by a RDL-first process and match with a test pad and a test lead of a second wiring area, and can perform individual or integral electrical and functional tests on the RDL, an electronic element joint condition, the test pad and the like at different stages of the process so as to eliminate defective elements in advance in the process or repair defective products so as to avoid the consumption of subsequent processes and materials on the defective elements. The package structure manufactured according to the method of the present invention may have a special structure, for example, in the package structure with the second wiring region reserved, the test wires including the test electrodes may penetrate through the entire redistribution layer, the bottom of the redistribution layer may have the test pads, or the test wires may be exposed in the case of removing the test pads, and in the package structure with the second wiring region cut, the solder layer may be exposed on the sidewall surface of the package structure.

Drawings

Fig. 1 to 7 are schematic process diagrams illustrating a manufacturing method of a package structure according to a first embodiment of the invention.

Fig. 8 to 13 are schematic process diagrams illustrating a manufacturing method of a package structure according to a second embodiment of the invention.

Fig. 14 is a schematic top view of a package structure according to a second embodiment of the invention.

Fig. 15 is a schematic cross-sectional view of a second embodiment of a package structure and a method for fabricating the same according to the present invention.

Fig. 16 is a top view of the package structure shown in fig. 15.

Fig. 17 and fig. 18 are a process diagram and a cross-sectional diagram of another variation of the second embodiment of the package structure and the method for manufacturing the same, respectively.

FIG. 19 is a process diagram illustrating a method for fabricating a package structure according to a third embodiment of the present invention.

Fig. 20 is a flowchart illustrating a method for fabricating a package structure according to the present invention.

Wherein the reference numerals are as follows:

100. 100 ', 200', 200 ″ package structure; a 110 substrate; 112 a release layer; 210 a solder layer; 212 a conductive pad; 214 patterning the conductive layer; 2141 redistribution of conductive lines; 2141' bonding electrodes; 216a dielectric layer; 216a through hole; 218 a bonding material; 220 a test pad; 222 testing the lead; 2221 a test electrode; 230. 2301, 2302 electronic components; 232 bonding pads; 234 a sealant layer; 240 solder balls; 300 testing the machine; 302 a conductive wire; 310. 312, 314 probes; RDL rewiring layer; l1 first rewiring layer; l2 second rewiring layer; l3 third rewiring layer; d1, D2 cut line; r1 first wiring region; r2 second wiring region; s1 first surface; s2 second surface; SL1, SL2, SL3, SL4 side walls; PR photoresist layer; UT packaging structure unit; s102 to S118, and S202 to S206.

Detailed Description

In order to make those skilled in the art understand the present invention, the following embodiments are specifically illustrated and described in detail with reference to the accompanying drawings. It should be noted that the drawings are simplified schematic diagrams, and therefore, only the elements and combinations related to the present invention are shown to provide a clearer description of the basic architecture or implementation method of the present invention, and the actual elements and layout may be more complicated. In addition, for convenience of description, the components shown in the drawings are not necessarily drawn to scale, and the actual implementation numbers, shapes and sizes may be adjusted according to design requirements.

Furthermore, the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, steps, operations, and/or elements, but do not preclude the presence or addition of one or more other features, regions, steps, operations, elements, and/or groups thereof. When an element such as a layer or region is referred to as being "on" or extending "onto" another element (or variations thereof), it can be directly on or extend directly onto the other element or intervening elements may also be present. On the other hand, when an element is referred to as being "directly on" or extending "directly onto" another element (or variations thereof), there are no intervening elements present between the two. Also, when an element is referred to as being "coupled" to another element (or variations thereof), it can be directly connected to the other element or be indirectly connected (e.g., electrically connected) to the other element through one or more elements.

It is understood that the several embodiments recited below may be combined, rearranged or mixed in order to achieve additional embodiments without departing from the spirit of the invention.

Referring to fig. 1 to 7, fig. 1 to 7 are schematic process diagrams illustrating a manufacturing method of a package structure according to a first embodiment of the invention, and show the structure of each element in a cross-sectional view. As shown in fig. 1, the method for fabricating the package structure of the present invention includes providing a substrate 110, in this embodiment, the width of the substrate 110 in any direction is at least 400 millimeters (mm), and the substrate is a rectangular or square substrate. For example, the substrate 110 is a glass substrate having a length of 650 to 2500 millimeters (mm) and a width of 550 to 2200 millimeters (mm), such as: a substrate of 550 mm (length) X650 mm (width) or a substrate of 600 mm (length) X720 mm (width), but not limited thereto, the substrate 110 may have other dimensions larger than 550 mm (mm), wherein the substrate 110 of the embodiment has dimensions of 600 mm X720 mm (mm), but not limited thereto. Next, a release layer 112 is formed on the substrate 110, and then a patterned solder layer 210 is formed on the release layer 112, wherein the solder layer 210 includes a plurality of conductive pads 212 separated from each other. The patterned solder layer 210 is formed by, for example, forming a conductive layer (not shown) on the release layer 112, which includes a metal material, and then performing a patterning process such as photolithography and etching on the conductive layer to form the conductive pad 212.

Referring to fig. 2, a redistribution layer RDL is formed on the release layer 112 and the conductive pad 212, wherein the redistribution layer RDL includes at least one patterned conductive layer 214, at least one dielectric layer 216 and at least one via hole 216a, that is, the redistribution layer RDL includes a plurality of dielectric layers 216 and a plurality of corresponding patterned conductive layers 214 and via holes 216a, so as to redistribute the lines. For example, as shown in fig. 2 of the present embodiment, the redistribution layer RDL may have a first redistribution layer L1, a second redistribution layer L2, and a third redistribution layer L3, and the first redistribution layer L1, the second redistribution layer L2, and the third redistribution layer L3 respectively have a patterned conductive layer 214, a dielectric layer 216, and a plurality of vias 216a penetrating through the dielectric layer 216 and connecting the patterned conductive layer 214, but not limited thereto. The step of forming the first redistribution layer L1 includes forming a first dielectric layer 216 on the release layer 112, forming one or more through holes 216a in the first dielectric layer 216 to expose the conductive pads 212, forming a conductive layer (not shown) on the first dielectric layer 216, filling the conductive layer into the through holes 216a to contact the conductive pads 212, and patterning the conductive layer to form a patterned conductive layer 214, wherein the patterned conductive layer 214 includes a plurality of redistribution wires 2141, and each of the conductive pads 212 of the present embodiment corresponds to and is electrically connected to one of the redistribution wires 2141, but not limited thereto. Then, a similar process is used to fabricate the second redistribution layer L2, such as forming a second dielectric layer 216 on the first redistribution layer L1, forming a plurality of through holes 216a in the second dielectric layer 216, and exposing the redistribution traces 2141 on the surface of the first redistribution layer L1. Then, a second conductive layer (not shown) is formed on the second dielectric layer 216, so that the second conductive layer fills the through hole 216a of the second dielectric layer 216, and then the second conductive layer is patterned, thereby forming the patterned conductive layer 214 of the second redistribution layer L2, which also includes a plurality of redistribution wires 2141, and is in contact with and electrically connected to the corresponding redistribution wires 2141 of the first redistribution layer L1 through the through hole 216a of the second redistribution layer L2. The process of the third redistribution layer L3 is similar and will not be described again. As shown in fig. 2, the redistribution layer RDL has a first surface S1 and a second surface S2. The first surface S1 is located on a side of the redistribution layer RDL opposite to the release layer 112, the second surface S2 is a surface of the redistribution layer RDL opposite to the first surface S1, that is, the second surface S2 is disposed opposite to the first surface S1, that is, the redistribution layer RDL is in contact with the release layer 112, and the solder layer 210 is located on the second surface S2 of the redistribution layer RDL. It should be noted that, in the present embodiment, the uppermost third redistribution layer L3 may be used to bond with an electronic device disposed later, so the third redistribution layer L3 may be regarded as a bonding layer, and the redistribution wire 2141 of the third redistribution layer L3 has at least one bonding electrode 2141 ', the bonding electrode 2141' is exposed on the first surface S1 of the redistribution layer RDL, and may also be regarded as a bonding electrode disposed on the first surface S1 of the redistribution layer RDL for bonding with an electronic device, and the electronic device may be a chip (chip), a processor (processor), a die (die), an Integrated Circuit (IC) or other devices related to active/passive devices. In the present embodiment, at least one conductive pad 212 is electrically connected to one of the bonding electrodes 2141'.

Referring to fig. 3, after forming the redistribution layer RDL and before bonding the electronic device, a first stage test may be optionally performed: the bonding electrode 2141' is directly contacted by the probe 310 to perform a short circuit test on the redistribution layer RDL. For example, a testing machine 300 including a plurality of probes 310 is provided, wherein each probe 310 is electrically connected to the testing machine 300 through a conductive wire 302, and each bonding electrode 2141' is respectively contacted with one probe 310 to electrically connect the two, and then the testing machine 300 is used to respectively perform a short circuit test on each redistribution conductive wire 2141 of the redistribution layer RDL to determine whether the redistribution layer RDL is defective.

Since the invention is a RDL-first (RDL-first) process, i.e. a RDL is formed on the substrate 110 first, and then the electronic component is bonded on the RDL, the RDL can be tested before the electronic component is bonded on the RDL. By performing the short circuit test, the manufacturing yield of the RDL of the redistribution layer can be obtained, and the RDL of the redistribution layer can be repaired or the RDL of the redistribution layer with poor yield can be eliminated. And then, according to the short circuit test result, performing subsequent manufacturing on the detected RDL of the redistribution layer, so that the condition that the product qualification rate of the finally manufactured packaging structure is reduced due to the defect of the RDL of the redistribution layer is eliminated, and further the overall manufacturing qualification rate of the packaging structure is improved and the waste of subsequent materials is reduced.

Referring to fig. 4, after the first-stage short circuit test is performed on the RDL, at least one

electronic element

2301, 2302 is bonded to the first surface S1 of the RDL. In the present embodiment, the bonding electrode 2141 ' is connected to the

electronic element

2301, 2302 via at least one bonding pad 232, and the bonding electrode 2141 ' may have a bonding material 218 on the surface thereof and disposed between the

electronic element

2301, 2302 and the bonding electrode 2141 '. In detail, before the

electronic devices

2301, 2302 are bonded, the bonding material 218 may be formed on the bonding electrodes 2141 ', and then the bonding pads 232 of the

electronic devices

2301, 2302 are bonded to the bonding material 218 (e.g., in a eutectic manner) to electrically connect to the bonding electrodes 2141', wherein the bonding material 218 is, for example, tin, nickel gold, or nickel-palladium gold, and the bonding pads 232 include, for example, but not limited to, tin, nickel, gold, or an alloy. For example, in other embodiments, solder balls may be used to bond the

electronic devices

2301, 2302 and the RDL. It should be noted that the present embodiment is exemplified by providing the

electronic devices

2301 and 2302 with two different integrated circuits, to show that the bonding of the electronic devices on the RDL is not limited to one type of electronic device in the process, in other words, the bonded electronic devices may have the same or different integrated circuits, and one or more types of electronic devices and any number of electronic devices may be simultaneously bonded in the process according to the product requirements.

Referring to fig. 5, an adhesive layer 234 is formed on the RDL first surface S1, in the embodiment, the adhesive layer 234 is mainly disposed outside the

electronic elements

2301, 2302 and substantially does not cover the upper surfaces of the

electronic elements

2301, 2302, but the invention is not limited thereto, and in a variation, the adhesive layer 234 may cover the upper surfaces of the

electronic elements

2301, 2302. Next, a separation step is performed to separate the releasing layer 112 from the substrate 110 by the weight wiring layer RDL and the soldering layer 210, so as to expose the conductive pad 212 on the second surface S2 of the weight wiring layer RDL. For example, since the release layer 112 has a temporary adhesion effect, the separation step can be performed by irradiating the release layer 112 with laser light to debond the release layer 112, and then peeling the release layer 112 and the substrate 110 from the RDL, but not limited thereto. After the separation process, a cleaning process can be optionally performed.

Then, as shown in fig. 6, the second stage test can be selectively performed to perform an open circuit test, a short circuit test and a function test on the package body connected with the

electronic devices

2301, 2302. The second stage testing may include performing the above-described testing by contacting the exposed conductive pad 212 with a probe 310. In detail, the testing machine 300 can be used to electrically connect a plurality of probes 310 through the wires 302, and the probes 310 are respectively contacted and electrically connected to the conductive pads 212, so as to perform the testing. It should be noted that the manufacturing method of the package structure of the present embodiment can test the overall electrical yield after the redistribution layer RDL is bonded to the electronic element 2301 and the electronic element 2302 before the solder balls are bonded to the conductive pads 212, so as to selectively repair the package or eliminate the defective product, thereby avoiding wasting the process and material on the defective product.

Referring to fig. 7, after the second stage of testing, a solder ball 240 is formed on each of the conductive pads 212. Then, a cutting process is performed to form at least one package structure, wherein the cutting process can be performed by laser cutting, wheel cutting or impact cutting (punch), but not limited thereto. The cutting process may be performed at a selected position according to the requirement, such as cutting along the cutting line D1 or the cutting line D2, or cutting along the cutting lines D1 and D2, but not limited thereto. As shown in fig. 7, if the package structure 100 is cut along the cut line D1, the package structure 100 including both the electronic device 2301 and the electronic device 2302 is manufactured, and if the package structure 100 'is cut along the cut line D1 and the cut line D2, the package structure 100' includes only one electronic device 2301 or one electronic device 2302. In other words, the package structures 100, 100 'of the present invention may have any number of electronic components, and the electronic components in a single package structure 100, 100' may be the same or different from each other.

The package structure and the manufacturing method thereof of the present invention are not limited to the above embodiments. Other embodiments or variations of the present invention will be further disclosed, and various embodiments can be mixed and matched with each other, however, in order to simplify the description and to make the differences between various embodiments or variations obvious, the same components are labeled with the same reference numerals hereinafter, and repeated descriptions are omitted.

Referring to fig. 8 to 13, fig. 8 to 13 are schematic process diagrams illustrating a manufacturing method of a package structure according to a second embodiment of the invention. As shown in fig. 8, similar to the first embodiment of the invention, in the second embodiment of the package structure manufacturing method, the release layer 112 and the redistribution layer RDL are sequentially formed on the substrate 110, however, the difference between the present embodiment and the first embodiment lies in that the first wiring region R1 and the second wiring region R2 of each package unit UT are defined on the substrate 110 according to the range of each package to be manufactured, wherein the second wiring region R2 is disposed outside the first wiring region R1, and the conductive pad 212, a portion of the dielectric layer 216 and the redistribution wire 2141 are located in the first wiring region R1. It should be noted that the redistribution layer RDL in this embodiment may also be regarded as having a first wiring region R1 and a second wiring region R2. In addition, in the embodiment, the second wiring region R2 is disposed at the periphery of the first wiring region R1 and surrounds the first wiring region R1, but not limited thereto. In addition, when the bonding layer 210 is formed, the test pad 220 is formed at the second wiring region R2, and is directly connected to and in contact with one of the conductive pads 212 to be electrically connected to each other. Furthermore, when the patterned conductive layer 214 of the redistribution layer RDL is fabricated, the test wires 222 are fabricated in the second wiring region R2 at the same time, and the test wires 222 penetrate through the entire redistribution layer RDL and have at least one test electrode 2221 exposed on the first surface S1 of the redistribution layer RDL, and are correspondingly and electrically connected to the test pads 220. In other words, the test electrode 2221 of the present embodiment is disposed on the first surface S1 of the redistribution layer RDL, and overlaps the second wiring region R2, and the bonding electrode 2141' overlaps the first wiring region R1. In the present embodiment, at least one conductive pad 212 is electrically connected to one of the bonding electrode 2141' and the testing electrode 2221.

After the RDL is fabricated and before the electronic components are bonded, a first stage test may be optionally performed to test the RDL. The testing machine 300 is in contact with and electrically connected to the bonding electrodes 2141' through one set of probes 310, and in contact with and electrically connected to the testing electrodes 2221 through another set of probes 312, so as to perform short circuit testing and open circuit testing. Depending on the requirements of different processes and the design of the testing tool 300, the testing tool 300 can test a single package structure unit UT, or simultaneously test a plurality of package structure units UT. It should be noted that, in the embodiment, each package structure unit UT has the second wiring region R2, and the second wiring region R2 is provided with the test pads 220 and the test wires 222 including the test electrodes 2221, so that the

probes

310 and 312 of the tester 300 can be used to perform a complete open circuit test on each set of wires in the redistribution layer RDL, thereby effectively detecting the conductive and electrical effects of the wires. Furthermore, the single package structure unit UT is not limited to only one test pad 220 and one test lead 222, and for example, a plurality of test leads 222 and test electrodes 2221 corresponding to each redistribution lead 2141 may be included at the same time, so as to test each redistribution lead 2141 in the first-stage test. Similar to the first embodiment, the invention is a redistribution layer first-pass (RDL-first) process, which is performed before the electronic device is bonded on the RDL, so as to obtain the yield of the RDL, thereby eliminating the defective package structure unit UT and avoiding the waste of the subsequent processes and materials.

Referring to fig. 9, at least one electronic device 230 is bonded to the first surface S1 of the redistribution layer RDL and is connected to the corresponding bonding electrode 2141' through at least one bonding pad 232 of the electronic device 230. Each package structure unit UT may have one or more identical or different electronic components 230, and only one electronic component 230 is illustrated as a representative example in the present embodiment. Then, as shown in fig. 10, after the electronic component 230 is bonded and before the sealant layer 234 is formed, a second stage test is performed to perform a short circuit test, an open circuit test and a functional test with the probe 312 passing through the test wire 222 including the test electrode 2221. In detail, the testing machine 300 can directly contact the bonding material 218 on the testing electrode 2221 through the probe 312 to electrically connect to the testing wire 222 for testing. It should be noted that, in this stage of testing, before the formation of the adhesive layer 234, the electrical yield of the redistribution layer RDL after being bonded to the electronic element 230 may be tested, for example, by using a functional test to confirm the electrical operation effect of each redistribution wire 2141 in the electronic element 230 and the redistribution layer RDL, so as to eliminate the package structure unit UT with poor yield.

Referring to fig. 11, after the electronic component 230 is bonded, an adhesive layer 234 is formed on the first surface S1 of the redistribution layer RDL, and then a separation step is performed to separate the release layer 112 and the substrate 110 from the redistribution layer RDL and the solder layer 210, for example, the release layer 112 is debonded, and then the release layer 112 and the substrate 110 are removed by peeling, but not limited thereto. Then, the third stage test can be selectively performed by using the testing machine 300 to contact each testing pad 220 or the conducting pad 212 with the probe 314 for performing the short circuit test, the open circuit test and the functional test. In this stage, the electrical performance of the redistribution layer RDL and the electronic device 230 after bonding can be tested before the solder balls 240 are formed on the conductive pads 212, so as to know the yield of the whole package structure unit UT.

Referring to fig. 12 and fig. 13, a solder ball 240 is formed on each of the conductive pads 212. Then, a dicing process is performed to form at least one package structure 200. Wherein, the cutting process can select the cutting position according to the requirement. In the present embodiment, a dicing process is performed at the position of the dicing line D1, such that a portion of the redistribution layer RDL provided with the test electrodes 2221 or the test wires 222 and the test pads 220 are separated from the package structure 200, that is, the second wiring region R2 is cut away to leave the first wiring region R1, so as to form at least one package structure 200, as shown in fig. 13. It should be noted that, since the test pad 220 is removed during the cutting process, the conductive pad 212 connected to the test pad 220 is exposed to the sidewalls SL1 and SL2 of the package structure 200, i.e., the exposed solder layer 210 is visible from the surfaces of the sidewalls SL1 and SL2 of the package structure 200.

Referring to fig. 14, fig. 14 is a schematic top view of a package structure 200 according to a second embodiment of the present invention, in which case (a), case (B) and case (C) respectively show the exposure of the solder layer 210 in three variations. As mentioned above, after the second wiring region R2 is cut along the cutting line D1, at least one of the conductive pads 212 is exposed on at least one sidewall surface of the redistribution layer RDL, and the positions and the number of the conductive pads 212 exposed on the sidewall of the redistribution layer RDL are substantially related to the designed positions of the test wires 222 (including the test electrodes 2221) and the test pads 220 in the original second wiring region R2. In the example (a) of fig. 14, the conductive pad 212 or the solder layer 210 is exposed by the left and right sidewalls SL1 and SL2 (or lateral sidewalls) of the package structure 200; in the example (B), the solder layer 210 is exposed to the left and right sidewalls SL1, SL2 and the upper and lower sidewalls SL3, SL4 (or longitudinal sidewalls) of the package structure 200, wherein a portion of the conductive pad 212 extends from the lateral sidewall to the longitudinal sidewall; in example (C) of fig. 14, the conductive pad 212 is exposed only to the surfaces of the upper and lower sidewalls SL3, SL 4. It should be noted that the position where the solder layer 210 is exposed is not limited to fig. 14, for example, the conductive pad 212 may not be exposed to the longitudinal sidewall or the lateral sidewall in a symmetrical manner, or may be exposed to only one surface of the sidewalls SL1, SL2, SL3, and SL 4. Moreover, in order to highlight the exposed positions of the conductive pads 212, the conductive pads 212 shown in fig. 14 protrude from the sidewalls SL1, SL2, SL3, and SL4, however, actually, the sidewalls SL1, SL2, SL3, and SL4 of the package structure 200 manufactured by the manufacturing method of the present invention should have smooth surfaces, that is, the exposed solder layers 210 are substantially aligned with the surfaces of the sidewalls SL1, SL2, SL3, and SL4, respectively.

Referring to fig. 15 and 16, fig. 15 is a schematic cross-sectional view illustrating a variation of the package structure and the method of fabricating the same according to the second embodiment of the present invention, and fig. 16 is a schematic top view illustrating the package structure shown in fig. 15. In this variation, a cutting process is performed by the cutting line D2 of fig. 12, thereby forming the package structure 200' shown in fig. 15. Since the dicing process of this variation does not cut the second wiring region R2, the package structure 200 ' still retains the test wires 222 (including the test electrodes 2221) and the test pads 220, in which case the solder layer 210 may not be exposed on the surface of the sidewalls (e.g., sidewalls SL1, SL2) of the package structure 200 ', however, in some cases, the solder layer 210 may still be exposed on the surface of the sidewalls of the package structure 200 '. It should be noted that although the test electrode 2221 should not be seen from the top view of the package structure 200', to show the position of the test electrode 2221 relative to the first wiring region R1, fig. 16 still illustrates the test electrode 2221, which is located in the second wiring region R2 and is disposed around the first wiring region R1, and the electronic component 230 is disposed in the first wiring region R1.

As can be seen from the second embodiment and the variations thereof, the package structure manufactured by the method of manufacturing a package structure of the present invention may include both the first wiring area and the second wiring area, or only the first wiring area, depending on the product requirements.

Referring to fig. 17 and 18, fig. 17 and 18 are a process schematic view and a cross-sectional view of another variation of the package structure and the method for fabricating the same according to the second embodiment of the present invention, wherein fig. 17 is continued to fig. 11. As shown in fig. 17, after removing the release layer 112 and the substrate 110, a step of removing the test pad 220 may be further included. The method of removing the test pad 220 is exemplified by performing a photolithography and etching process, such as covering the first wiring region R1 with the patterned photoresist layer PR and exposing the test pad 220 of the second wiring region R2, and then performing an etching process on the test pad 220 to remove the exposed test pad 220, but not limited thereto. Thereafter, a solder ball 240 is formed on each of the conductive pads 212, and a cutting process is performed along the cutting line D2 to form the package structure 200 ", as shown in fig. 18. It is noted that in this variation, the test wires 222 penetrate through the entire redistribution layer RDL and are exposed at the bottom of the package structure 200 ″, i.e., the second surface S2 of the redistribution layer RDL. In the third stage of testing, the probe 314 may scratch or generate a groove on the surface of the test pad 220 when contacting the test pad 220 for short circuit testing, open circuit testing and functional testing, so that the bottom of the package structure 200 ″ can be made more beautiful by removing the test pad 220.

Referring to fig. 19, fig. 19 is a process diagram of a method for fabricating a package structure according to a third embodiment of the invention. The difference between the present embodiment and the second embodiment is that fig. 19 only illustrates one package structure unit, wherein three or more conductive pads 212 and corresponding redistribution wires 2141 are disposed in the first wiring region R1, and not every conductive pad 212 is connected to one test pad 220. In addition, in the first stage test, the probes 310 may be respectively brought into contact with and electrically connected to the bonding electrodes 2141', and the probes 312 may be simultaneously brought into contact with and electrically connected to the testing electrodes 2221, so as to perform a short circuit test and an open circuit test.

As can be seen from the above, the method for fabricating the package structure of the present invention mainly includes the steps shown in fig. 20, which are described below.

Step S102: a substrate is provided, wherein the substrate has a width in either direction of at least 400 millimeters (mm).

Step S104: a release layer is formed on the substrate.

Step S106: a patterned solder layer including a plurality of conductive pads separated from each other is formed on the release layer, and in some embodiments, the solder layer further includes a test pad disposed on the second wiring region.

Step S108: and forming a rewiring layer on the release layer and the conductive pad, wherein the rewiring layer comprises at least one dielectric layer, at least one patterned conductive layer and at least one through hole, and the through hole penetrates through the dielectric layer and is connected with the patterned conductive layer. The patterned conductive layer includes redistribution traces and bonding electrodes, and optionally includes test traces or test electrodes disposed in the second wiring region and electrically connected to the corresponding test pads.

Step S202: after the redistribution layer is formed and before the electronic element is bonded, the bonding electrode and the test electrode are selectively contacted with a probe respectively to perform a short/open test.

Step S110: at least one electronic component is bonded to the first surface of the redistribution layer.

Step S204: short/open/functional testing is performed selectively with the probe passing through the test electrode or test lead.

Step S112: and forming a sealing adhesive layer on the first surface of the rewiring layer.

Step S114: and a separation step is carried out to separate the substrate self-weight wiring layer and the welding layer from the release layer.

Step S206: the test pads are selectively contacted with probes for short/open/functional testing.

Step S116: the test pad is selectively removed.

Step S118: solder balls are respectively formed on the conductive pads. Then, a cutting process can be selectively performed to cut the package body into a desired size according to the product requirements, so as to form the package structure.

In summary, the package structure and the manufacturing method thereof of the present invention use the RDL-first process to manufacture the panel level package (FOPLP), and the test pads and the test wires in the second wiring area, so that the RDL, the electronic device, the test pads, and the like can be individually or integrally tested for electrical and functional properties at different stages of the manufacturing process, so as to eliminate the defective device in advance during the manufacturing process, or repair the defective device, thereby avoiding the consumption of the subsequent process and material on the defective device. The package structure manufactured according to the method of the present invention may have a special structure, for example, in the package structure with the second wiring region reserved, the test wires including the test electrodes may penetrate through the entire redistribution layer, the bottom of the redistribution layer may have the test pads, or the test wires may be exposed in the case of removing the test pads, and in the package structure with the second wiring region cut, the solder layer may be exposed on the sidewall surface of the package structure. It should be noted that the package structure provided by the present invention can be applied to electronic device packages with high-density pins, and the application range includes single electronic device modules, multiple electronic device stacked modules, or other suitable package structures.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A package structure, comprising:

a redistribution layer having a first surface, a second surface opposite to the first surface, and a sidewall connecting the first surface and the second surface;

at least one bonding electrode disposed on the first surface of the redistribution layer and protruding from the first surface of the redistribution layer;

an electronic element electrically connected to the bonding electrode; and

the sealing adhesive layer is formed on the first surface of the redistribution layer and directly contacts the first surface, and the sealing adhesive layer is arranged on the outer side of the electronic element;

2. The package structure of claim 1, further comprising:

3. The package structure of claim 1, further comprising:

4. The package structure of claim 1, wherein the redistribution layer further comprises:

5. The package structure of claim 1, wherein the sidewall of the redistribution layer exposes a plurality of the plurality of conductive pads.