CN112992804A - Semiconductor package device and method of manufacturing the same - Google Patents

Semiconductor package device and method of manufacturing the same Download PDF

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Publication number
CN112992804A
CN112992804A CN202110095169.XA CN202110095169A CN112992804A CN 112992804 A CN112992804 A CN 112992804A CN 202110095169 A CN202110095169 A CN 202110095169A CN 112992804 A CN112992804 A CN 112992804A
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fan
chip
layer
out layer
semiconductor package
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吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor packaging device comprises a first chip and a circuit layer; the first chip is positioned on the circuit layer, and the active surface of the first chip faces the circuit layer; the semiconductor packaging device defines a stress neutral region, and the corner of the active surface of the first chip is close to the stress neutral region. The semiconductor packaging device reduces the stress borne by the stress concentration point of the first chip, further reduces the extrusion effect of the corners of the first chip on surrounding materials (such as packaging materials), avoids the corresponding structural fracture and is beneficial to improving the product yield.

Description

Semiconductor package device and method of manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductor packaging devices, and more particularly, to a semiconductor packaging device and a method of manufacturing the same.
Background
The FOCoS (Fan Out Chip on Substrate) packaging technology is implemented by using Fan-Out composite chips on a typical ball grid array Substrate. It can provide a lower cost solution with practically better electrical and thermal performance than silicon interposer structures.
In the FOCoS packaging structure, due to different thermal expansion systems of different materials, the deformation is different in size when the temperature changes, so that the packaging structure is warped and stress is generated inside the packaging structure. The existing FOCoS packaging structure has the problem that the yield of products is reduced due to structural fracture caused by stress.
Disclosure of Invention
The present disclosure provides a semiconductor package device and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package device including a first chip and a wiring layer;
the first chip is positioned on the circuit layer, and the active surface of the first chip faces the circuit layer;
the semiconductor packaging device is defined with a stress neutral area, and the corner of the active surface of the first chip is close to the stress neutral area.
In some optional embodiments, the semiconductor package device further includes a packaging material covering the first chip.
In some alternative embodiments, the distance between the stress neutral region and the bottom surface of the semiconductor package device is determined by the following formula (1):
C＝A·[E1(v1+y·s)+E2(v2-y·s)]formula (1)
Wherein C is a distance between the stress neutral region and the bottom surface of the semiconductor package device, A is a predetermined constant, and E is1Is the Young's modulus of the first fan-out layer, E2Is the Young's modulus of the packaging material, s is the area of the first fan-out layer, y is the thickness of the first fan-out layer, v1Is a volume ratio of the first fan-out layer to the semiconductor package device, v2Is the volume ratio of the packaging material to the semiconductor packaging device.
In some alternative embodiments, the routing layer includes a main fan-out layer and a first fan-out layer located on the main fan-out layer, an upper surface of the first fan-out layer being closer to the stress neutral zone than the upper surface of the main fan-out layer, the first chip being located on the main first fan-out layer.
In some alternative embodiments, the second chip is located on the main fan-out layer.
In some optional embodiments, the semiconductor package device further comprises a second fan-out layer located on the main fan-out layer, the second fan-out layer and the first fan-out layer are located on the same side of the main fan-out layer, and the second chip is located on the second fan-out layer.
In some alternative embodiments, corners of the active surface of the second chip are proximate to the stress neutral region.
In some optional embodiments, the stress neutral region is located near a middle position of the semiconductor package device in a thickness direction.
In some optional embodiments, the semiconductor package device further includes a second chip on the wiring layer.
In some alternative embodiments, corners of the active surface of the second chip are proximate to the stress neutral region.
In some optional embodiments, the first chip is a high bandwidth memory chip and the second chip is an application specific integrated circuit chip.
In some optional embodiments, the circuit layer comprises at least two dielectric layers, and at least one of the dielectric layers has a different thickness from the other dielectric layers.
In some optional embodiments, the line layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer has a thickness greater than a thickness of the second dielectric layer, and the second dielectric layer is closer to the first chip than the first dielectric layer.
In some alternative embodiments, an underfill material is disposed between the first chip and the wiring layer.
In some alternative embodiments, the underfill material is filled by molding or capillary means.
In some optional embodiments, the connection between the first chip and the circuit layer is at least one of a through silicon via connection, a copper pillar connection, a flexible circuit board connection, and a wire connection.
In some optional embodiments, a surface of the encapsulant is provided with a heat dissipation layer.
In some alternative embodiments, the bottom surface of the wiring layer is provided with an electrical connector.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:
forming a main fan-out layer on a carrier through repeated processes of photoetching, electroplating and etching;
forming a first fan-out layer on the main fan-out layer through repeated processes of photoetching, electroplating and etching, wherein the main fan-out layer and the first fan-out layer jointly form a circuit layer;
electrically connecting a first chip to the first fan-out layer, wherein an active surface of the first chip faces the wiring layer;
disposing an underfill material between the first chip and the first fan-out layer;
and molding the main fan-out layer to obtain the semiconductor packaging device, wherein the semiconductor packaging device defines a stress neutral region, and the corner of the active surface of the first chip is close to the stress neutral region. .
In some optional embodiments, the forming a first fan-out layer on the main fan-out layer by a repeated process of photolithography, electroplating, and etching includes:
placing a barrier layer on the main fan-out layer, wherein the barrier layer has a cavity;
and forming the first fan-out layer in the cavity of the barrier layer through repeated processes of photoetching, electroplating and etching.
In some optional embodiments, the method further comprises, prior to the molding over the main fan-out layer:
connecting a second chip to the main fan-out layer;
an underfill material is disposed between the second chip and the main fan-out layer.
In some optional embodiments, after the molding over the main fan-out layer, the method further comprises:
and arranging a heat dissipation layer on the surface of the packaging material of the semiconductor packaging device.
In some optional embodiments, after the molding over the main fan-out layer, the method further comprises:
and arranging an electric connector on the outer surface of the circuit layer.
In a third aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:
forming a circuit layer on the carrier through repeated processes of photoetching, electroplating and etching;
connecting a first chip and a second chip to the circuit layers respectively;
respectively arranging an underfill material between the first chip and the circuit layer and between the second chip and the circuit layer;
and performing molding on the circuit layer to obtain the semiconductor packaging device.
In the semiconductor package device and the manufacturing method thereof provided by the embodiment of the disclosure, the corner of the active surface of the first chip is disposed at a position close to the stress neutral region, so that the stress applied to the stress concentration point of the first chip is reduced, the extrusion effect of the corner of the first chip on surrounding materials (such as a package material) is further reduced, the corresponding structural fracture is avoided, and the product yield is improved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic illustration of a fracture phenomenon in the prior art;
fig. 2 is a first schematic diagram of a semiconductor package device according to an embodiment of the present invention;
fig. 3 is a force diagram of a semiconductor package device according to an embodiment of the present invention;
fig. 4 is a second schematic diagram of a semiconductor package device according to an embodiment of the present invention;
fig. 5 is a schematic diagram of various connection manners of a first chip and a wiring layer in a semiconductor package device according to an embodiment of the present invention;
fig. 6 is a schematic view showing a manner of disposing a silicon dummy layer in a semiconductor package device according to an embodiment of the present invention;
fig. 7 is a schematic diagram of various chip arrangements in a semiconductor package device according to an embodiment of the present invention;
fig. 8-15 are schematic diagrams of a manufacturing process of a semiconductor package device according to an embodiment of the present invention.
Description of the symbols:
100 first chip 100a first chip
100b second first chip 200 second chip
300 line level 301 main fan-out layer
302 first fan-out layer 303 first dielectric layer
304 second dielectric layer 305 third dielectric layer
306 fourth dielectric layer 400 encapsulant
500 silicon dummy layer 600 heat sink layer
700 electrical connector 900 underfill material
10 carrier 11 barrier layer
12 bonding head 101 through-silicon-via
102 copper post 103 flexible circuit board
104 connecting line
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a schematic diagram of a fracture phenomenon in the prior art. As shown in fig. 1, the first chip 100 and the second chip 200 are disposed on the circuit layer 300, and the package material 400 is disposed around the first chip and the second chip. Due to the fact that thermal expansion systems of different materials are different, deformation is different in size when temperature changes, and therefore the packaging structure is warped and stress is generated inside the packaging structure. The stress may cause the corners of the first chip 100 to press the encapsulant 400, thereby causing the broken encapsulant 400 to break. The fracture site is shown in fig. 1 by white dashed circles.
Fig. 2 is a first schematic diagram of a semiconductor package device according to an embodiment of the present invention. The semiconductor package device includes a first chip 100 and a wiring layer 300. The first chip 100 is located on the circuit layer 300, and an active surface of the first chip 100 faces the circuit layer 300. Here, the active surface is a surface of the chip for external connection, for example, in fig. 2, the active surface of the first chip 100 is a lower surface.
In the present embodiment, the semiconductor package device defines a stress neutral region 800, and the stress neutral region 800 is shown in fig. 2 by a dotted line. Here, the stress neutral region refers to a region where the stress is zero in the semiconductor package device. Referring to fig. 3, an arrow on the right side of the semiconductor package device in fig. 3 represents a corresponding stress, wherein a direction of the arrow represents a direction of the stress, and a length of the line segment represents a magnitude of the stress. In the example of fig. 3, the stress inside the semiconductor package device gradually decreases to the left and then gradually increases to the right in the top-down direction. It is easily understood that during the continuous variation of the stress, the semiconductor package device shown in fig. 3 has a horizontal plane corresponding to zero stress, which is a stress neutral region.
In the present embodiment, the corners of the active surface of the first chip 100 are close to the stress neutral region 800. In one example, a distance from a corner of the active surface of the first chip 100 to the stress neutral region 800 is smaller than a distance from a corner of the active surface of the first chip 100 to the bottom surface of the wiring layer 300. In another example, the distance from the corner of the active surface of the first chip 100 to the stress neutral region 800 is less than a predetermined value, such as 5 microns, 10 microns, or 20 microns.
In one example, the semiconductor package device further includes a package 400 covering the first chip 100.
In one example, the wiring layer 300 includes a main fan-out layer 301 and a first fan-out layer 302 located on the main fan-out layer 301, an upper surface of the first fan-out layer 302 being closer to the stress neutral zone 800 than an upper surface of the main fan-out layer 301. The first chip 100 is located on the first fan-out layer 302.
As shown in fig. 2, the first fan-out layer 302 is located above the main fan-out layer 301, and the first chip 100 is located above the first fan-out layer 302. The first fan-out layer 302 is opposite the first chip 100, with the widths being close together. The width of the first fan-out layer 302 is less than the width of the main fan-out layer 301.
In one example, the distance of the stress neutral region from the bottom surface of the semiconductor package is determined by the following equation (1):
C＝A·[E1(v1+y·s)+E2(v2-y·s)]formula (1)
Wherein C is the distance between the stress neutral region and the bottom surface of the semiconductor package device, A is a predetermined constant, and E is1Young's modulus of the first fan-out layer, E2Is the Young's modulus of the packaging material, s is the area of the first fan-out layer, y is the thickness of the first fan-out layer, v1Is the volume ratio of the first fan-out layer to the semiconductor package device, v2Is the volume ratio of the packaging material to the semiconductor packaging device.
In another example, the distance between the stress neutral region and the bottom surface of the semiconductor package device is determined by the following equation (2):
C＝A·[E1(v1+y·s)+E2(v2-y·s)]+E3v3+E4v4……+E8v8formula (2)
Wherein, C, A, E1、E2、s、y、v1、v2The meaning of (A) is the same as in the above example, E3、E4……E8A Young's modulus, v, representing the Young's modulus of the semiconductor package device except for the package material and the first fan-out layer3、v4……v8The volume ratio of the other parts except the packaging material and the first fan-out layer to the whole in the semiconductor packaging device is represented.
As can be seen from a comparison of the formula (1) and the formula (2), the difference between the two is whether or not the other portions of the semiconductor package device except for the package material and the first fan-out layer are included in the calculation range. Since the related data of the packaging material and the first fan-out layer play a main role in calculating the distance between the stress neutral region and the bottom surface of the semiconductor packaging device, a more accurate and reliable calculation result can be obtained through the formula (1).
In one example, the stress neutral region is located near a middle position of the semiconductor package device in a thickness direction. As shown in fig. 2, the stress neutral region 800 and the bottom surface of the semiconductor package are both in the horizontal direction, and the stress neutral region 800 is located near the middle of the semiconductor package in the thickness direction (i.e., in the up-down direction in the drawing). Alternatively, the stress neutral region 800 is located approximately the same distance from the top surface of the semiconductor package as the bottom surface of the semiconductor package.
In one example, the semiconductor package device further includes a second chip on the wiring layer. As shown in fig. 2, the second chip 200 is located on the circuit layer 300. Specifically, the second chip 200 is located on the main fan-out layer 301. Further, an underfill material 900 is also disposed between the second chip 200 and the main fanout layer 301.
In one example, corners of the active surface of the second chip are proximate to the stress neutral region. As shown in fig. 2, the active surface (i.e., the bottom surface in the figure) of the second chip 200 is adjacent to the stress neutral region 800. Here, the corner of the active surface of the second chip is close to the stress neutral region, and may be a distance from the corner of the active surface of the second chip 200 to the stress neutral region 800, which is smaller than a distance from the corner of the active surface of the second chip 200 to the bottom surface of the circuit layer 300, or a distance from the corner of the active surface of the second chip 200 to the stress neutral region 800 is smaller than a preset value.
In one example, the conductor encapsulation apparatus may further include a second fan-out layer (not shown in fig. 2) located on the main fan-out layer 301, which may be located on the same side of the main fan-out layer 301 as the first fan-out layer 302, and the second chip 200 may be located on the second fan-out layer.
In one example, the first chip 100 is a High Bandwidth Memory (HBM) chip, and the second chip 200 is an Application Specific Integrated Circuit (ASIC).
In one example, the circuit layer 300 includes at least two dielectric layers, of which at least one dielectric layer has a different thickness from the other dielectric layers. As shown in fig. 4, the circuit layer 300 includes four dielectric layers, i.e., a first dielectric layer 303, a second dielectric layer 304, a third dielectric layer 305, and a fourth dielectric layer 306. The thickness of the first dielectric layer 303 is greater than the thicknesses of the other three dielectric layers.
In the above example, the thickness of the first dielectric layer 303 is larger than the thickness of the second dielectric layer 304, and the second dielectric layer 304 is closer to the first chip 100 than the first dielectric layer 303. Therefore, the thickness distribution of each dielectric layer in the packaging structure can be more reasonable.
In one example, an underfill material is disposed between the first chip and the wiring layer. The underfill material may be filled by molding or capillary means.
In one example, the connection between the first chip and the circuit layer is at least one of a through silicon via connection, a copper pillar connection, a flexible circuit board connection, and a wire connection. Fig. 5 is a schematic diagram of various connection modes of the first chip and the wiring layer in the semiconductor package device according to the embodiment of the invention. In the upper left illustration of fig. 5, the first chip 100 and the wiring layer 300 are connected by a through-silicon-via 101, wherein the through-silicon-via 101 is filled with a conductive material, such as copper metal. In the upper right diagram of fig. 5, the first chip 100 and the wiring layer 300 are connected by copper pillars 102. In the lower left illustration of fig. 5, the first chip 100 and the wiring layer 300 are connected by a flexible circuit board 103. In the lower right illustration of fig. 5, the first chip 100 and the line layer 300 are connected by a connection line 104. The connection mode can be selected according to specific requirements.
In one example, a surface of the encapsulant is provided with a heat sink layer. As shown in fig. 4, a heat dissipation layer 600 is disposed on a surface of the package material 400. The material of the heat dissipation layer 600 is, for example, metallic tin. Therefore, the radiating performance of the structure is improved. Further, a silicon dummy layer 500 is disposed between the package material 400 and the heat dissipation layer 600.
In one example, the bottom surface of the wiring layer is provided with an electrical connector. As shown in fig. 4, the bottom surface of the circuit layer 300 is provided with an electrical connector 700. Thus, the external connection of the semiconductor packaging device is favorably realized.
In one example, a silicon dummy layer may or may not be disposed above the second chip. As illustrated on the left side in fig. 6, a silicon dummy layer 500 is disposed above the second chip 200. The silicon dummy layer 500 can serve as a placeholder to adjust the position of the second chip 200. As illustrated on the right side in fig. 6, no silicon dummy layer is disposed over the second chip 200.
In one example, the number of the first chips or the second chips may be at least two. As illustrated in the upper part of fig. 7, the number of the first chips is two, i.e., a first chip 100a and a second chip 100b, and the second chip 200 is located between the two first chips. As illustrated in the lower part of fig. 7, the number of the first chips is two, i.e., a first chip 100a and a second chip 100b, and the second chip 200 is located at the right side of the two first chips.
In the semiconductor package device provided by the embodiment of the disclosure, the corners of the active surface of the first chip are arranged at the position close to the stress neutral region, so that the stress applied to the stress concentration point of the first chip is reduced, the extrusion effect of the corners of the first chip on surrounding materials (such as packaging materials) is further reduced, the corresponding structural fracture is avoided, and the product yield is favorably improved.
The embodiment also provides a manufacturing method of the semiconductor packaging device. Referring to fig. 8-15, the method includes the steps of:
in a first step, a main fan-out layer is formed on a carrier through a repeated process of photoetching, electroplating and etching. As shown in fig. 8, a main fan-out layer 301 can be formed on a carrier 10 by a repeated process of photolithography, plating, and etching.
And secondly, forming a first fan-out layer on the main fan-out layer through repeated processes of photoetching, electroplating and etching, wherein the main fan-out layer and the first fan-out layer jointly form a circuit layer.
In one example, the second step may be performed as follows: first, a barrier layer is placed over the main fan-out layer, wherein the barrier layer has a cavity. As shown in fig. 9, the barrier layer 11 is placed on the main fanout layer 301 by the bond head 12. Next, a first fan-out layer is formed within the cavity of the barrier layer by a repeated process of photolithography, plating, and etching. As shown in fig. 10, a first fan-out layer 302 is formed within the cavity of the barrier layer 11 by a repeated process of photolithography, plating, and etching.
And thirdly, electrically connecting the first chip to the first fan-out layer, wherein the active surface of the first chip faces the circuit layer. As shown in fig. 11, the first chip 100 is placed on the first fan-out layer 302 and electrically connected by soldering. Wherein the active surface (i.e., the lower surface in fig. 11) of the first chip 100 faces the first fan-out layer 302.
And fourthly, arranging an underfill material between the first chip and the first fan-out layer. As shown in fig. 11, an underfill material may be disposed between the first chip 100 and the first fan-out layer 302 by molding or capillary means.
And fifthly, molding is carried out above the main fan-out layer to obtain the semiconductor packaging device, wherein the corner of the active surface of the first chip is close to the stress neutral region of the semiconductor packaging device. As shown in fig. 11, molding is performed over the main fan-out layer 301 so that the encapsulating material 400 is formed over the main fan-out layer 301 to obtain the semiconductor package device. Wherein the corners of the active surface of the first chip 100 are close to the stress neutral region of the semiconductor package device.
In one example, prior to molding over the main fan-out layer, the method further comprises: first, a second chip is connected to the main fan-out layer. As shown in fig. 11, the second chip 200 is connected to the main fan-out layer 301. Next, an underfill material is disposed between the second chip and the main fanout layer. As shown in fig. 2, an underfill material is disposed between the second chip 200 and the main fanout layer 301.
In one example, after molding over the main fan-out layer, the method further comprises: a heat dissipation layer is provided on a surface of a package material of a semiconductor package device. Therefore, the heat dissipation performance of the packaging structure can be further improved.
In one example, after molding over the main fan-out layer, the method further comprises: and arranging an electric connector on the outer surface of the circuit layer. As shown in fig. 5, electrical connections 700 are provided on the surface of main fanout layer 301. Therefore, the external connection of the packaging structure is facilitated.
The present embodiment also provides another method of manufacturing a semiconductor package device. Referring to fig. 14-15, the method includes the following steps.
First, a wiring layer is formed on a carrier through a repeated process of photolithography, plating, and etching. As shown in fig. 14, a wiring layer 300 may be formed on the carrier 10 through a repeated process of photolithography, plating, and etching. The circuit layer 300 includes four dielectric layers.
Secondly, the first chip and the second chip are respectively connected to the circuit layers. As shown in fig. 15, the first chip 100 and the second chip 200 may be respectively connected to the wiring layer 300 by a soldering method.
And then, respectively arranging an underfill material between the first chip and the circuit layer and between the second chip and the circuit layer. As shown in fig. 15, an underfill material, such as an underfill, is disposed between the first chip 100 and the circuit layer 300 and between the second chip 200 and the circuit layer 300, respectively.
Finally, molding is performed over the wiring layer to obtain the semiconductor package device. As shown in fig. 15, molding is performed over the wiring layer 300 to fill the encapsulant 400, thereby obtaining a semiconductor package device.
The method for manufacturing the semiconductor package device in this embodiment can achieve similar technical effects to those of the semiconductor package device described above, and will not be described herein again.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package device includes a first chip and a wiring layer;
the first chip is positioned on the circuit layer, and the active surface of the first chip faces the circuit layer;
the semiconductor packaging device defines a stress neutral region, and corners of an active surface of the first chip are close to the stress neutral region.
2. The semiconductor package device of claim 1, wherein a distance of the stress neutral region from a bottom surface of the semiconductor package device is determined by the following formula (1):
C＝A·[E1(v1+y·s)+E2(v2-y·s)]formula (1)
Wherein C is a distance between the stress neutral region and the bottom surface of the semiconductor package device, A is a predetermined constant, and E is1Is the Young's modulus of the first fan-out layer, E2Is the Young's modulus of the packaging material, s is the area of the first fan-out layer, y is the thickness of the first fan-out layer, v1Is a volume ratio of the first fan-out layer to the semiconductor package device, v2Is the volume ratio of the packaging material to the semiconductor packaging device.
3. The semiconductor package device of claim 1, wherein the routing layer comprises a main fan-out layer and a first fan-out layer located on the main fan-out layer, an upper surface of the first fan-out layer being closer to the stress neutral zone than an upper surface of the main fan-out layer, the first chip being located on the main first fan-out layer.
4. The semiconductor package device of claim 3, wherein the second die is located on the main fan-out layer.
5. The semiconductor package device of claim 3, wherein the semiconductor package device further comprises a second fan-out layer located on the main fan-out layer, the second fan-out layer and the first fan-out layer being located on a same side of the main fan-out layer, the second chip being located on the second fan-out layer.
6. The semiconductor package device of claim 5, wherein corners of the active surface of the second chip are proximate to the stress neutral region.
7. The semiconductor package device according to claim 1, wherein the stress neutral region is located near a middle position of the semiconductor package device in a thickness direction.
8. The semiconductor package device of claim 1, wherein the semiconductor package device further comprises a second chip on the wiring layer.
9. A method of manufacturing a semiconductor package device, comprising:
forming a main fan-out layer on a carrier through repeated processes of photoetching, electroplating and etching;
forming a first fan-out layer on the main fan-out layer through repeated processes of photoetching, electroplating and etching, wherein the main fan-out layer and the first fan-out layer jointly form a circuit layer;
electrically connecting a first chip to the first fan-out layer, wherein an active surface of the first chip faces the wiring layer;
disposing an underfill material between the first chip and the first fan-out layer;
and molding the main fan-out layer to obtain the semiconductor packaging device, wherein the semiconductor packaging device defines a stress neutral region, and the corner of the active surface of the first chip is close to the stress neutral region.
10. The method of claim 9, wherein the forming a first fan-out layer on the main fan-out layer by a repeated process of photolithography, plating, and etching comprises:
placing a barrier layer on the main fan-out layer, wherein the barrier layer has a cavity;
and forming the first fan-out layer in the cavity of the barrier layer through repeated processes of photoetching, electroplating and etching.
CN202110095169.XA 2021-01-25 2021-01-25 Semiconductor package device and method of manufacturing the same Pending CN112992804A (en)

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