CN115706019A - Semiconductor package device and method of manufacturing the same - Google Patents

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a first chip; a second chip; a heat conductive member located between the first chip and the second chip; and the heat radiating fin is positioned above the first chip and the second chip. The semiconductor packaging device can avoid the internal structure of the semiconductor packaging device from being broken, and is beneficial to improving the yield of products.

Description

Semiconductor package device and method of manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.

Background

Nowadays, electronic devices are being miniaturized, and accordingly, higher demands are being made on the miniaturization of the package device.

In a conventional Fan-Out on Substrate (Fan Out Layer on Substrate) package structure, a Redistribution Layer (RDL) is generally disposed on a Substrate (Substrate). On the other hand, the Pitch (Pitch) of Input/output (I/O) on the bottom surface of the redistribution layer is generally large because it matches the Pitch of Input/output of the substrate. On the other hand, the line pitch of the input and output of the chip is generally small. Therefore, the pitch of the rewiring layer and the input/output of the chip is not uniform, making it difficult to directly connect the two. For the above reasons, the chips can be disposed on one side of the redistribution layer in a side-by-side manner or a stacked manner, which may result in an increase in the size of the package structure, which is not favorable for realizing miniaturization of the package device.

Therefore, a new technical solution is needed to solve at least one of the above technical problems.

Disclosure of Invention

The present disclosure provides a semiconductor package device and a method of manufacturing the same.

In a first aspect, the present disclosure provides a semiconductor package device comprising:

a substrate having an accommodating space;

the redistribution layer is positioned on the substrate, wherein a first surface of the redistribution layer is provided with a first electronic element, a second surface of the redistribution layer is provided with a second electronic element, and the second electronic element is positioned in the accommodating space.

In some optional embodiments, the redistribution layer is recessed with respect to the substrate to expose a first conductive member of the substrate surface, the first conductive member being electrically connected to the redistribution layer.

In some optional embodiments, the second surface of the redistribution layer is provided with an outer ring conductive element and an inner ring conductive element, the outer ring conductive element is located outside the inner ring conductive element, the inner ring conductive element is electrically connected to the second electronic component through a connection line, and the outer ring conductive element is electrically connected to the substrate through solder.

In some alternative embodiments, the planar dimensions of the outer ring conductive member are greater than the planar dimensions of the inner ring conductive member.

In some alternative embodiments, adjacent outer ring conductive members have a first predetermined spacing therebetween, and adjacent inner ring conductive members have a second predetermined spacing therebetween.

In some optional embodiments, a filling material is disposed in the accommodating space.

In some optional embodiments, the semiconductor package device further includes:

and the sealing material coats the first surface and the side wall of the redistribution layer.

In some alternative embodiments, at least a portion of a surface of the first electronic component is exposed outside the encapsulant.

In some alternative embodiments, the substrate and the redistribution layer are electrically connected by solder and/or a connection line.

In some alternative embodiments, the number of the first electronic element and/or the second electronic element is at least two;

the at least two first electronic elements are arranged in a stack, and/or the at least two second electronic elements are arranged in a stack.

In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:

electrically connecting a second surface of the redistribution layer with a first surface of a substrate through solder, wherein the substrate is provided with an accommodating space, and a second electronic element is arranged on the second surface of the redistribution layer and is positioned in the accommodating space;

forming a filling material in the accommodating space;

electrically connecting a first surface of the redistribution layer with a first surface of the substrate through a connection line;

fixing a first electronic component to a first surface of the redistribution layer;

and forming a sealing material on the first surface of the substrate to obtain the semiconductor packaging device, wherein the sealing material coats the first surface and the side wall of the redistribution layer.

In some optional embodiments, after forming an encapsulant on the substrate to obtain the semiconductor package device, the method further comprises:

and arranging an external connecting piece on the second surface of the substrate.

In the semiconductor packaging device and the manufacturing method thereof provided by the disclosure, a first electronic element is arranged on the first surface of the redistribution layer, and a second electronic element is arranged on the second surface of the redistribution layer and is positioned in the accommodating space of the substrate. Compared with the existing arrangement mode of arranging chips side by side or stacking chips, the second electronic element in the present disclosure is arranged in the substrate in an embedded mode, so that the thickness of the packaging device can be reduced, the miniaturization of the packaging device is facilitated, and further the miniaturization of electronic equipment is realized.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a prior art semiconductor package device;

fig. 2-8 are first through seventh schematic views of a semiconductor package device according to an embodiment of the present invention;

fig. 9 to 13 are schematic views of a method of manufacturing a semiconductor package device according to an embodiment of the present invention.

Description of the symbols:

11. a package substrate; 12. a fan-out layer; 13. an upper chip; 100. a substrate; 110. a first conductive member; 120. a second conductive member; 130. an accommodating space; 200. a rewiring layer; 210. an inner ring conductive member; 220. an outer ring conductive member; 310. a first electronic component; 320. a second electronic component; 400. a filler material; 500. connecting wires; 600. welding flux; 700. a sealing material; 710. a conductive post; 800. an external electrical connection; 910. a carrier; 920. a bond head; 930. injecting a glue piece; 940. and (5) a wire bonding piece.

Detailed Description

The following description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples, and the technical problems and effects solved by the present invention will be readily apparent to those skilled in the art from the description of the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and sizes shown in the drawings and described in the specification are only used for understanding and reading the contents described in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any modifications of the structures, changes of the proportion relation, or adjustments of the sizes, which do not affect the effects and the achievable purposes of the present invention, should still fall within the scope of the technical contents disclosed in the present invention. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.

It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a schematic diagram of a semiconductor package device in the prior art. As shown in fig. 1, the semiconductor package device includes a package substrate 11, a fan-out layer 12, and a plurality of upper chips 13. The fan-out layer 12 is disposed on the package substrate 11. The line widths of the input and output on the bottom surface of the fan-out layer 12 are equal to those of the package substrate 11. A plurality of upper dies 13 are disposed in a stacked manner on the fan-out layer 12. The line width of the input/output of the upper chip 13 is not coincident with the line width of the input/output of the fan-out layer 12. In this semiconductor package device, since the plurality of upper chips 13 are stacked, the vertical size of the structure is large, which is disadvantageous for miniaturization of the package device.

Fig. 2 to 7 are first to sixth schematic views of semiconductor package devices according to embodiments of the present invention.

Fig. 2 illustrates a longitudinal section of a semiconductor package device according to an embodiment of the present invention. As shown in fig. 2, the semiconductor package device in the present embodiment includes a substrate 100, a redistribution layer 200, a first electronic component 310, and a second electronic component 320. The substrate 100 has a receiving space 130. The rewiring layer 200 is located on the substrate 100. The first electronic component 310 is located on a first surface (i.e., the upper surface in fig. 2) of the redistribution layer 200, and the second electronic component 320 is located on a second surface (i.e., the lower surface in fig. 2) of the redistribution layer 200. The second electronic element 320 is located in the accommodating space 130 of the substrate 100.

As shown in fig. 2, the second surface of the redistribution layer 200 is provided with an outer-loop conductor 220 and an inner-loop conductor 210. The inner ring conductor 210 is electrically connected to the second electronic component 320 through a connection line 500, and the outer ring conductor 220 is electrically connected to the substrate 100 through a solder 600.

As shown in fig. 2, the upper surface of the substrate 100 is provided with a first conductive member 110 and a second conductive member 120. The first conductive member 110 is electrically connected to the conductive member on the upper surface of the redistribution layer 200 through a connection line 500. The second conductive member 120 is electrically connected to the outer ring conductive member 220 of the lower surface of the redistribution layer 200 by solder 600. Wherein, the redistribution layer 200 is retracted relative to the substrate 100 to expose the first conductive member 110 on the surface of the substrate 100, and the width of the redistribution layer 200 is smaller than that of the substrate 100. The lower surface of the substrate 100 is also provided with an external electrical connection 800.

As shown in fig. 2, the number of the second electronic components 320 is two, and two second electronic components 320 are stacked. In other embodiments, the number of the second electronic elements 320 may be one, three, or five, etc., which is not limited by the present disclosure. Similarly, the number of the first electronic components 310 may be plural, and may be arranged in a stacked manner.

As shown in fig. 2, a filling material 400 is disposed in the accommodating space 130 to enhance the structural strength and protect the second electronic element 320 in the accommodating space 130. The filler 400 may be a Molding Compound (Molding Compound) or an Underfill (Underfill), etc.

As shown in fig. 2, the semiconductor package device further includes a sealing material 700. The sealant 700 covers the first surface and the sidewall of the redistribution layer 200. Wherein, the upper surface of the first electronic component 310 is exposed to the outside, so as to achieve a better heat dissipation effect.

Fig. 3 shows a bottom view (looking up from the bottom of the redistribution layer 200) of the redistribution layer 200 of the semiconductor packaging apparatus according to the embodiment of the present invention. As shown in fig. 3, the second surface of redistribution layer 200 is provided with outer-ring conductor 220 and inner-ring conductor 210, outer-ring conductor 220 being located outside inner-ring conductor 210. The planar size of outer race conductor 220 is larger than the planar size of inner race conductor 210. The planar dimension may be a width, a circumference, a diagonal length, or the like, and the disclosure is not limited thereto.

In this embodiment, adjacent outer ring conductors 220 have a first predetermined spacing therebetween, and adjacent inner ring conductors 210 have a second predetermined spacing therebetween. In one example, the first predetermined spacing may be determined based on a planar size of outer race conductor 220 and the second predetermined spacing may be determined based on a planar size of inner race conductor 210. The correspondence relationship between the first predetermined interval and the planar size of the outer ring conductive member 220 and the correspondence relationship between the second predetermined interval and the planar size of the inner ring conductive member 210 may refer to the correspondence relationship between the line width and the line distance in the art, which is not limited by the present disclosure.

Fig. 4 illustrates a top view (looking down from the top of the substrate 100) of the substrate 100 of the semiconductor package device according to an embodiment of the present invention. As shown in fig. 4, the upper surface of the substrate 100 is provided with a first conductive member 110 and a second conductive member 120, and the first conductive member 110 is located outside the second conductive member 120. The middle portion of the substrate 100 is provided with an accommodating space 130. The accommodating space 130 is opened upward.

Fig. 5 is a modification of the semiconductor package device shown in fig. 2, in which the right side of the redistribution layer 200 and the right side of the substrate 100 in fig. 2 are connected by a connection wire 500, and the connection is performed by a solder 600, specifically, a Flip Chip (Flip Chip) method.

Fig. 6 is a modification of the semiconductor package device shown in fig. 2. In the semiconductor package device shown in fig. 2, the sealing material 700 is a Molding Compound (Molding Compound), and in the semiconductor package device shown in fig. 6, the sealing material 700 is a Potting Compound (Potting).

Fig. 7 is a modification of the semiconductor package shown in fig. 2. In the semiconductor package device shown in fig. 2, the upper surface of the redistribution layer 200 and the upper surface of the substrate 100 are electrically connected by the connection line 500, whereas in the semiconductor package device shown in fig. 7, the upper surface of the redistribution layer 200 and the upper surface of the substrate 100 are respectively provided with the conductive posts 710, and the conductive posts 710 are further connected to the uppermost conductive trace, thereby achieving electrical connection between the upper surface of the redistribution layer 200 and the upper surface of the substrate 100.

Fig. 8 is a modification of the semiconductor package shown in fig. 2. In the semiconductor package device shown in fig. 8, the substrate 100 has a plurality of accommodating spaces 130, and each accommodating space 130 is provided with a corresponding second electronic element 320. In this manner, it is advantageous to achieve a coordination between the lateral dimension (i.e., X-Y size) and the longitudinal dimension (i.e., Z height) of the semiconductor package device.

In the semiconductor package device and the method for manufacturing the same provided by the present disclosure, the first electronic element 310 is disposed on the first surface of the redistribution layer 200, and the second electronic element 320 is disposed on the second surface of the redistribution layer 200 and is located in the accommodating space 130 of the substrate 100. Compared with the existing arrangement mode of arranging chips side by side or stacking chips, the second electronic element 320 in the present disclosure is arranged in the substrate in an embedded mode, so that the thickness of the packaging device can be reduced, the miniaturization of the packaging device is facilitated, and the miniaturization of electronic equipment is further realized.

The embodiment also provides a manufacturing method of the semiconductor packaging device. As shown in fig. 8-12, the method includes the steps of:

in a first step, as shown in fig. 9, the carrier 910 is moved by the bonding head 920 to communicate with the redistribution layer 200 thereon, and the second surface of the redistribution layer 200 is electrically connected to the first surface of the substrate 100 by the solder 600. The substrate 100 has an accommodating space 130, a second surface of the redistribution layer 200 is provided with a second electronic element 320, and the second electronic element 320 is located in the accommodating space 130.

Secondly, as shown in fig. 10, the filling material 400 is formed in the accommodating space 130 by the glue injection member 930.

Third, as shown in fig. 11, the first surface of the redistribution layer 200 is electrically connected to the first surface of the substrate 100 by a bonding wire 500 using a wire bonding member (e.g., a bonding pin) 940.

Fourth, as shown in fig. 12, the first electronic component 310 is fixed to the first surface of the redistribution layer 200.

In a fifth step, as shown in fig. 13, a sealant 700 is formed on the first surface of the substrate 100 to obtain the semiconductor package device, wherein the sealant 700 covers the first surface and the sidewall of the redistribution layer 200.

In one example, after the fifth step, an external connection member may be disposed on the second surface of the substrate 100, so as to obtain the semiconductor package device shown in fig. 2.

The method for manufacturing a semiconductor package device in this embodiment can achieve the technical effects of the semiconductor package device described above, and will not be described herein again.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package device, comprising:

a substrate having an accommodating space;

the redistribution layer is located on the substrate, wherein a first surface of the redistribution layer is provided with a first electronic element, a second surface of the redistribution layer is provided with a second electronic element, and the second electronic element is located in the accommodating space.

2. The semiconductor package device of claim 1, wherein the redistribution layer is recessed relative to the substrate to expose a first conductive member of the substrate surface, the first conductive member being electrically connected to the redistribution layer.

3. The semiconductor package device according to claim 1, wherein the second surface of the redistribution layer is provided with an outer-ring conductive member and an inner-ring conductive member, the outer-ring conductive member being located outside the inner-ring conductive member, the inner-ring conductive member being electrically connected to the second electronic component through a connection wire, the outer-ring conductive member being electrically connected to the substrate through solder.

4. The semiconductor package device of claim 3, wherein a planar dimension of the outer ring conductive member is greater than a planar dimension of the inner ring conductive member.

5. The semiconductor package device of claim 4, wherein adjacent outer ring conductive members have a first predetermined spacing therebetween and adjacent inner ring conductive members have a second predetermined spacing therebetween; and a filling material is arranged in the accommodating space.

6. The semiconductor package device of claim 1, wherein the semiconductor package device further comprises:

and the sealing material coats the first surface and the side wall of the redistribution layer.

7. The semiconductor package device according to claim 6, wherein at least a part of a surface of the first electronic element is exposed outside the sealing material.

8. The semiconductor package device of claim 1, wherein the number of the first electronic element and/or the second electronic element is at least two;

the at least two first electronic elements are arranged in a stack, and/or the at least two second electronic elements are arranged in a stack.

9. A method of manufacturing a semiconductor package device, comprising:

electrically connecting a second surface of the redistribution layer with a first surface of a substrate through solder, wherein the substrate is provided with an accommodating space, and a second electronic element is arranged on the second surface of the redistribution layer and is positioned in the accommodating space;

forming a filling material in the accommodating space;

electrically connecting a first surface of the redistribution layer with a first surface of the substrate through a connection line;

fixing a first electronic element to a first surface of the redistribution layer;

and forming a sealing material on the first surface of the substrate to obtain the semiconductor packaging device, wherein the sealing material covers the first surface and the side wall of the redistribution layer.

10. The method of claim 9, wherein after forming a sealant on the substrate to obtain the semiconductor package device, the method further comprises:

and arranging an external connecting piece on the second surface of the substrate.

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