CN115706019A - Semiconductor package device and method of manufacturing the same - Google Patents

Abstract

The present disclosure relates to semiconductor packaging devices and methods of manufacturing the same. The semiconductor packaging device includes: a first chip; a second chip; a heat conduction element located between the first chip and the second chip; and a cooling fin located above the first chip and the second chip. The semiconductor packaging device can avoid breakage of the internal structure of the semiconductor packaging device, which is beneficial to improving product yield.

Description

Semiconductor packaging device and manufacturing method thereof

technical field

The present disclosure relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device and a manufacturing method thereof.

Background technique

Nowadays, electronic equipment is continuously developing toward the direction of miniaturization, and correspondingly higher requirements are put forward for the miniaturization of the size of packaging devices.

In the existing fan-out layer on substrate (Fan Out Layer on Substrate) packaging structure, a redistribution layer (Redistribution Layer, RDL) is usually disposed on the substrate (Substrate). On the one hand, the pitch of the input/output (I/O) on the bottom surface of the redistribution layer matches the pitch of the input/output of the substrate, so the pitch is usually larger. On the other hand, the line pitch of the input and output of the chip is usually small. Therefore, the redistribution layer is inconsistent with the line pitch of the input and output of the chip, making it difficult to directly connect the two. Based on the above reasons, chips can usually only be arranged on one side of the redistribution layer in a side-by-side manner or in a stacked manner, which will lead to an increase in the size of the packaging structure, which is not conducive to miniaturization of the size of the packaging device.

Therefore, it is necessary to propose a new technical solution to solve at least one of the above technical problems.

Contents of the invention

The present disclosure provides a semiconductor package device and a manufacturing method thereof.

In a first aspect, the present disclosure provides a semiconductor packaging device, including:

The base plate has an accommodating space;

A redistribution layer located on the substrate, wherein the first surface of the redistribution layer is provided with a first electronic component, the second surface of the redistribution layer is provided with a second electronic component, and the second electronic component located in the accommodating space.

In some optional implementation manners, the redistribution layer is retracted relative to the substrate to expose the first conductive member on the surface of the substrate, and the first conductive member is electrically connected to the redistribution layer.

In some optional embodiments, the second surface of the redistribution layer is provided with an outer ring conductive element and an inner ring conductive element, the outer ring conductive element is located outside the inner ring conductive element, and the inner ring The conductive element is electrically connected to the second electronic component through a connection wire, and the outer ring conductive element is electrically connected to the substrate through solder.

In some optional implementation manners, the plane size of the outer ring conductive member is larger than the plane size of the inner ring conductive member.

In some optional implementation manners, there is a first preset interval between adjacent conductive members of the outer ring, and there is a second preset interval between adjacent conductive members of the inner ring.

In some optional implementation manners, a filler is provided in the accommodating space.

In some optional implementation manners, the semiconductor packaging device also includes:

The sealing material covers the first surface and the sidewall of the redistribution layer.

In some optional implementation manners, at least part of the surface of the first electronic component is exposed outside the sealing material.

In some optional implementation manners, the substrate and the redistribution layer are electrically connected by solder and/or connecting wires.

In some optional embodiments, the number of the first electronic component and/or the second electronic component is at least two;

The at least two first electronic components are stacked, and/or the at least two second electronic components are stacked.

In a second aspect, the present disclosure provides a method for manufacturing a semiconductor packaging device, including:

The second surface of the redistribution layer is electrically connected to the first surface of the substrate through solder, wherein the substrate has an accommodating space, the second surface of the redistribution layer is provided with a second electronic component, and the second electronic component is The component is located in the containing space;

forming a filling material in the accommodating space;

electrically connecting the first surface of the redistribution layer to the first surface of the substrate through connecting wires;

fixing a first electronic component to the first surface of the redistribution layer;

A sealing material is formed on the first surface of the substrate to obtain the semiconductor packaging device, wherein the sealing material covers the first surface and the sidewall of the redistribution layer.

In some optional implementation manners, after forming a sealing material on the substrate to obtain the semiconductor package device, the method further includes:

An external connecting piece is arranged on the second surface of the substrate.

In the semiconductor package device and its manufacturing method provided by the present disclosure, the first electronic component is disposed on the first surface of the redistribution layer, and the second electronic component is disposed on the second surface of the redistribution layer and positioned in the accommodating space of the substrate Inside. Compared with the existing way of setting chips side by side or stacking chips, the second electronic component in the present disclosure is embedded in the substrate, so the thickness of the packaging device can be reduced, which is beneficial to realize the miniaturization of the packaging device, and further realize Miniaturization of electronic equipment.

Description of drawings

Other characteristics, objects and advantages of the present disclosure will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

1 is a schematic diagram of a semiconductor packaging device in the prior art;

2-8 are first to seventh schematic diagrams of a semiconductor packaging device according to an embodiment of the present invention;

9-13 are schematic diagrams of a manufacturing method of a semiconductor packaging device according to an embodiment of the present invention.

Symbol Description:

11. Packaging substrate; 12. Fan-out layer; 13. Upper chip; 100. Substrate; 110. First conductive member; 120. Second conductive member; 130. Accommodating space; 200. Rewiring layer; 210. Inner ring Conductive part; 220, outer ring conductive part; 310, first electronic component; 320, second electronic component; 400, filler material; 500, connecting wire; 600, solder; 700, sealing material; 710, conductive column; 800, External electrical connectors; 910, carrier; 920, bonding head; 930, plastic injection parts; 940, wiring parts.

Detailed ways

The specific implementation of the present invention will be described below in conjunction with the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the technical effects produced by the content recorded in this specification. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. In addition, for the convenience of description, only the parts related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of the specification are only used to match the content recorded in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementable aspects of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the implementable scope of the present invention without substantive change in the technical content.

It should also be noted that the longitudinal section corresponding to the embodiments of the present disclosure may be a section corresponding to a front view direction, the transverse section may be a section corresponding to a right view direction, and the horizontal section may be a section corresponding to an upper view direction.

In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other if there is no conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and embodiments.

FIG. 1 is a schematic diagram of a semiconductor packaging device in the prior art. As shown in FIG. 1 , the semiconductor package device includes a package substrate 11 , a fan-out layer 12 and a plurality of upper chips 13 . The fan-out layer 12 is disposed on the packaging substrate 11 . The input-output line width of the bottom surface of the fan-out layer 12 is consistent with the input-output line width of the package substrate 11 . A plurality of upper chips 13 are stacked on the fan-out layer 12 . The line width of the input and output of the upper chip 13 is inconsistent with the line width of the input and output of the fan-out layer 12 . In this semiconductor packaging device, since a plurality of upper chips 13 are arranged in a stacked manner, the longitudinal dimension of the structure is relatively large, which is not conducive to miniaturization of the packaging device.

2-7 are first to sixth schematic diagrams of a semiconductor packaging device according to an embodiment of the present invention.

FIG. 2 shows a longitudinal section of a semiconductor package device according to an embodiment of the present invention. As shown in FIG. 2 , the semiconductor package device in this embodiment includes a substrate 100 , a redistribution layer 200 , a first electronic component 310 and a second electronic component 320 . The substrate 100 has an accommodating space 130 . The redistribution layer 200 is located on the substrate 100 . The first electronic component 310 is located on the first surface of the redistribution layer 200 (ie, the upper surface in FIG. 2 ), and the second electronic component 320 is located on the second surface of the redistribution layer 200 (ie, the lower surface in FIG. 2 ). The second electronic component 320 is located in the accommodating space 130 of the substrate 100 .

As shown in FIG. 2 , the second surface of the redistribution layer 200 is provided with an outer conductive element 220 and an inner conductive element 210 . The inner conductive member 210 is electrically connected to the second electronic component 320 through the connecting wire 500 , and the outer conductive member 220 is electrically connected to the substrate 100 through the solder 600 .

As shown in FIG. 2 , the upper surface of the substrate 100 is provided with a first conductive element 110 and a second conductive element 120 . The first conductive element 110 is electrically connected to the conductive element on the upper surface of the redistribution layer 200 through the connection wire 500 . The second conductive member 120 is electrically connected to the outer ring conductive member 220 on the lower surface of the redistribution layer 200 through the solder 600 . Wherein, the redistribution layer 200 shrinks relative to the substrate 100 to expose the first conductive member 110 on the surface of the substrate 100 , and the width of the redistribution layer 200 is smaller than the width of the substrate 100 . The lower surface of the substrate 100 is also provided with an external electrical connector 800 .

As shown in FIG. 2 , there are two second electronic components 320 , and the two second electronic components 320 are stacked. In other implementation manners, the number of the second electronic component 320 may be one, three or five, etc., which is not limited in the present disclosure. Similarly, the number of first electronic components 310 may also be multiple, and may also be arranged in a stacked manner.

As shown in FIG. 2 , a filling material 400 is disposed in the accommodating space 130 to enhance structural strength and protect the second electronic component 320 in the accommodating space 130 . The filling material 400 may be a molding compound or an underfill.

As shown in FIG. 2 , the semiconductor packaging device further includes a sealing material 700 . The sealing material 700 covers the first surface and the sidewall of the redistribution layer 200 . Wherein, the upper surface of the first electronic component 310 is exposed outside, so as to achieve a better heat dissipation effect.

FIG. 3 shows a bottom view (looking upward from the bottom of the redistribution layer 200 ) of the redistribution layer 200 of the semiconductor package device according to an embodiment of the present invention. As shown in FIG. 3 , the second surface of the redistribution layer 200 is provided with an outer conductive element 220 and an inner conductive element 210 , and the outer conductive element 220 is located outside the inner conductive element 210 . The planar size of the outer conductive member 220 is greater than the planar size of the inner conductive member 210 . The above-mentioned planar dimensions may be width, perimeter or diagonal length, etc., which are not limited in the present disclosure.

In this embodiment, there is a first preset interval between adjacent outer ring conductive members 220 , and there is a second preset interval between adjacent inner ring conductive members 210 . In one example, the first predetermined interval may be determined according to the planar size of the outer conductive member 220 , and the second predetermined interval may be determined according to the planar size of the inner conductive member 210 . The corresponding relationship between the first preset interval and the plane size of the outer ring conductive member 220 and the corresponding relationship between the second preset interval and the plane size of the inner ring conductive member 210 can refer to the corresponding relationship between line width and line distance in the art, this disclosure There is no limit to this.

FIG. 4 shows a top view (looking down from the top of the substrate 100 ) of the substrate 100 of the semiconductor package device according to an embodiment of the present invention. As shown in FIG. 4 , the upper surface of the substrate 100 is provided with a first conductive element 110 and a second conductive element 120 , and the first conductive element 110 is located outside the second conductive element 120 . An accommodating space 130 is disposed in the middle of the substrate 100 . The opening of the accommodating space 130 is upward.

FIG. 5 is a modification of the semiconductor package device shown in FIG. 2, which changes the connection between the right side of the redistribution layer 200 and the right side of the substrate 100 in FIG. , specifically the Flip Chip method.

FIG. 6 is a modification of the semiconductor packaging device shown in FIG. 2 . In the semiconductor packaging device shown in FIG. 2 , the sealing material 700 is a molding compound, and in the semiconductor packaging device shown in FIG. 6 , the sealing material 700 is a potting compound.

FIG. 7 is a modification of the semiconductor packaging device shown in FIG. 2 . In the semiconductor package device shown in FIG. 2 , the upper surface of the redistribution layer 200 is electrically connected to the upper surface of the substrate 100 through the connection wire 500 , while in the semiconductor package device shown in FIG. 7 , the upper surface of the redistribution layer 200 The upper surface of the substrate 100 and the upper surface of the substrate 100 are respectively provided with conductive pillars 710 , and the conductive pillars 710 are further connected to the uppermost conductive circuit, so as to realize the electrical connection between the upper surface of the redistribution layer 200 and the upper surface of the substrate 100 .

FIG. 8 is a modification of the semiconductor packaging device shown in FIG. 2 . In the semiconductor packaging device shown in FIG. 8 , the substrate 100 has a plurality of accommodating spaces 130 , and each accommodating space 130 is provided with a corresponding second electronic component 320 . In this way, it is beneficial to realize the coordination between the lateral size (ie, X-Y size) and the vertical size (ie, Z height) of the semiconductor package device.

In the semiconductor package device and its manufacturing method provided by the present disclosure, the first electronic component 310 is disposed on the first surface of the redistribution layer 200, and the second electronic component 320 is disposed on the second surface of the redistribution layer 200 and positioned on the substrate. 100 in the accommodating space 130 . Compared with the existing way of setting chips side by side or chip stacking, the second electronic component 320 in the present disclosure is embedded in the substrate, so the thickness of the packaging device can be reduced, which is beneficial to realize the miniaturization of the packaging device, and further Realize the miniaturization of electronic equipment.

This embodiment also provides a method for manufacturing a semiconductor packaging device. As shown in Figures 8-12, the method includes the following steps:

The first step, as shown in FIG. 9 , is to use the bonding head 920 to move the carrier 910 to communicate with the redistribution layer 200 on it, and electrically connect the second surface of the redistribution layer 200 to the first surface of the substrate 100 through solder 600 . Wherein, the substrate 100 has an accommodating space 130 , the second electronic component 320 is disposed on the second surface of the redistribution layer 200 , and the second electronic component 320 is located in the accommodating space 130 .

In the second step, as shown in FIG. 10 , the filling material 400 is formed in the accommodating space 130 through the injection part 930 .

In the third step, as shown in FIG. 11 , the first surface of the redistribution layer 200 is electrically connected to the first surface of the substrate 100 through the connecting wire 500 by using a wire bonding element (such as a welding pin) 940 .

The fourth step, as shown in FIG. 12 , is to fix the first electronic component 310 to the first surface of the redistribution layer 200 .

In the fifth step, as shown in FIG. 13 , a sealing material 700 is formed on the first surface of the substrate 100 to obtain a semiconductor package device, wherein the sealing material 700 covers the first surface and the sidewall of the redistribution layer 200 .

In one example, after the above fifth step, external connectors may be provided on the second surface of the substrate 100 to obtain a semiconductor package device as shown in FIG. 2 .

The manufacturing method of the semiconductor packaging device in this embodiment can achieve the technical effect of the semiconductor packaging device described above, and will not be repeated here.

While the present disclosure has been described and illustrated with reference to particular embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. Illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process and the like, there may be differences between the technical reproductions in this disclosure and the actual device. There may be other embodiments of the disclosure not specifically described. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that such operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the disclosure. Accordingly, the order and grouping of operations does not limit the present disclosure unless otherwise indicated herein.

Claims (10)

1. A semiconductor packaging device, comprising: The base plate has an accommodating space; A redistribution layer located on the substrate, wherein the first surface of the redistribution layer is provided with a first electronic component, the second surface of the redistribution layer is provided with a second electronic component, and the second electronic component located in the accommodating space. 2. The semiconductor package device according to claim 1, wherein the rewiring layer shrinks relative to the substrate to expose the first conductive member on the surface of the substrate, the first conductive member is connected to the rewiring layer layer electrical connection. 3. The semiconductor packaging device according to claim 1, wherein the second surface of the redistribution layer is provided with an outer conductive member and an inner conductive member, and the outer conductive member is located on the inner conductive member On the outside, the inner conductive member is electrically connected to the second electronic component through a connecting wire, and the outer conductive member is electrically connected to the substrate through solder. 4. The semiconductor package device according to claim 3, wherein a planar size of the outer conductive member is larger than a planar size of the inner conductive member. 5. The semiconductor packaging device according to claim 4, wherein there is a first preset interval between adjacent said outer ring conductive members, and there is a second preset interval between adjacent said inner ring conductive members ; The accommodating space is provided with a filling material. 6. The semiconductor packaging device according to claim 1, wherein the semiconductor packaging device further comprises: The sealing material covers the first surface and the sidewall of the redistribution layer. 7. The semiconductor package device according to claim 6, wherein at least part of the surface of the first electronic component is exposed outside the sealing material. 8. The semiconductor package device according to claim 1, wherein the number of the first electronic component and/or the second electronic component is at least two; The at least two first electronic components are stacked, and/or the at least two second electronic components are stacked. 9. A method of manufacturing a semiconductor packaging device, comprising: The second surface of the redistribution layer is electrically connected to the first surface of the substrate through solder, wherein the substrate has an accommodating space, the second surface of the redistribution layer is provided with a second electronic component, and the second electronic component is The component is located in the containing space; forming a filling material in the accommodating space; electrically connecting the first surface of the redistribution layer to the first surface of the substrate through connecting wires; fixing a first electronic component to the first surface of the redistribution layer; A sealing material is formed on the first surface of the substrate to obtain the semiconductor packaging device, wherein the sealing material covers the first surface and the sidewall of the redistribution layer. 10. The method according to claim 9, wherein, after forming a sealing material on the substrate to obtain the semiconductor package device, the method further comprises: An external connecting piece is arranged on the second surface of the substrate.

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