CN112992767A - Processing technology of compound semiconductor wafer - Google Patents
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- CN112992767A CN112992767A CN202110284168.XA CN202110284168A CN112992767A CN 112992767 A CN112992767 A CN 112992767A CN 202110284168 A CN202110284168 A CN 202110284168A CN 112992767 A CN112992767 A CN 112992767A
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- 150000001875 compounds Chemical class 0.000 title claims abstract description 85
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- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims abstract description 71
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- 239000010703 silicon Substances 0.000 claims abstract description 29
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a processing technology of a compound semiconductor wafer, which comprises the following steps: s1, finishing the front-stage crystal process of the small-size compound semiconductor substrate; s2, permanently bonding the compound semiconductor substrate and the silicon substrate; s3, manufacturing a back element process; s4, bonding the back of the compound semiconductor substrate to the glass carrier after the back process is finished; s5, turning over to the front side, completely removing the silicon substrate by using grinding and etching processes, and then manufacturing a front side process; s6, after the front face process is finished, a cutting process is carried out; and S7, debonding, removing the glass carrier plate, and removing the bonded adhesive film or composite film to complete the processing of the compound semiconductor wafer. The process can utilize the existing silicon substrate processing equipment to process the small-sized compound semiconductor substrate, thereby improving the production efficiency, enabling the small-sized compound semiconductor to be manufactured thinner, improving the utilization rate of the compound material crystal column and greatly reducing the material cost.
Description
Technical Field
The invention relates to the field of wafer processing, in particular to a processing technology of a compound semiconductor wafer.
Background
Semiconductor materials can be classified into elementary semiconductors such as semiconductors formed of silicon (Si), germanium (Ge), and the like, and compound semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like. While semiconductors have been mainly changed in the third generation in the past, gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) semiconductors, which are representative of the second and third generation semiconductors, are much more excellent in high-frequency performance and high-temperature performance than the first generation semiconductors, and are more expensive to manufacture, and are therefore new and expensive in semiconductors.
The compound semiconductor can show excellent performance on ultrahigh voltage (8000V) IGBT and ultrahigh frequency (300 KHz) MOSFET elements, but the current mass production technology of the crystal growth material can only limit the substrate size to 6 inches and below 6 inches, and is incompatible with the 8 inch/12 inch process of the existing silicon chip. Although the price of the small-sized compound semiconductor substrate is much lower than that of the large-sized substrate (compound semiconductor), the production efficiency of the device is not good, so that the reasonable development of the industry cannot be driven.
Disclosure of Invention
In order to solve the above-mentioned drawbacks of the prior art, the present invention provides a process for processing a compound semiconductor wafer, which uses a secondary bonding technique. The first is permanent bonding of silicon base plate, making back element and metal, the second is temporary bonding by using glass carrier plate, turning over to front to remove silicon base plate, making contact window and front metal and passivation layer or electroplating (chemical plating), and finally transferring to cutting mould frame, and using diamond cutter wheel or laser + plasma etching process to implement cutting process to make small-size compound semiconductor implement crystal grain sealing and testing engineering.
The purpose of the invention can be realized by the following technical scheme:
a process for processing a compound semiconductor wafer, comprising the steps of:
s1, finishing the front-stage crystal process of the small-size compound semiconductor substrate, including Gate, oxide interlayer, ion implantation and tempering processes;
s2, depositing a LID layer on the front surface of the small-size compound semiconductor substrate and then permanently bonding the small-size compound semiconductor substrate with the silicon substrate;
s3, bonding the silicon substrate, turning over to the back of the wafer, manufacturing a back component, comprising the processes of exposure, projection, particle implantation, photoresistance removal and high-temperature tempering, and then performing back metal deposition and chemical plating electroplating processes, and finishing the alloy forming and heating process of metal and compound semiconductor;
s4, bonding the back of the compound semiconductor substrate to the glass carrier plate by using a thick glue coating or elastic filling composite film after the back process is finished;
s5, turning over to the front side, completely removing the silicon substrate by grinding and etching processes to completely expose the ILD layer on the surface of the compound semiconductor, and then manufacturing a contact window, a metal connecting wire, a passivation layer and a chemical plating electroplating process on the front side;
s6, after the front process is finished, a cutting process is carried out to ensure that no metal is connected with the metal layer in the gap area at the edge of the compound semiconductor;
and S7, attaching the cut crystal grains to a cutting die frame, then removing the glass carrier plate by bonding, finally removing the bonded adhesive film or composite film by using a solvent or an adhesive tape, lifting the metal in the gap to complete the processing of the compound semiconductor wafer, and carrying out subsequent packaging and testing processes.
Further preferably, the compound semiconductor substrate includes a SiC substrate, a GaN substrate and a GaAs substrate, and the temperature of the particle implantation in step S1 is 400-500 ℃, and the temperature of the annealing process is 1000-1800 ℃.
Further preferably, the method for permanently bonding the compound semiconductor substrate and the silicon substrate in step S2 includes the steps of:
s201, depositing an ILD layer on the front surface of the compound semiconductor substrate through CVD;
s202, flattening the ILD layer on the front surface of the compound semiconductor substrate through CMP, and reducing the surface roughness Ra to be less than 0.5 mu m;
s203, forming Si-H, Si-O active bonds on the surface of the Si substrate by using the plasma;
s204, bonding the front surface of the small-size compound semiconductor substrate to the silicon substrate;
s205, heating to above 400 ℃ for above 4h to generate permanent bonding between the two substrates.
Further preferably, in step S3, the compound semiconductor substrate edge is provided with an R-shaped chamfer during metal deposition and electroplating, the chamfer is made during the substrate cutting and edge grinding, so that the metal is disconnected at the compound semiconductor substrate edge for facilitating the subsequent separation process after debonding.
Further preferably, the cutting process in step S6 uses a diamond wheel, laser or plasma etching.
Further preferably, the step S7 is performed by thermal pyrolytic bonding, UV irradiation photolytic bonding or laser debonding.
The invention has the beneficial effects that:
compared with the prior art, the compound semiconductor in the prior art can only manufacture elements in a process below 6 inches, the benefit is poor, and the material cost is far higher than that of a silicon-based process, the compound semiconductor in the prior art adopts a bonding (double-time) technology, can fully utilize compound semiconductor base materials with various small sizes to integrate a large-size silicon-based carrier plate and a back process, greatly improves the production efficiency, can utilize the small-size compound semiconductor base plate of the prior Si (silicon-based) production line, does not need repeated investment, can manufacture the thin base plate (200 plus materials and 300 mu m) in the small-size compound semiconductor, is thinner than the thickness (500 plus materials and 600 mu m) of the prior 6-inch base plate to be less than half, greatly improves the utilization rate of the compound material (Ingout) crystal column.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic molding diagram of step S1 of the process of the present invention;
FIG. 2 is a schematic molding diagram of step S2 of the process of the present invention;
FIG. 3 is a schematic molding diagram of step S3 of the present invention;
FIG. 4 is a schematic molding diagram of step S4 of the present invention;
FIG. 5 is a schematic molding diagram of step S5 of the present invention;
fig. 6 is a schematic molding diagram of step S6 of the present invention.
In the figure:
1-compound semiconductor substrate, 2-alignment mark, 3-R type chamfer, 4-ILD layer, 5-silicon substrate, 6-glass carrier plate and 7-crystal grain.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
Example 1
A process for processing a compound semiconductor wafer, comprising the steps of:
s1, finishing a front-stage crystal process of the small-size compound semiconductor substrate, wherein the front-stage crystal process comprises a Gate, an oxide interlayer, ion implantation and tempering processes, the particle implantation temperature is 400 ℃, and the tempering process temperature is 1600 ℃;
s2, permanently bonding a plurality of small-size compound semiconductor substrates to a silicon substrate, specifically:
s201, depositing an ILD layer on the front surface of the compound semiconductor substrate through CVD;
s202, flattening the ILD layer on the front surface of the compound semiconductor substrate through CMP, and reducing the surface roughness Ra to be less than 0.5 mu m;
s203, forming Si-H, Si-O active bonds on the surface of the Si substrate by using the plasma;
s204, bonding the front surface of the small-size compound semiconductor substrate to the silicon substrate;
s205, heating to 500 ℃ for 5h to generate permanent bonding between the two layers of substrates;
s3, bonding the silicon substrate, turning over to the back of the wafer, manufacturing a back component, comprising the processes of exposure, projection, particle implantation, photoresistance removal and high-temperature tempering, and then performing back metal deposition and chemical plating electroplating processes, and finishing the alloy forming and heating process of metal and compound semiconductor;
s4, bonding the back of the compound semiconductor substrate to the glass carrier plate by using a thick glue coating or elastic filling composite film after the back process is finished;
s5, turning over to the front side, completely removing the silicon substrate by grinding and etching processes to completely expose the ILD layer on the surface of the compound semiconductor, and then manufacturing a contact window, a metal connecting wire, a passivation layer and a chemical plating electroplating process on the front side;
s6, after finishing the front process, cutting the compound semiconductor wafer by using a diamond cutter wheel, laser or plasma etching to ensure that no metal is connected with the metal layer in the gap region at the edge of the compound semiconductor;
and S7, attaching the cut crystal grains to a cutting die frame, removing the glass carrier plate by utilizing pyrolytic bonding, UV irradiation photolysis bonding or laser de-bonding, finally removing the bonded adhesive film or composite film by using a solvent or an adhesive tape, and lifting the metal at the gap to complete the processing of the compound semiconductor wafer, so that the subsequent packaging and testing processes can be carried out.
In step S3, an R-shaped chamfer is formed on the edge of the compound semiconductor substrate during metal deposition and electroplating, and the chamfer is formed during the cutting and edge grinding of the substrate, so that the metal is disconnected at the edge of the compound semiconductor substrate for facilitating the subsequent separation process after debonding.
Example 2
A process for processing a compound semiconductor wafer, comprising the steps of:
s1, finishing a front-stage crystal process of the small-size compound semiconductor substrate, wherein the front-stage crystal process comprises a Gate, an oxide interlayer, ion implantation and tempering processes, the particle implantation temperature is 800 ℃, and the tempering process temperature is 1200 ℃;
s2, permanently bonding a plurality of small-size compound semiconductor substrates to a silicon substrate, specifically:
s201, depositing an ILD layer on the front surface of the compound semiconductor substrate through CVD;
s202, flattening the ILD layer on the front surface of the compound semiconductor substrate through CMP, and reducing the surface roughness Ra to be less than 0.5 mu m;
s203, forming Si-H, Si-O active bonds on the surface of the Si substrate by using the plasma;
s204, bonding the front surface of the small-size compound semiconductor substrate to the silicon substrate;
s205, heating to 600 ℃ for 6h to generate permanent bonding between the two layers of substrates;
s3, bonding the silicon substrate, turning over to the back of the wafer, manufacturing a back component, comprising the processes of exposure, projection, particle implantation, photoresistance removal and high-temperature tempering, and then performing back metal deposition and chemical plating electroplating processes, and finishing the alloy forming and heating process of metal and compound semiconductor;
s4, bonding the back of the compound semiconductor substrate to the glass carrier plate by using a thick glue coating or elastic filling composite film after the back process is finished;
s5, turning over to the front side, completely removing the silicon substrate by grinding and etching processes to completely expose the ILD layer on the surface of the compound semiconductor, and then manufacturing a contact window, a metal connecting wire, a passivation layer and a chemical plating electroplating process on the front side;
s6, after finishing the front process, cutting the compound semiconductor wafer by using a diamond cutter wheel, laser or plasma etching to ensure that no metal is connected with the metal layer in the gap region at the edge of the compound semiconductor;
and S7, attaching the cut crystal grains to a cutting die frame, removing the glass carrier plate by utilizing pyrolytic bonding, UV irradiation photolysis bonding or laser de-bonding, finally removing the bonded adhesive film or composite film by using a solvent or an adhesive tape, and lifting the metal at the gap to complete the processing of the compound semiconductor wafer, so that the subsequent packaging and testing processes can be carried out.
In step S3, an R-shaped chamfer is formed on the edge of the compound semiconductor substrate during metal deposition and electroplating, and the chamfer is formed during the cutting and edge grinding of the substrate, so that the metal is disconnected at the edge of the compound semiconductor substrate for facilitating the subsequent separation process after debonding.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (6)
1. A process for processing a compound semiconductor wafer, comprising the steps of:
s1, finishing the front-stage crystal process of the small-size compound semiconductor substrate, including Gate, oxide interlayer, ion implantation and tempering processes;
s2, depositing a LID layer on the front surface of the small-size compound semiconductor substrate and then permanently bonding the small-size compound semiconductor substrate with the silicon substrate;
s3, bonding the silicon substrate, turning over to the back of the wafer, manufacturing a back component, comprising the processes of exposure, projection, particle implantation, photoresistance removal and high-temperature tempering, and then performing back metal deposition and chemical plating electroplating processes, and finishing the alloy forming and heating process of metal and compound semiconductor;
s4, bonding the back of the compound semiconductor substrate to the glass carrier plate by using a thick glue coating or elastic filling composite film after the back process is finished;
s5, turning over to the front side, completely removing the silicon substrate by grinding and etching processes to completely expose the ILD layer on the surface of the compound semiconductor, and then manufacturing a contact window, a metal connecting wire, a passivation layer and a chemical plating electroplating process on the front side;
s6, after the front process is finished, a cutting process is carried out to ensure that no metal is connected with the metal layer in the gap area at the edge of the compound semiconductor;
and S7, attaching the cut crystal grains to a cutting die frame, then removing the glass carrier plate by bonding, finally removing the bonded adhesive film or composite film by using a solvent or an adhesive tape, lifting the metal in the gap to complete the processing of the compound semiconductor wafer, and carrying out subsequent packaging and testing processes.
2. The process for processing a compound semiconductor wafer as claimed in claim 1, wherein the compound semiconductor substrate comprises a SiC substrate, a GaN substrate and a GaAs substrate, and the annealing process temperature in the step S1 is 1000-1800 ℃.
3. The process of claim 1, wherein the method for permanently bonding the compound semiconductor substrate and the silicon substrate in the step S2 comprises the steps of:
s201, depositing an ILD layer on the front surface of the compound semiconductor substrate through CVD;
s202, flattening the ILD layer on the front surface of the compound semiconductor substrate through CMP, and reducing the surface roughness Ra to be less than 0.5 mu m;
s203, forming Si-H, Si-O active bonds on the surface of the Si substrate by using the plasma;
s204, bonding the front surface of the small-size compound semiconductor substrate to the silicon substrate;
s205, heating to above 400 ℃ for above 4h to generate permanent bonding between the two substrates.
4. The process of claim 1, wherein the compound semiconductor substrate edge is provided with an R-shaped chamfer during metal deposition and electroplating in step S3, the chamfer is formed during the cutting and edging of the substrate, so that the metal is disconnected at the compound semiconductor substrate edge for facilitating the subsequent separation process after debonding.
5. The process of claim 1, wherein the dicing process in step S6 uses a diamond wheel, laser or plasma etching.
6. The process for manufacturing a compound semiconductor wafer according to claim 1, wherein the step S7 is performed by thermal pyrolytic bonding, UV irradiation photolytic bonding or laser debonding.
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| CN202110284168.XA CN112992767A (en) | 2021-03-17 | 2021-03-17 | Processing technology of compound semiconductor wafer |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1187200A (en) * | 1997-09-05 | 1999-03-30 | Toshiba Corp | Semiconductor substrate and manufacture of semiconductor device |
| CN111192822A (en) * | 2020-01-10 | 2020-05-22 | 上海大学 | Low temperature bonding method of silicon wafer and compound semiconductor wafer |
| CN111599754A (en) * | 2020-06-19 | 2020-08-28 | 绍兴同芯成集成电路有限公司 | Ultrathin wafer processing technology |
| CN112259495A (en) * | 2020-10-22 | 2021-01-22 | 绍兴同芯成集成电路有限公司 | Wafer printing process |
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2021
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| JPH1187200A (en) * | 1997-09-05 | 1999-03-30 | Toshiba Corp | Semiconductor substrate and manufacture of semiconductor device |
| CN111192822A (en) * | 2020-01-10 | 2020-05-22 | 上海大学 | Low temperature bonding method of silicon wafer and compound semiconductor wafer |
| CN111599754A (en) * | 2020-06-19 | 2020-08-28 | 绍兴同芯成集成电路有限公司 | Ultrathin wafer processing technology |
| CN112259495A (en) * | 2020-10-22 | 2021-01-22 | 绍兴同芯成集成电路有限公司 | Wafer printing process |
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