CN111192822A - Low temperature bonding method of silicon wafer and compound semiconductor wafer - Google Patents

Low temperature bonding method of silicon wafer and compound semiconductor wafer Download PDF

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CN111192822A
CN111192822A CN202010024306.6A CN202010024306A CN111192822A CN 111192822 A CN111192822 A CN 111192822A CN 202010024306 A CN202010024306 A CN 202010024306A CN 111192822 A CN111192822 A CN 111192822A
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compound semiconductor
silicon wafer
graphene
wafer
crystal
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CN111192822B (en
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闵嘉华
秦美琪
陈军
戴灵恩
赵树浩
梁小燕
张继军
沈悦
王林军
赵岳
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Beijing Transpacific Technology Development Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Abstract

The invention discloses a low-temperature bonding method of a silicon wafer and a compound semiconductor wafer, which uses new substance graphene as a bonding medium to realize the bonding of CdZnTe and silicon, and comprises the following steps: preparing silicon wafer, and performing standard wet chemical cleaning (RCA) on the silicon wafer; then preparing a CdZnTe wafer, and carrying out surface treatment processes such as chamfering, physical polishing, chemical mechanical polishing and the like on the CdZnTe crystal; then, the graphene is transferred to the surface of Si, or the graphene is transferred to the surface of CZT, or the graphene is transferred to the surfaces of CZT and Si, low-temperature annealing bonding is carried out on the two crystals, the problem of overhigh bonding is avoided, the bonding quality is high, and the performance is excellent.

Description

Low temperature bonding method of silicon wafer and compound semiconductor wafer
Technical Field
The invention relates to a preparation method of a semiconductor electronic device, in particular to a combination method between silicon and a compound semiconductor material, which is applied to the technical field of preparation processes of semiconductor electronic devices.
Background
Silicon has low cost and other advantages and is widely used in the field of microelectronics, but because it does not have the characteristics of linear photoelectric effect and the like, it needs to be combined with compound semiconductors to form optoelectronic devices and integrated circuits with more functions and better performance. Epitaxial growth is not suitable for bonding between compound semiconductor and silicon due to lattice mismatch between different crystals, which is a common method.
Although progress has been made in the method of bonding a compound semiconductor to silicon, group II-VI compound semiconductors and silicon are rarely bonded. In the prior art, the problems of high temperature, difficult alignment of crystal orientation, low bonding rate and the like exist in the bonding process, CdZnTe is a II-VI compound semiconductor material for manufacturing a nuclear radiation detector with high efficiency and high resolution, and if silicon and II-VI compound semiconductor crystal can be bonded, a series of novel devices are expected to be developed, which becomes a technical problem to be solved urgently and limits the application of the novel semiconductor in the period.
Disclosure of Invention
In order to solve the problems of the prior art, the invention aims to overcome the defects in the prior art and provide a low-temperature bonding method of a silicon wafer and a compound semiconductor wafer, wherein an intermediate layer is introduced into the middle of a bonding material to become an important method for bonding between a compound semiconductor and silicon. According to the invention, graphene is used as a bonding medium, so that low-temperature bonding of CdZnTe and silicon is realized, the problem of overhigh bonding is avoided, the bonding quality is high, and the performance is excellent.
In order to achieve the purpose of the invention, the invention adopts the following technical scheme:
a low-temperature bonding method of a silicon wafer and a compound semiconductor wafer, comprising the steps of:
a. silicon chip pretreatment:
preparing a silicon wafer, and cleaning the silicon wafer by a chemical cleaning method to obtain a clean silicon wafer;
b. surface treatment of compound semiconductor wafer:
preparing a compound semiconductor wafer, chamfering the compound semiconductor crystal, and then performing physical polishing and chemical mechanical polishing surface treatment processes to enable the crystal surface of the compound semiconductor wafer to have no visible scratches and finish the surface treatment of the compound semiconductor wafer;
c. bonding process of silicon wafer and compound semiconductor wafer:
adopting any one of the following three modes of bonding a silicon wafer and a compound semiconductor wafer:
the first method is as follows: b, taking graphene as an intermediate medium material, transferring the graphene to the surface of the silicon wafer pretreated in the step a, coating the graphene on the surface of the silicon wafer, cleaning the silicon wafer and the compound semiconductor wafer subjected to surface treatment in the step b in deionized water, and drying; then, attaching the surface of the Si crystal with the surface coated with graphene to the surface of the crystal of the compound semiconductor wafer to form a combined layer structure in a silicon-graphene-compound semiconductor form, and then carrying out low-temperature annealing bonding at the temperature of not higher than 250 ℃ to enable the graphene layer to form an electron transport layer, thereby preparing a silicon wafer and compound semiconductor wafer bonded wafer device;
the second method comprises the following steps: transferring graphene to the surface of the compound semiconductor wafer subjected to the surface treatment in the step b by using the graphene as an intermediate medium material, coating the graphene on the surface of the compound semiconductor wafer, and cleaning the silicon wafer and the compound semiconductor wafer pretreated in the step a in deionized water and then drying the silicon wafer and the compound semiconductor wafer; then, adhering the surface of a compound semiconductor with the surface coated with graphene to the surface of a crystal of a silicon wafer to form a combined layer structure in the form of a silicon-graphene-compound semiconductor, and then carrying out low-temperature annealing bonding at the temperature of not higher than 250 ℃ to enable a graphene layer to form an electron transport layer, thereby preparing a silicon wafer and compound semiconductor wafer bonded wafer device;
the third method comprises the following steps: respectively transferring graphene to the surface of the compound semiconductor wafer subjected to the surface treatment in the step b and the surface of the compound semiconductor wafer subjected to the surface treatment in the step b by using the graphene as an intermediate medium material, respectively coating the graphene on the surface of the compound semiconductor wafer and the surface of a silicon wafer, cleaning the silicon wafer and the compound semiconductor wafer in deionized water, and drying; and then, adhering the surface of the compound semiconductor with the surface coated with the graphene to the surface of the crystal of the silicon wafer with the surface coated with the graphene to form a combined layer structure in the form of a silicon-graphene-compound semiconductor, and then carrying out low-temperature annealing bonding at the temperature of not higher than 250 ℃ to enable the graphene layer to form an electron transport layer, thereby preparing the silicon wafer and compound semiconductor wafer bonded wafer device.
As a preferred technical scheme of the invention, in the step c, when the low-temperature annealing bonding is carried out, the annealing temperature is 100-250 ℃, and the annealing time is 20-24 h.
In the step B, a group IIB-VIA semiconductor or a group IIIB-VA semiconductor is used as the compound semiconductor wafer. The compound semiconductor wafer further preferably employs CdZnTe.
As a preferred technical solution of the present invention, in the step a, the silicon wafer is cleaned by a chemical cleaning method, which includes the following steps:
preparing cleaning solution I, solution II and solution III for cleaning:
the solution I is organic matter cleaning solution, and is prepared by mixing ammonia water with the mass concentration not lower than 27%, hydrogen peroxide with the mass concentration not lower than 30% and deionized water according to the volume ratio of 1:1: 5;
the solution II is an oxide removing solution, and is prepared by mixing hydrofluoric acid with the mass concentration not lower than 50% and deionized water according to the volume ratio of 1: 50;
the solution III is an ionic cleaning solution, and is prepared by mixing hydrochloric acid with the mass concentration not lower than 37%, hydrogen peroxide with the mass concentration not lower than 30% and deionized water according to the volume ratio of 1:1: 6;
the silicon wafer is sequentially subjected to the following cleaning processes:
firstly, immersing a silicon wafer into the solution I, immersing for at least 10 minutes at the temperature of not higher than 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for at least 2 minutes; then, soaking the silicon wafer in the solution II for at least 30 seconds at normal temperature, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for at least 2 minutes; and finally, soaking the silicon wafer in the solution III for at least 10 minutes at the temperature of not higher than 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for at least 2 minutes to finish the silicon wafer cleaning process.
As a preferred embodiment of the present invention, in the step b, when performing surface treatment on the compound semiconductor wafer, the compound semiconductor wafer is chamfered to smooth the peripheral corners; adhering the compound semiconductor crystal to a glass plate by using wax, and performing primary polishing by using a PM6 physical polishing instrument, wherein the polishing plate is a glass plate, the pressure of a clamp is set to be 120g, and the polishing solution is formed by mixing 3-micron aluminum oxide powder and deionized water according to the weight of 1: 10; placing the glass plate on a clamp, starting polishing until the thickness of the compound semiconductor wafer is reduced to be less than 200 micrometers, and stopping polishing to enable the surface of the compound semiconductor crystal to be frosted; then the polishing disk is replaced by a flannelette disk, the pressure of the clamp is adjusted to 230g, the polishing solution is still formed by mixing 3-micron aluminum oxide powder and deionized water according to the weight ratio of 1:10, and the polishing is stopped after at least 10 minutes, so that the surface of the compound semiconductor crystal has no obvious scratch;
finally, performing physical and chemical polishing by using a PM6 physical and chemical polishing machine, wherein the polishing solution is a chemical polishing solution, the pressure of a clamp is set to be 50g, and polishing is started until no visible scratches exist on the surface of the compound semiconductor crystal; and then soaking the glass plate and the compound semiconductor crystal in a paraffin removal solution until the compound semiconductor crystal falls off from the surface of the glass plate, washing the compound semiconductor crystal with deionized water for at least 2 minutes, and drying to obtain a clean compound semiconductor wafer, thereby completing the surface treatment process of the compound semiconductor wafer.
As a preferred technical solution of the present invention, in the step c, when the graphene is transferred to the surface of the compound semiconductor crystal or the silicon wafer, the specific steps are as follows:
adopting suspended self-help transfer graphene, releasing the graphene coated with a PMMA protective film in deionized water, contacting the surface treated by a compound semiconductor crystal or a silicon wafer with a graphene plane in the deionized water, taking out the graphene from the deionized water, airing the graphene in the air for at least 20 minutes, then drying the graphene for at least 30 minutes in an environment at the temperature of not higher than 70 ℃, then taking out the compound semiconductor crystal or the silicon wafer, and cooling the graphene to room temperature; and preparing two parts of acetone solution, soaking the compound semiconductor crystal or the silicon wafer in the first part of acetone for at least 10 minutes, taking out the compound semiconductor crystal or the silicon wafer, transferring the compound semiconductor crystal or the silicon wafer into the second part of acetone, soaking for at least 30 minutes, and removing PMMA (polymethyl methacrylate) to completely transfer and combine graphene on the surface of the crystal.
Compared with the prior art, the invention has the following obvious and prominent substantive characteristics and remarkable advantages:
1. according to the method, graphene is introduced as a bonding medium layer in the process of bonding CdZnTe and silicon, the temperature required by the adopted bonding method is low, and part of the process can be carried out at room temperature; the graphene can effectively improve the surface roughness of the crystal and reduce the requirement of bonding on the surface roughness of the crystal; ohmic contact is formed between the graphene and the CdZnTe crystal, so that electron transmission is facilitated, and the effect that the graphene has an electron transmission layer is realized;
2. the method is simple and easy to implement, low in cost and suitable for popularization and application.
Drawings
FIG. 1 is a schematic diagram of a CdZnTe and Graphene/Si bonded wafer prepared by a method according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of a wafer after bonding Graphene/CZT and Si prepared by the second method of the embodiment of the invention.
FIG. 3 is a schematic diagram of a wafer after bonding of Graphene/Si and Graphene/CZT prepared by the third method according to the embodiment of the present invention.
Detailed Description
The above-described scheme is further illustrated below with reference to specific embodiments, which are detailed below:
the first embodiment is as follows:
in this embodiment, a low-temperature bonding method of a silicon wafer and a compound semiconductor wafer includes the steps of:
a. silicon chip pretreatment:
preparing a silicon wafer, and cleaning the silicon wafer by a standard RCA chemical cleaning method, wherein the method comprises the following steps:
preparing cleaning solution I, solution II and solution III for cleaning:
the solution I is organic matter cleaning solution which is prepared by mixing 27% ammonia water, 30% hydrogen peroxide and deionized water in a volume ratio of 1:1: 5;
the solution II is an oxide removing solution, and is prepared by mixing hydrofluoric acid with the mass concentration of 50% and deionized water according to the volume ratio of 1: 50;
the solution III is an ionic cleaning solution, and is prepared by mixing hydrochloric acid with the mass concentration of 37%, hydrogen peroxide with the mass concentration of 30% and deionized water according to the volume ratio of 1:1: 6;
the silicon wafer is sequentially subjected to the following cleaning processes:
firstly, immersing a silicon wafer into the solution I, immersing for 10 minutes at 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes; then, soaking the silicon wafer in the solution II for 30 seconds at normal temperature, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes; and finally, soaking the silicon wafer in the solution III for 10 minutes at 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes to complete the silicon wafer cleaning process to obtain a clean silicon wafer.
Surface treatment of CdZnTe wafer:
preparing a CdZnTe wafer, chamfering the CdZnTe crystal to smooth the peripheral corners, and then carrying out physical polishing and chemical mechanical polishing surface treatment processes, wherein the steps are as follows:
adhering CdZnTe crystal to a glass plate by using wax, taking care that the CdZnTe crystal is symmetrically distributed on the glass plate, using a PM6 physical polishing instrument to carry out primary polishing, wherein a glass plate is selected as a polishing plate, the pressure of a clamp is set to be 120g, and polishing solution is formed by mixing 3-micron aluminum oxide powder and deionized water according to the weight ratio of 1: 10; placing the glass plate on a clamp, and polishing until the thickness of the CdZnTe wafer is reduced to a value less than 200 microns, so that the surface of the CdZnTe crystal is frosted; then replacing the polishing disk with a flannelette disk, adjusting the pressure of the clamp to 230g, mixing polishing solution which is 3 microns of alumina powder and deionized water according to the weight ratio of 1:10, and stopping polishing after at least 10 minutes to ensure that no obvious scratch is formed on the surface of the CdZnTe crystal;
finally, performing physical and chemical polishing by using a PM6 physical and chemical polishing machine, wherein the polishing solution is a chemical polishing solution, the pressure of a clamp is set to be 50g, and polishing is started until no visible scratches are formed on the surface of the CdZnTe crystal; then soaking the glass plate and the CdZnTe crystal in paraffin removal liquid until the CdZnTe crystal falls off from the surface of the glass plate, then washing the CdZnTe crystal with deionized water for 2 minutes, and drying to obtain a clean CdZnTe wafer, thereby completing the surface treatment process of the CdZnTe wafer;
c. bonding process of silicon wafer and CdZnTe wafer:
adopting suspended self-help transfer graphene, releasing the graphene coated with a PMMA protective film in deionized water, contacting the surface treated by CdZnTe crystal and a silicon wafer with a graphene plane in the deionized water, taking out the graphene from the deionized water, airing the graphene for 20 minutes in the air, then drying the graphene for 30 minutes at 70 ℃, then taking out the compound semiconductor crystal and the silicon wafer, and cooling the compound semiconductor crystal and the silicon wafer to room temperature; preparing two parts of acetone solution, soaking the CdZnTe crystal and the silicon wafer in the first part of acetone for 10 minutes, taking out the CdZnTe crystal and the silicon wafer, transferring the CdZnTe crystal and the silicon wafer into the second part of acetone, soaking the CdZnTe crystal for 30 minutes, and removing PMMA (polymethyl methacrylate) to completely transfer and combine graphene to the surface of the CdZnTe crystal;
when the low-temperature bonding process of the silicon wafer and the CdZnTe wafer is carried out, graphene is adopted as an intermediate medium material, the graphene is coated on the surface of the silicon wafer, and the silicon wafer and the CdZnTe wafer are cleaned in deionized water and then are dried by nitrogen; and then attaching the surface of the Si crystal coated with Graphene on the surface and the surface of the CdZnTe crystal wafer, reversely buckling the Graphene/Si crystal wafer on the surface of the CZT crystal wafer to form a combined layer structure in a silicon-Graphene-CdZnTe form, and then carrying out low-temperature annealing bonding treatment for 22h at the temperature of 150 ℃ to enable the Graphene layer to form an electron transport layer, thereby preparing the silicon wafer and CdZnTe wafer bonded wafer device. Referring to fig. 1, fig. 1 is a schematic diagram of a wafer after CdZnTe and Graphene/Si bonding prepared by the method of this embodiment, and as can be seen from fig. 1, this embodiment bonds a ii-vi compound semiconductor CZT and Si, uses a two-dimensional material Graphene as an intermediate medium, and functions as an electron transport layer in CZT and Si. In the embodiment, a new substance graphene is adopted as a bonding medium, so that the bonding of CdZnTe and silicon is realized, the excessively high bonding temperature is avoided, and the problem of direct bonding caused by the fact that the thermal expansion coefficient of CdZnTe is much larger than that of silicon is solved. The graphene can effectively improve the surface roughness of the crystal and reduce the requirement of bonding on the surface roughness of the crystal; ohmic contact is formed between the graphene and the CdZnTe crystal, so that electron transmission is facilitated, the effect that the graphene has an electron transmission layer is realized, the bonding quality is high, and the performance is excellent.
Example two:
this embodiment is substantially the same as the first embodiment, and is characterized in that:
in this embodiment, a low-temperature bonding method of a silicon wafer and a compound semiconductor wafer includes the steps of:
a. silicon chip pretreatment:
preparing a silicon wafer, and cleaning the silicon wafer by a standard RCA chemical cleaning method, wherein the method comprises the following steps:
preparing cleaning solution I, solution II and solution III for cleaning:
the solution I is organic matter cleaning solution which is prepared by mixing 27% ammonia water, 30% hydrogen peroxide and deionized water in a volume ratio of 1:1: 5;
the solution II is an oxide removing solution, and is prepared by mixing hydrofluoric acid with the mass concentration of 50% and deionized water according to the volume ratio of 1: 50;
the solution III is an ionic cleaning solution, and is prepared by mixing hydrochloric acid with the mass concentration of 37%, hydrogen peroxide with the mass concentration of 30% and deionized water according to the volume ratio of 1:1: 6;
the silicon wafer is sequentially subjected to the following cleaning processes:
firstly, immersing a silicon wafer into the solution I, immersing for 10 minutes at 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes; then, soaking the silicon wafer in the solution II for 30 seconds at normal temperature, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes; and finally, soaking the silicon wafer in the solution III for 10 minutes at 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes to complete the silicon wafer cleaning process to obtain a clean silicon wafer.
Surface treatment of CdZnTe wafer:
preparing a CdZnTe wafer, chamfering the CdZnTe crystal to smooth the peripheral corners, and then carrying out physical polishing and chemical mechanical polishing surface treatment processes, wherein the steps are as follows:
adhering CdZnTe crystal to a glass plate by using wax, taking care that the CdZnTe crystal is symmetrically distributed on the glass plate, using a PM6 physical polishing instrument to carry out primary polishing, wherein a glass plate is selected as a polishing plate, the pressure of a clamp is set to be 120g, and polishing solution is formed by mixing 3-micron aluminum oxide powder and deionized water according to the weight ratio of 1: 10; placing the glass plate on a clamp, and polishing until the thickness of the CdZnTe wafer is reduced to a value less than 200 microns, so that the surface of the CdZnTe crystal is frosted; then replacing the polishing disk with a flannelette disk, adjusting the pressure of the clamp to 230g, mixing polishing solution which is 3 microns of alumina powder and deionized water according to the weight ratio of 1:10, and stopping polishing after at least 10 minutes to ensure that no obvious scratch is formed on the surface of the CdZnTe crystal;
finally, performing physical and chemical polishing by using a PM6 physical and chemical polishing machine, wherein the polishing solution is a chemical polishing solution, the pressure of a clamp is set to be 50g, and polishing is started until no visible scratches are formed on the surface of the CdZnTe crystal; then soaking the glass plate and the CdZnTe crystal in paraffin removal liquid until the CdZnTe crystal falls off from the surface of the glass plate, then washing the CdZnTe crystal with deionized water for 2 minutes, and drying to obtain a clean CdZnTe wafer, thereby completing the surface treatment process of the CdZnTe wafer;
c. bonding process of silicon wafer and CdZnTe wafer:
adopting suspended self-help transfer graphene, releasing the graphene coated with a PMMA protective film in deionized water, contacting the surface treated by CdZnTe crystal and a silicon wafer with a graphene plane in the deionized water, taking out the graphene from the deionized water, airing the graphene for 20 minutes in the air, then drying the graphene for 30 minutes at 70 ℃, then taking out the compound semiconductor crystal and the silicon wafer, and cooling the compound semiconductor crystal and the silicon wafer to room temperature; preparing two parts of acetone solution, soaking the CdZnTe crystal and the silicon wafer in the first part of acetone for 10 minutes, taking out the CdZnTe crystal and the silicon wafer, transferring the CdZnTe crystal and the silicon wafer into the second part of acetone, soaking the CdZnTe crystal for 30 minutes, and removing PMMA (polymethyl methacrylate) to completely transfer and combine graphene to the surface of the CdZnTe crystal;
when the low-temperature bonding process of the silicon wafer and the CdZnTe wafer is carried out, graphene is adopted as an intermediate medium material, the graphene is transferred to the surface of the CdZnTe wafer, the graphene is coated on the surface of the CdZnTe wafer, and the silicon wafer and the CdZnTe wafer are cleaned in deionized water and then are dried by using nitrogen; and then adhering the CdZnTe surface with the surface coated with Graphene to the crystal surface of the silicon wafer, reversely buckling the Si wafer on the surface of the Graphene/CZT wafer to form a combined layer structure in the form of silicon-Graphene-CdZnTe, and then carrying out low-temperature annealing bonding treatment for 22h at the temperature of 150 ℃ to enable the Graphene layer to form an electron transport layer, thereby preparing the silicon wafer and compound semiconductor wafer bonded wafer device. Referring to fig. 2, fig. 2 is a schematic view of a wafer after bonding of Graphene/CZT and Si prepared by the method of the present embodiment. In the embodiment, a new substance graphene is adopted as a bonding medium, so that the bonding of CdZnTe and silicon is realized, the excessively high bonding temperature is avoided, and the problem of direct bonding caused by the fact that the thermal expansion coefficient of CdZnTe is much larger than that of silicon is solved. The graphene can effectively improve the surface roughness of the crystal and reduce the requirement of bonding on the surface roughness of the crystal; ohmic contact is formed between the graphene and the CdZnTe crystal, so that electron transmission is facilitated, the effect that the graphene has an electron transmission layer is realized, the bonding quality is high, and the performance is excellent.
Example three:
this embodiment is substantially the same as the previous embodiment, and is characterized in that:
in this embodiment, a low-temperature bonding method of a silicon wafer and a compound semiconductor wafer includes the steps of:
a. silicon chip pretreatment:
preparing a silicon wafer, and cleaning the silicon wafer by a standard RCA chemical cleaning method, wherein the method comprises the following steps:
preparing cleaning solution I, solution II and solution III for cleaning:
the solution I is organic matter cleaning solution which is prepared by mixing 27% ammonia water, 30% hydrogen peroxide and deionized water in a volume ratio of 1:1: 5;
the solution II is an oxide removing solution, and is prepared by mixing hydrofluoric acid with the mass concentration of 50% and deionized water according to the volume ratio of 1: 50;
the solution III is an ionic cleaning solution, and is prepared by mixing hydrochloric acid with the mass concentration of 37%, hydrogen peroxide with the mass concentration of 30% and deionized water according to the volume ratio of 1:1: 6;
the silicon wafer is sequentially subjected to the following cleaning processes:
firstly, immersing a silicon wafer into the solution I, immersing for 10 minutes at 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes; then, soaking the silicon wafer in the solution II for 30 seconds at normal temperature, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes; and finally, soaking the silicon wafer in the solution III for 10 minutes at 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for 2 minutes to complete the silicon wafer cleaning process to obtain a clean silicon wafer.
Surface treatment of CdZnTe wafer:
preparing a CdZnTe wafer, chamfering the CdZnTe crystal to smooth the peripheral corners, and then carrying out physical polishing and chemical mechanical polishing surface treatment processes, wherein the steps are as follows:
adhering CdZnTe crystal to a glass plate by using wax, taking care that the CdZnTe crystal is symmetrically distributed on the glass plate, using a PM6 physical polishing instrument to carry out primary polishing, wherein a glass plate is selected as a polishing plate, the pressure of a clamp is set to be 120g, and polishing solution is formed by mixing 3-micron aluminum oxide powder and deionized water according to the weight ratio of 1: 10; placing the glass plate on a clamp, and polishing until the thickness of the CdZnTe wafer is reduced to a value less than 200 microns, so that the surface of the CdZnTe crystal is frosted; then replacing the polishing disk with a flannelette disk, adjusting the pressure of the clamp to 230g, mixing polishing solution which is 3 microns of alumina powder and deionized water according to the weight ratio of 1:10, and stopping polishing after at least 10 minutes to ensure that no obvious scratch is formed on the surface of the CdZnTe crystal;
finally, performing physical and chemical polishing by using a PM6 physical and chemical polishing machine, wherein the polishing solution is a chemical polishing solution, the pressure of a clamp is set to be 50g, and polishing is started until no visible scratches are formed on the surface of the CdZnTe crystal; then soaking the glass plate and the CdZnTe crystal in paraffin removal liquid until the CdZnTe crystal falls off from the surface of the glass plate, then washing the CdZnTe crystal with deionized water for 2 minutes, and drying to obtain a clean CdZnTe wafer, thereby completing the surface treatment process of the CdZnTe wafer;
c. bonding process of silicon wafer and CdZnTe wafer:
adopting suspended self-help transfer graphene, releasing the graphene coated with a PMMA protective film in deionized water, contacting the surface treated by CdZnTe crystal and a silicon wafer with a graphene plane in the deionized water, taking out the graphene from the deionized water, airing the graphene for 20 minutes in the air, then drying the graphene for 30 minutes at 70 ℃, then taking out the compound semiconductor crystal and the silicon wafer, and cooling the compound semiconductor crystal and the silicon wafer to room temperature; preparing two parts of acetone solution, soaking the CdZnTe crystal and the silicon wafer in the first part of acetone for 10 minutes, taking out the CdZnTe crystal and the silicon wafer, transferring the CdZnTe crystal and the silicon wafer into the second part of acetone, soaking the CdZnTe crystal for 30 minutes, and removing PMMA (polymethyl methacrylate) to completely transfer and combine graphene to the surface of the CdZnTe crystal;
when the low-temperature bonding process of the silicon wafer and the CdZnTe wafer is carried out, graphene is adopted as an intermediate medium material, the graphene is respectively transferred to the surface of the CdZnTe wafer and the surface of the CdZnTe wafer, the graphene is respectively coated on the surface of the CdZnTe wafer and the surface of the silicon wafer, and the silicon wafer and the CdZnTe wafer are cleaned in deionized water and then are dried by nitrogen; and then adhering the CdZnTe surface coated with Graphene on the surface and the crystal surface of the silicon wafer coated with Graphene on the surface, reversely buckling the Graphene/Si wafer on the Graphene/CZT wafer surface to form a silicon-Graphene-CdZnTe-form combined layer structure, and then carrying out low-temperature annealing bonding treatment for 22h at the temperature of 150 ℃ to enable the Graphene layer to form an electron transport layer, thereby preparing the silicon wafer and compound semiconductor wafer bonded wafer device. Referring to fig. 3, fig. 3 is a schematic view of the wafer after Graphene/Si and Graphene/CZT bonding prepared by the method of the present embodiment. In the embodiment, a new substance graphene is adopted as a bonding medium, so that the bonding of CdZnTe and silicon is realized, the excessively high bonding temperature is avoided, and the problem of direct bonding caused by the fact that the thermal expansion coefficient of CdZnTe is much larger than that of silicon is solved. The graphene can effectively improve the surface roughness of the crystal and reduce the requirement of bonding on the surface roughness of the crystal; ohmic contact is formed between the graphene and the CdZnTe crystal, so that electron transmission is facilitated, the effect that the graphene has an electron transmission layer is realized, the bonding quality is high, and the performance is excellent.
Example four:
this embodiment is substantially the same as the previous embodiment, and is characterized in that:
in this embodiment, when the low-temperature bonding process of the silicon wafer and the CdZnTe wafer is performed, graphene is used as an intermediate medium material, and the silicon wafer and the CdZnTe wafer are dried by using nitrogen after being cleaned in deionized water; then a graphene medium layer is sandwiched between the surface of the Si crystal and the surface of the CdZnTe wafer to form a combined layer structure in the form of silicon-graphene-CdZnTe, and then low-temperature annealing bonding treatment is carried out for 24 hours at the temperature of 100 ℃ to enable the graphene layer to form an electron transport layer, so that the silicon wafer and CdZnTe wafer bonded wafer device is prepared. In this example, a ii-vi compound semiconductor CZT is bonded to Si, and graphene, which is a two-dimensional material, is used as an intermediate medium to function as an electron transport layer in CZT and Si. In the embodiment, a new substance graphene is adopted as a bonding medium, so that the bonding of CdZnTe and silicon is realized, the excessively high bonding temperature is avoided, and the problem of direct bonding caused by the fact that the thermal expansion coefficient of CdZnTe is much larger than that of silicon is solved. The graphene can effectively improve the surface roughness of the crystal and reduce the requirement of bonding on the surface roughness of the crystal; ohmic contact is formed between the graphene and the CdZnTe crystal, so that electron transmission is facilitated, the effect that the graphene has an electron transmission layer is realized, the bonding quality is high, and the performance is excellent.
Example five:
this embodiment is substantially the same as the previous embodiment, and is characterized in that:
in this embodiment, when the low-temperature bonding process of the silicon wafer and the CdZnTe wafer is performed, graphene is used as an intermediate medium material, and the silicon wafer and the CdZnTe wafer are dried by using nitrogen after being cleaned in deionized water; and then sandwiching a graphene medium layer between the surface of the Si crystal and the surface of the CdZnTe wafer to form a combined layer structure in the form of silicon-graphene-CdZnTe, and then carrying out low-temperature annealing bonding treatment for 20 hours at the temperature of 250 ℃ to enable the graphene layer to form an electron transport layer, thereby preparing the silicon wafer and CdZnTe wafer bonded wafer device. In this example, a ii-vi compound semiconductor CZT is bonded to Si, and graphene, which is a two-dimensional material, is used as an intermediate medium to function as an electron transport layer in CZT and Si. In the embodiment, a new substance graphene is adopted as a bonding medium, so that the bonding of CdZnTe and silicon is realized, the excessively high bonding temperature is avoided, and the problem of direct bonding caused by the fact that the thermal expansion coefficient of CdZnTe is much larger than that of silicon is solved. The graphene can effectively improve the surface roughness of the crystal and reduce the requirement of bonding on the surface roughness of the crystal; ohmic contact is formed between the graphene and the CdZnTe crystal, so that electron transmission is facilitated, the effect that the graphene has an electron transmission layer is realized, the bonding quality is high, and the performance is excellent.
While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but various changes may be made in accordance with the objects of the invention, and any changes, modifications, substitutions, combinations or simplifications made in accordance with the spirit and principles of the present invention shall be equivalent substitutions, and fall within the scope of the invention as long as the technical principles and inventive concepts of the low temperature bonding method of silicon wafer and compound semiconductor wafer according to the present invention are met.

Claims (7)

1. A low-temperature bonding method of a silicon wafer and a compound semiconductor wafer is characterized in that: the method comprises the following steps:
a. silicon chip pretreatment:
preparing a silicon wafer, and cleaning the silicon wafer by a chemical cleaning method to obtain a clean silicon wafer;
b. surface treatment of compound semiconductor wafer:
preparing a compound semiconductor wafer, chamfering the compound semiconductor crystal, and then performing physical polishing and chemical mechanical polishing surface treatment processes to enable the crystal surface of the compound semiconductor wafer to have no visible scratches and finish the surface treatment of the compound semiconductor wafer;
c. bonding process of silicon wafer and compound semiconductor wafer:
adopting any one of the following three modes of bonding a silicon wafer and a compound semiconductor wafer:
the first method is as follows: b, taking graphene as an intermediate medium material, transferring the graphene to the surface of the silicon wafer pretreated in the step a, coating the graphene on the surface of the silicon wafer, cleaning the silicon wafer and the compound semiconductor wafer subjected to surface treatment in the step b in deionized water, and drying; then, attaching the surface of the Si crystal with the surface coated with graphene to the surface of the crystal of the compound semiconductor wafer to form a combined layer structure in a silicon-graphene-compound semiconductor form, and then carrying out low-temperature annealing bonding at the temperature of not higher than 250 ℃ to enable the graphene layer to form an electron transport layer, thereby preparing a silicon wafer and compound semiconductor wafer bonded wafer device;
the second method comprises the following steps: transferring graphene to the surface of the compound semiconductor wafer subjected to the surface treatment in the step b by using the graphene as an intermediate medium material, coating the graphene on the surface of the compound semiconductor wafer, and cleaning the silicon wafer and the compound semiconductor wafer pretreated in the step a in deionized water and then drying the silicon wafer and the compound semiconductor wafer; then, adhering the surface of a compound semiconductor with the surface coated with graphene to the surface of a crystal of a silicon wafer to form a combined layer structure in the form of a silicon-graphene-compound semiconductor, and then carrying out low-temperature annealing bonding at the temperature of not higher than 250 ℃ to enable a graphene layer to form an electron transport layer, thereby preparing a silicon wafer and compound semiconductor wafer bonded wafer device;
the third method comprises the following steps: respectively transferring graphene to the surface of the compound semiconductor wafer subjected to the surface treatment in the step b and the surface of the compound semiconductor wafer subjected to the surface treatment in the step b by using the graphene as an intermediate medium material, respectively coating the graphene on the surface of the compound semiconductor wafer and the surface of a silicon wafer, cleaning the silicon wafer and the compound semiconductor wafer in deionized water, and drying; and then, adhering the surface of the compound semiconductor with the surface coated with the graphene to the surface of the crystal of the silicon wafer with the surface coated with the graphene to form a combined layer structure in the form of a silicon-graphene-compound semiconductor, and then carrying out low-temperature annealing bonding at the temperature of not higher than 250 ℃ to enable the graphene layer to form an electron transport layer, thereby preparing the silicon wafer and compound semiconductor wafer bonded wafer device.
2. The low-temperature bonding method of a silicon wafer and a compound semiconductor wafer according to claim 1, characterized in that: in the step c, when the low-temperature annealing bonding is performed, the annealing temperature is 100-250 ℃, and the annealing time is 20-24 h.
3. The low-temperature bonding method of a silicon wafer and a compound semiconductor wafer according to claim 1, characterized in that: in the step B, the compound semiconductor wafer adopts a IIB-VIA group semiconductor or a IIIB-VA group semiconductor.
4. The low-temperature bonding method of a silicon wafer and a compound semiconductor wafer according to claim 3, characterized in that: in the step b, CdZnTe is adopted as the compound semiconductor wafer.
5. The low-temperature bonding method of a silicon wafer and a compound semiconductor wafer according to claim 1, characterized in that: in the step a, the silicon wafer is cleaned by a chemical cleaning method, and the method comprises the following steps:
preparing cleaning solution I, solution II and solution III for cleaning:
the solution I is organic matter cleaning solution, and is prepared by mixing ammonia water with the mass concentration not lower than 27%, hydrogen peroxide with the mass concentration not lower than 30% and deionized water according to the volume ratio of 1:1: 5;
the solution II is an oxide removing solution, and is prepared by mixing hydrofluoric acid with the mass concentration not lower than 50% and deionized water according to the volume ratio of 1: 50;
the solution III is an ionic cleaning solution, and is prepared by mixing hydrochloric acid with the mass concentration not lower than 37%, hydrogen peroxide with the mass concentration not lower than 30% and deionized water according to the volume ratio of 1:1: 6;
the silicon wafer is sequentially subjected to the following cleaning processes:
firstly, immersing a silicon wafer into the solution I, immersing for at least 10 minutes at the temperature of not higher than 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for at least 2 minutes; then, soaking the silicon wafer in the solution II for at least 30 seconds at normal temperature, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for at least 2 minutes; and finally, soaking the silicon wafer in the solution III for at least 10 minutes at the temperature of not higher than 70 ℃, taking out the silicon wafer, and then putting the silicon wafer into deionized water for cleaning for at least 2 minutes to finish the silicon wafer cleaning process.
6. The low-temperature bonding method of a silicon wafer and a compound semiconductor wafer according to claim 1, characterized in that: in the step b, when the surface treatment of the compound semiconductor wafer is carried out, the compound semiconductor wafer is chamfered to smooth the peripheral corners; adhering the compound semiconductor crystal to a glass plate by using wax, and performing primary polishing by using a PM6 physical polishing instrument, wherein the polishing plate is a glass plate, the pressure of a clamp is set to be 120g, and the polishing solution is formed by mixing 3-micron aluminum oxide powder and deionized water according to the weight of 1: 10; placing the glass plate on a clamp, starting polishing until the thickness of the compound semiconductor wafer is reduced to be less than 200 micrometers, and stopping polishing to enable the surface of the compound semiconductor crystal to be frosted; then the polishing disk is replaced by a flannelette disk, the pressure of the clamp is adjusted to 230g, the polishing solution is still formed by mixing 3-micron aluminum oxide powder and deionized water according to the weight ratio of 1:10, and the polishing is stopped after at least 10 minutes, so that the surface of the compound semiconductor crystal has no obvious scratch;
finally, performing physical and chemical polishing by using a PM6 physical and chemical polishing machine, wherein the polishing solution is a chemical polishing solution, the pressure of a clamp is set to be 50g, and polishing is started until no visible scratches exist on the surface of the compound semiconductor crystal; and then soaking the glass plate and the compound semiconductor crystal in a paraffin removal solution until the compound semiconductor crystal falls off from the surface of the glass plate, washing the compound semiconductor crystal with deionized water for at least 2 minutes, and drying to obtain a clean compound semiconductor wafer, thereby completing the surface treatment process of the compound semiconductor wafer.
7. The low-temperature bonding method of a silicon wafer and a compound semiconductor wafer according to claim 1, characterized in that: in the step c, when the graphene is transferred to the surface of the compound semiconductor crystal or the silicon wafer, the specific steps are as follows:
adopting suspended self-help transfer graphene, releasing the graphene coated with a PMMA protective film in deionized water, contacting the surface treated by a compound semiconductor crystal or a silicon wafer with a graphene plane in the deionized water, taking out the graphene from the deionized water, airing the graphene in the air for at least 20 minutes, then drying the graphene for at least 30 minutes in an environment at the temperature of not higher than 70 ℃, then taking out the compound semiconductor crystal or the silicon wafer, and cooling the graphene to room temperature; and preparing two parts of acetone solution, soaking the compound semiconductor crystal or the silicon wafer in the first part of acetone for at least 10 minutes, taking out the compound semiconductor crystal or the silicon wafer, transferring the compound semiconductor crystal or the silicon wafer into the second part of acetone, soaking for at least 30 minutes, and removing PMMA (polymethyl methacrylate) to completely transfer and combine graphene on the surface of the crystal.
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