CN112992708B - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN112992708B CN112992708B CN201911294734.4A CN201911294734A CN112992708B CN 112992708 B CN112992708 B CN 112992708B CN 201911294734 A CN201911294734 A CN 201911294734A CN 112992708 B CN112992708 B CN 112992708B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 141
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 181
- 230000004888 barrier function Effects 0.000 claims abstract description 108
- 238000000034 method Methods 0.000 claims abstract description 69
- 238000001514 detection method Methods 0.000 claims abstract description 56
- 230000000903 blocking effect Effects 0.000 claims abstract description 3
- 238000005498 polishing Methods 0.000 claims description 48
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 15
- 230000015572 biosynthetic process Effects 0.000 abstract description 12
- 238000007517 polishing process Methods 0.000 description 12
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- 239000007789 gas Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises an element layer, a first insulating layer and a dielectric layer which are sequentially formed, wherein the dielectric layer comprises an etching blocking layer and a first dielectric layer which are positioned on the surface of the first insulating layer, and the dielectric layer is provided with a second through hole, and the method comprises the following steps: detecting the semiconductor device after the etching barrier layer is formed and before the second through hole is formed, and obtaining a detection result of the semiconductor device; if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer; regrowing a dielectric layer on one side of the surface of the first insulating layer, which is away from the element layer; and until the detection result of the semiconductor device meets a first condition, reducing the probability of influencing the yield of the semiconductor device due to the defect of the formation of a dielectric layer in the semiconductor device, thereby improving the yield of the semiconductor device.
Description
Technical Field
The application relates to the technical field of semiconductor device manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
With the development of semiconductor technology, the semiconductor chip manufacturing industry is also growing, so the quality requirements of the market on the semiconductor chips are also increasing.
At present, the production of semiconductor chips is mass production, and each semiconductor chip is completed by thousands of processes, such as film, photoetching, etching, polishing and the like, and the final yield and reliability of the whole semiconductor chip are inevitably affected by any one process, so that the yield of the finished product of the existing semiconductor chip is lower.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a manufacturing method of a semiconductor device, so as to improve the yield of the semiconductor device.
In order to achieve the above purpose, the present application provides the following technical solutions:
The manufacturing method of the semiconductor device comprises an element layer, a first insulating layer positioned on the surface of a first side of the element layer and a dielectric layer positioned on one side of the first insulating layer, which is away from the element layer, wherein at least one first through hole is formed in the first insulating layer, a first plug connector electrically connected with the element layer is filled in the first through hole, the dielectric layer comprises an etching blocking layer and a first dielectric layer positioned on the surface of the first insulating layer, and the dielectric constant of the first dielectric layer is smaller than 4F/m; the manufacturing method comprises the following steps:
Step 1: in the process of forming the dielectric layer, detecting the semiconductor device at preset time to obtain a detection result of the semiconductor device;
step 2: if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer;
Step 3: regrowing the dielectric layer on the side of the surface of the first insulating layer, which is away from the element layer;
step 4: repeating the steps 1-3 until the detection result of the semiconductor device meets a first condition;
The dielectric layer is provided with a second through hole, the second through hole is filled with a second plug connector electrically connected with the first plug connector, and the preset time is after the etching barrier layer is formed and before the second through hole is formed in the dielectric layer.
Optionally, after step 2, before step 3, the method further includes:
and polishing the first insulating layer for a first time, and removing part of the first insulating layer and part of the first plug connector.
Optionally, the value range of the first time is 1s-4s, including the endpoint value.
Optionally, after the etching stop layer is manufactured, before the first dielectric layer is formed, if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer includes:
If the detection result of the semiconductor device does not meet the first condition and the thickness of the etching barrier layer is smaller than a first preset value, forming a buffer layer on the surface of the etching barrier layer;
Polishing the buffer layer and the etching barrier layer until the etching barrier layer is removed;
Wherein the hardness of the buffer layer is less than the hardness of the etch stop layer and not greater than the hardness of the first dielectric layer, and the texture of the buffer layer is softer than the etch stop layer and not softer than the texture of the first dielectric layer.
Optionally, the buffer layer is an ethyl silicate layer.
Optionally, after the forming of the first dielectric layer for the preset time, if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer includes:
etching part of the first dielectric layer, and reserving the first dielectric layer with the first thickness;
polishing the first dielectric layer with the first thickness and the etching barrier layer until the etching barrier layer is removed;
wherein the first thickness is less than the thickness of the etch stop layer.
Optionally, the first thickness is no greater than 200 angstroms.
Optionally, the etching gas of the first dielectric layer is C 4F8、O2, ar or N 2.
Optionally, etching a portion of the first dielectric layer, and retaining the first dielectric layer with the first thickness includes:
etching the first dielectric layer with the second thickness;
Determining an etching rate of the first dielectric layer based on an etching process of the first dielectric layer of the second thickness;
continuing etching the rest part of the first dielectric layer for a second time by utilizing the etching rate of the first dielectric layer so as to keep the first dielectric layer with the first thickness;
Wherein the sum of the first thickness and the second thickness is less than the total thickness of the first dielectric layer.
Optionally, the second thickness is 1/2 of the total thickness of the first dielectric layer.
Optionally, the dielectric layer further includes a photoresist pattern located on a side of the first dielectric layer away from the etching barrier layer; the preset time is located after the photoresist pattern is formed, and if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer includes:
Removing the photoresist pattern;
etching part of the first dielectric layer, and reserving the first dielectric layer with the first thickness;
polishing the first dielectric layer with the first thickness and the etching barrier layer until the etching barrier layer is removed;
wherein the first thickness is less than the thickness of the etch stop layer.
Optionally, the dielectric layer further includes a first mask layer between the photoresist pattern and the first dielectric layer, and after removing the photoresist pattern, the method further includes, before etching a portion of the dielectric layer:
And removing the first mask layer.
Optionally, the first mask layer is a metal mask layer, and removing the first mask layer includes:
And removing the first mask layer by utilizing H 2O2.
In the technical scheme provided by the embodiment of the application, the semiconductor device comprises an element layer, a first insulating layer positioned on the surface of a first side of the element layer, and a dielectric layer positioned on one side of the first insulating layer away from the element layer, wherein the method comprises the following steps: in the process of forming the dielectric layer, detecting the semiconductor device at preset time to obtain a detection result of the semiconductor device; if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer; regrowing the dielectric layer on the side of the surface of the first insulating layer, which is away from the element layer; until the detection result of the semiconductor device meets a first condition, the probability of influencing the yield of the semiconductor device due to the defect of the formation of a dielectric layer in the semiconductor device is reduced, and the yield of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
Fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 3 is a flowchart of a method for fabricating a semiconductor device according to another embodiment of the present application;
fig. 4 is a flowchart of a method for fabricating a semiconductor device according to a first embodiment of the present application;
fig. 5 to 7 are cross-sectional views of structures involved in a method for manufacturing a semiconductor device according to a first embodiment of the present application;
Fig. 8 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment of the present application;
Fig. 9 to 11 are cross-sectional views of structures involved in a method for manufacturing a semiconductor device according to a second embodiment of the present application;
Fig. 12 is a flowchart of a method for manufacturing a semiconductor device according to a third embodiment of the present application;
Fig. 13 to 16 are cross-sectional views of structures involved in a method for manufacturing a semiconductor device according to a third embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
As described in the background section, the yield of the existing semiconductor chip is relatively low.
This is because, in a practical production line, the fabrication of semiconductor chips faces various potential threats occurring at any time, such as downtime, defects, malfunction, and the like. Specifically, in a thin film process commonly used in semiconductor chip manufacturing, if a defect or thickness abnormality occurs in a thin film in a growth process, a plurality of defect problems such as photoresist defocusing, etching stopping, polishing scratch and the like occur when a series of links such as subsequent photoetching, etching, polishing and the like are carried out, so that the semiconductor chip has the defect, and the yield of the semiconductor chip is affected. Moreover, these defects are often undetectable when the semiconductor chip is shipped, and once the defects are flown into the customer's hand, they have a great influence on the company's image.
Based on the above, the embodiment of the application provides a manufacturing method of a semiconductor device. The method for manufacturing the semiconductor device according to the embodiment of the present application for issue will be described below with reference to the drawings.
Referring to fig. 1, in the embodiment of the present application, the semiconductor device includes an element layer 1, a first insulating layer 2 located on a first side surface of the element layer 1, and a dielectric layer 3 located on a side of the first insulating layer 2 facing away from the element layer 1, where at least one first via 21 is located in the first insulating layer 2, a first plug 22 electrically connected to the element layer 1 is filled in the first via 21, a second via 33 is located in the dielectric layer 3, and a second plug 34 electrically connected to the first plug 21 is filled in the second via 33, where the dielectric layer 3 includes an etching stop layer 31 and a first dielectric layer 32 located on a surface of the first insulating layer 2, and a dielectric constant of the first dielectric layer 32 is less than 4F/m, which is not limited by the present application, so long as the first dielectric layer is a low-k material layer.
Referring to fig. 2, the embodiment of the application provides a method for manufacturing a semiconductor device, which includes:
Step 1: in the process of forming the dielectric layer 3, detecting the semiconductor device at preset time to obtain a detection result of the semiconductor device;
step 2: if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer 3;
step 3: regrowing the dielectric layer 3 on the side of the surface of the first insulating layer 2 facing away from the element layer 1;
step 4: repeating the steps 1-3 until the detection result of the semiconductor device meets a first condition;
Wherein the preset time is located after the formation of the etching stop layer 31 and before the formation of the second through hole 33 in the dielectric layer 3.
It should be noted that, in one embodiment of the present application, the first condition is that the performance of the semiconductor device meets the production requirement of the semiconductor chip, for example, the dielectric layer in the semiconductor device does not have defects such as surface polishing scratch, photoresist defocus, and the like.
On the basis of the above embodiment, in one embodiment of the present application, if the detection result of the semiconductor device does not satisfy the first condition, removing the dielectric layer 3 includes: if the detection result of the semiconductor device does not meet the first condition, the dielectric layer 3 is removed by using an etching process, but the application is not limited thereto, and in other embodiments of the application, the dielectric layer may be removed by using other processes, where appropriate.
Therefore, in the manufacturing method provided by the embodiment of the application, in the process that the dielectric layer is formed on one side of the first insulating layer, which is away from the element layer, the semiconductor device is detected at a preset time before the second through hole is formed in the dielectric layer, and the detection result of the semiconductor device is obtained; and if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer, and regrowing the dielectric layer on one side of the surface of the first insulating layer, which is away from the element layer, until the detection result of the semiconductor device meets the first condition, so as to reduce the probability of influencing the yield of the semiconductor device due to the defect of the formation of the dielectric layer in the semiconductor device, improve the yield of the semiconductor device, and further improve the customer satisfaction.
It should be noted that, in the process of removing the dielectric layer, damage is likely to be caused to the first insulating layer and the first plug connector located in the first insulating layer, so that in order to avoid forming a dielectric layer with good quality on the damaged first plug connector, the yield of the semiconductor device still cannot be effectively improved.
On the basis of the above embodiment, in one embodiment of the present application, as shown in fig. 3, the method further includes, after step 2 and before step 3:
Step 23: and polishing the first insulating layer for a first time, and removing part of the first insulating layer and part of the first plug connector so as to remove the first insulating layer and the damaged layer on the surface of the first plug connector, thereby reducing the probability of influencing the yield of the semiconductor device due to damage on the surfaces of the first insulating layer and the first plug connector.
Based on the above embodiment, in one embodiment of the present application, the value range of the first time is 1s-4s, including the endpoint value, so as to avoid excessive polishing of the first insulating layer and the first plug connector caused by excessively long polishing time, and insufficient polishing time, so that the damaged layers on the surfaces of the first insulating layer and the first plug connector cannot be completely removed.
Specifically, in one embodiment of the present application, the first time is 2s, but the present application is not limited thereto, and the present application is specifically limited thereto as the case may be.
On the basis of the above embodiments, in one embodiment of the present application, the first plug connector and the second plug connector are copper plugs; however, the present application is not limited thereto, and in other embodiments of the present application, the first connector and the second connector may be other conductive connectors, as long as the first connector and the second connector have good electrical conductivity.
As can be seen from the above, the method for manufacturing a semiconductor device according to the embodiment of the present application can reduce the probability of influencing the yield of the semiconductor device due to the defect of the formation of the dielectric layer in the semiconductor device, and improve the yield of the semiconductor device, thereby improving customer satisfaction.
It should be noted that, in the forming process of the dielectric layer, the preset time may be located after the growth of any one of the dielectric layers is completed, and the content of step 2 (removing the dielectric layer if the detection result of the semiconductor device does not meet the first condition) in the embodiment of the present application is described below with reference to a specific embodiment.
Embodiment one:
In the embodiment of the present application, the preset time is located after the etching stop layer 31 is manufactured and before the first dielectric layer 32 is formed, as shown in fig. 4, in the embodiment of the present application, if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer 3 includes:
step 211: referring to fig. 5, if the detection result of the semiconductor device does not meet the first condition and the thickness of the etching stopper is smaller than the first preset value, forming a buffer layer 4 on the surface of the etching stopper 31;
step 212: referring to fig. 6, the buffer layer 4 and the etch stopper 31 are polished until the etch stopper 31 is removed.
Specifically, in one embodiment of the present application, the first preset value is 200 angstroms, but the present application is not limited thereto, and the present application is specifically limited thereto as the case may be.
It should be noted that, the etching barrier layer in the dielectric layer is generally thinner, if the etching barrier layer is directly polished, the polishing time is shorter, and the control is not easy, so in the embodiment of the application, a buffer layer is formed on the surface of the etching barrier layer, and then the buffer layer and the etching barrier layer are polished, so as to control the polishing time.
On the basis of the above embodiment, in one embodiment of the present application, in order to avoid the excessively long polishing time for removing the dielectric layer due to the introduction of the buffer layer, in the embodiment of the present application, the hardness of the buffer layer 4 is smaller than the hardness of the etch stop layer 31 and not greater than the hardness of the first dielectric layer 32, and the texture of the buffer layer 4 is softer than the etch stop layer 31 and not softer than the texture of the first dielectric layer 32, so that the polishing process of the buffer layer has a faster polishing rate, thereby not excessively increasing the polishing time of the dielectric layer.
It should be noted that, because the removal rates of the buffer layer and the etch stop layer are different, in order to avoid that the removal rates of the buffer layer and the etch stop layer are different in the process of removing the buffer layer and the etch stop layer, the removal time of the dielectric layer is not well controlled, and the thickness of the buffer layer is not too large. Optionally, the thickness of the buffer layer is less than the thickness of the etch stop layer, and more preferably, the thickness of the buffer layer is no greater than 200 angstroms. The application is not limited thereto and is specifically applicable.
On the basis of any one of the foregoing embodiments, in one embodiment of the present application, forming a buffer layer on a surface of the etching stopper layer includes:
depositing a buffer layer on the surface of the etching barrier layer in a preset temperature range, wherein the preset temperature range is 400-550 ℃ and comprises an endpoint value, but the application is not limited to the above, and the application is specifically determined according to the situation;
specifically, on the basis of the foregoing embodiment, in one embodiment of the present application, the buffer layer is an ethyl silicate layer.
It should be noted that, due to the specific fabrication, the thickness of the etching barrier layer may have different thicknesses according to different processes and different materials according to different processes. Therefore, the thickness of the etching barrier layer may be smaller than or not smaller than the first preset value, and at this time, the removing time of the etching barrier layer is longer, and the etching barrier layer is easy to control.
Therefore, on the basis of any one of the foregoing embodiments, in one embodiment of the present application, if the detection result of the semiconductor device does not meet the first condition, and the thickness of the etching barrier layer is not less than the first preset value, removing the dielectric layer 3 may also include: and if the detection result of the semiconductor device does not meet the first condition, directly removing the dielectric layer 3.
Specifically, in one embodiment of the present application, the preset time is located after the etching stop layer 31 is manufactured, before the first dielectric layer 32 is formed, if the detection result of the semiconductor device does not meet the first condition, and the thickness of the etching stop layer is not less than a first preset value, removing the dielectric layer 3 includes:
If the detection result of the semiconductor device does not meet the first condition and the thickness of the etching barrier layer is greater than the first preset value, the etching barrier layer 31 is directly polished until the etching barrier layer 31 is removed.
Optionally, on the basis of the foregoing embodiment, in one embodiment of the present application, if the detection result of the semiconductor device does not meet the first condition and the thickness of the etching barrier layer is greater than a first preset value, directly polishing the etching barrier layer 31 until removing the etching barrier layer 31 includes:
Polishing the etching barrier layer with the third thickness, and reserving the etching barrier layer with the fourth thickness;
determining the polishing rate of the etching barrier layer based on the polishing process of the etching barrier layer with the third thickness;
And determining the polishing time of the rest etching barrier layers by utilizing the polishing rate of the etching barrier layers, and continuing polishing the etching barrier layers with the fourth thickness until the etching barrier layers are completely removed.
On the basis of the above embodiments, in one embodiment of the present application, the third thickness is 1/2 of the fourth thickness; in other embodiments of the present application, the third thickness may be 1/3, 2/5, etc. of the fourth thickness, which is not limited in this aspect, and only needs to ensure that the polishing rate of the etching barrier layer can be determined by polishing the etching barrier layer with the third thickness, which is not limited in this aspect, and is specific according to circumstances.
It should be noted that, the specific process parameters in the etching barrier layer polishing process are not limited in the present application, and are specific according to the situation.
It should be further noted that, in the above embodiment, the etching barrier layer is removed by using a polishing process as an example, but the application is not limited thereto, and in other embodiments of the application, other removing processes, such as an etching process, may be used to remove the etching barrier layer, and if there is a fear that the surface flatness formed by the etching process is to be improved, a method of etching before polishing may also be used, which is not limited thereto, and the application is specific to the situation.
Since the surface topography of the etching barrier layer may or may not be good (i.e., good flatness and uniformity) before the etching barrier layer is removed, in any of the above embodiments, if the surface topography of the etching barrier layer is good, the polishing is performed by using the same polishing parameters all the time during the polishing of the etching barrier layer; referring to fig. 7, if the surface topography of the etch stop layer is not good, the surface topography of the semiconductor device after the removal of the etch stop layer may be adjusted by adjusting the process parameters during the polishing of the etch stop layer.
Specifically, in one embodiment of the present application, when the surface morphology of the etching barrier layer is not good, the surface morphology of the semiconductor device after the etching barrier layer is removed is adjusted by adjusting the process parameters in the polishing process of the etching barrier layer, and if the detection result of the semiconductor device does not meet the first condition and the thickness of the etching barrier layer is greater than the first preset value, the polishing of the etching barrier layer 31 is directly performed until the removal of the etching barrier layer 3 includes:
based on the surface morphology of the etching barrier layer, adjusting the polishing pressure of each area on the surface of the etching barrier layer, polishing the etching barrier layer for the first time, and polishing away part of the etching barrier layer to ensure that the surface morphology of the etching barrier layer has better flatness and uniformity;
And polishing the rest of the etching barrier layer by adopting a conventional polishing process until the etching barrier layer is removed. Specifically, in the conventional polishing process, the polishing pressure of each area on the surface of the etching barrier layer is the same.
Therefore, according to the manufacturing method of the semiconductor device, the polishing process of the etching barrier layer is divided into two steps, the surface morphology of the etching barrier layer is changed while the thickness of the etching barrier layer is removed through polishing in the first step, and the etching barrier layer is completely removed through polishing in the second step, so that the flatness and uniformity of the surface of the regrown dielectric layer are good. The application is not limited thereto and is specifically applicable.
According to the manufacturing method of the semiconductor device, after the formation of the etching barrier layer on one side of the first insulating layer, which is away from the element layer, is completed, before the formation of the first dielectric layer, the semiconductor device is detected, and a detection result of the semiconductor device is obtained; if the detection result of the semiconductor device does not meet the first condition, removing the etching barrier layer; forming an etching barrier layer on one side of the first insulating layer, which is away from the element layer; and performing subsequent processes until the detection result of the semiconductor device meets the first condition, so as to reduce the probability of influencing the yield of the semiconductor device due to the defect of the formation of the dielectric layer in the semiconductor device, thereby improving the yield of the semiconductor device.
Embodiment two:
In the embodiment of the present application, the preset time is optionally after the first dielectric layer 32 is formed, and in the embodiment of the present application, the thickness of the etching stop layer is smaller than the first preset value, but the present application is not limited thereto, and is specifically defined as the case may be.
Specifically, in one embodiment of the present application, as shown in fig. 8, if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer 3 includes:
step 221: referring to fig. 9, a portion of the first dielectric layer 32 is etched, leaving a first dielectric layer 321 of a first thickness;
Step 222: referring to fig. 10, the first dielectric layer 321 and the etch stop layer 31 of the first thickness are polished until the etch stop layer 31 is removed.
It should be noted that, in the embodiment of the present application, if the etching barrier layer in the dielectric layer is thinner, the polishing time is shorter and the control is not good if the etching barrier layer is directly polished, so in the embodiment of the present application, only part of the first dielectric layer is removed and the first dielectric layer with the first thickness is remained in the process of etching the first dielectric layer, so that the first dielectric layer with the first thickness is used as a buffer layer on the surface of the etching barrier layer, and the first dielectric layer and the etching barrier layer are polished so as to control the polishing time. However, the present application is not limited thereto, and in other embodiments of the present application, if the detection result of the semiconductor device does not meet the first condition and the thickness of the etching barrier layer is greater than the first preset value, removing the dielectric layer 3 may also include: and if the detection result of the semiconductor device does not meet the first condition, firstly removing the first dielectric layer completely, and then removing the etching barrier layer, wherein the etching barrier layer is determined according to the situation.
Because the removal rate of the polishing process is smaller than that of the etching process, if the polishing process is directly used for removing the dielectric layer, the time for removing the dielectric layer is longer, so in the embodiment of the application, part of the first dielectric layer is removed by the etching process, and the rest of the first dielectric layer and the etching barrier layer are removed by the polishing process, so that the total removal time of the dielectric layer and the removal time control difficulty of the etching barrier layer are simultaneously considered.
It should be noted that, if the first dielectric layer with the first thickness is thicker, the removal time of the dielectric layer is longer, so the value of the first thickness is not too large.
Moreover, since the hardness of the first dielectric layer is smaller than that of the etching barrier layer, and the texture of the first dielectric layer is softer than that of the etching barrier layer, there is a difference in removal rates of the first dielectric layer and the etching barrier layer during polishing, and thus, if the first dielectric layer of the first thickness remains thicker, the difference in removal rates of the first dielectric layer and the etching barrier layer may also result in poor control of the removal time of the dielectric layer.
Therefore, on the basis of the above embodiment, in one embodiment of the present application, in order to avoid that the polishing time is too long and the removal time of the etching barrier layer is not well controlled when the first dielectric layer with the first thickness is removed due to the first dielectric layer remaining, the first thickness is smaller than the thickness of the etching barrier layer, and is optionally not greater than 200 angstroms, but the present application is not limited thereto, and the present application is specifically limited thereto as the case may be.
In addition, in the process of etching the first dielectric layer, the etching time of the first dielectric layer is generally controlled by adopting a theoretical etching rate, and in the actual etching process, the theoretical etching rate and the actual etching rate of the first dielectric layer may deviate, so that the first dielectric layer is removed by theoretical etching all the time for the surface, and an over-etching phenomenon is caused.
Etching the first dielectric layer with the second thickness;
Determining an etching rate of the first dielectric layer based on an etching process of the first dielectric layer of the second thickness;
and continuing etching the rest part of the first dielectric layer for a second time by utilizing the etching rate of the first dielectric layer so as to keep the first dielectric layer with the first thickness.
It should be noted that the method for calculating the second time includes: the etching time (denoted as first time) required by the first dielectric layer to remove the second thickness and the remaining thickness after the first dielectric layer to remain the first thickness is calculated based on the actual etching rate of the first dielectric layer and the remaining thickness after the first dielectric layer is removed from the second thickness and the first dielectric layer to remain the first thickness, and then the first time is subtracted by 2 seconds to remain the first dielectric layer of the first thickness.
On the basis of the above embodiments, in one embodiment of the present application, the second thickness is 1/2 of the total thickness of the first dielectric layer; alternatively, in other embodiments of the present application, the second thickness may be 1/3, 2/5, etc. of the total thickness of the first dielectric layer, which is only required to ensure that the actual etching rate of the first dielectric layer can be determined by etching the first dielectric layer with the second thickness.
Based on the foregoing embodiments, in one embodiment of the present application, the etching gas of the first dielectric layer is one or more gases selected from C 4F8、O2, ar and N 2, which are not limited in this regard, and the present application is specifically limited as appropriate.
On the basis of the above embodiment, in one embodiment of the present application, the preset time is after the first dielectric layer 32 is formed, and the thickness of the etching barrier layer is greater than the first preset value, in this embodiment of the present application, the thickness of the etching barrier layer itself is already convenient for controlling the removal time of the etching barrier layer, and if a portion of the first dielectric layer remains on the surface of the etching barrier layer as a buffer layer, the polishing time will be too long.
Therefore, on the basis of the foregoing embodiment, in one embodiment of the present application, if the detection result of the semiconductor device does not meet the first condition, the thickness of the etching barrier layer is greater than a first preset value, and removing the dielectric layer 3 includes:
etching the first dielectric layer for a third time based on the etching rate of the first dielectric until the first dielectric layer is completely removed;
and removing the etching barrier layer 31 until the etching barrier layer is removed.
Since no buffer layer is formed on the surface of the etching stopper layer, the etching and/or polishing process of the etching stopper layer is directly described in detail in the first embodiment, which is not limited by the present application, and is specific as the case may be.
According to the manufacturing method of the semiconductor device, after the first dielectric layer is formed on one side, away from the first insulating layer, of the etching barrier layer, the semiconductor device is detected, and a detection result of the semiconductor device is obtained; if the detection result of the semiconductor device does not meet the first condition, removing the first dielectric layer and the etching barrier layer; forming an etching barrier layer on one side of the first insulating layer, which is away from the element layer, and forming a first dielectric layer on one side of the etching barrier layer, which is away from the first insulating layer; and performing a subsequent process until the detection result of the semiconductor device meets a first condition, so as to reduce the probability of influencing the yield of the semiconductor device due to the defect of the formation of the dielectric layer in the semiconductor device, thereby improving the yield of the semiconductor device.
Embodiment III:
in the embodiment of the present application, referring to fig. 11, the dielectric layer 3 further includes a photoresist pattern 5 on a side of the first dielectric layer 32 facing away from the etching stopper 31; referring to fig. 12, in an embodiment of the present application, if the detection result of the semiconductor device does not satisfy the first condition, removing the dielectric layer 3 includes:
step 231: referring to fig. 13, the photoresist pattern 5 is removed;
step 232: referring to fig. 14, a portion of the first dielectric layer 32 is etched, leaving a first dielectric layer 321 of a first thickness;
Step 233: referring to fig. 15, the first dielectric layer 321 and the etch stop layer 31 of the first thickness are polished until the etch stop layer 31 is removed;
Wherein the first thickness is smaller than the thickness of the etching stopper 31.
The difference between the present embodiment and the second embodiment is that: and detecting the semiconductor device after the photoresist pattern is formed, wherein if the detection result of the semiconductor device does not meet the first condition, the photoresist pattern is removed first and then the first dielectric layer and the etching barrier layer are removed on the basis of the second embodiment. Since the process of removing the first dielectric layer and the etching stopper layer has been described in detail in the first embodiment and the second embodiment, this embodiment will not be described in detail.
Alternatively, in one embodiment of the present application, the photoresist pattern may be removed by a conventional photoresist removal process, which is not described in detail herein, since it is well known to those skilled in the art.
According to the manufacturing method of the semiconductor device, after the first dielectric layer is away from the photoresist pattern on one side of the etching barrier layer, the semiconductor device is detected, and a detection result of the semiconductor device is obtained; if the detection result of the semiconductor device does not meet the first condition, removing the photoresist pattern, the first dielectric layer and the etching barrier layer; and forming an etching barrier layer on one side of the first insulating layer, which is away from the element layer, forming a first dielectric layer on one side of the etching barrier layer, which is away from the first insulating layer, and forming a photoresist pattern on one side of the first dielectric layer, which is away from the etching barrier layer, until the detection result of the semiconductor device meets a first condition, and performing a subsequent process to reduce the probability of influencing the yield of the semiconductor device due to the defect of the formation of the dielectric layer in the semiconductor device, thereby improving the yield of the semiconductor device.
On the basis of any of the above embodiments, in one embodiment of the present application, referring to fig. 16, the dielectric layer 3 further includes a first mask layer 35 located between the photoresist pattern 5 and the first dielectric layer 32, and in an embodiment of the present application, after removing the photoresist pattern 5, the method further includes, before etching a portion of the dielectric layer 3:
the first mask layer 35 is removed.
Specifically, in one embodiment of the present application, the first mask layer is a metal mask layer, and optionally, a material of the first mask layer is TiN, but the present application is not limited thereto, and the present application is specifically limited thereto as the case may be.
On the basis of the foregoing embodiment, in one embodiment of the present application, the first mask layer is a metal mask layer, and removing the first mask layer includes: and removing the first mask layer by utilizing H 2O2. However, the present application is not limited thereto, and in other embodiments of the present application, other acidic solutions may be used to remove the first mask layer, as the case may be.
It should be noted that, if the preset time is located after the first mask layer is formed and before the photoresist pattern is formed, if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer 3 may also include: removing the first mask layer; etching part of the first dielectric layer, and reserving the first dielectric layer with the first thickness; polishing the first dielectric layer with the first thickness and the etching barrier layer 31 until the etching barrier layer is removed; the application is not limited thereto, as the case may be.
It should be noted that, in the foregoing embodiments of the present application, the etching stop layer is formed in the dielectric layer at the preset time, before the first dielectric layer is formed, after the first dielectric layer is formed, before the photoresist pattern is formed, and after the photoresist pattern is formed, respectively, which are described as examples, but the present application is not limited thereto, and in other embodiments of the present application, the dielectric layer may further include other film layers, and the preset time may also be other time, which is not limited thereto, and is specific to the present application as required.
In summary, in the method for manufacturing a semiconductor device according to the embodiment of the present application, during a process of forming a dielectric layer on a side of the first insulating layer away from the element layer, detecting the semiconductor device at a preset time before forming a second through hole in the dielectric layer, to obtain a detection result of the semiconductor device; and if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer, and regrowing the dielectric layer on one side of the surface of the first insulating layer, which is away from the element layer, until the detection result of the semiconductor device meets the first condition, so as to reduce the probability of influencing the yield of the semiconductor device due to the defect of the formation of the dielectric layer in the semiconductor device, improve the yield of the semiconductor device, and further improve the customer satisfaction.
In the present description, each part is described in a progressive manner, and each part is mainly described as different from other parts, and identical and similar parts between the parts are mutually referred.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. The manufacturing method of the semiconductor device is characterized in that the semiconductor device comprises an element layer, a first insulating layer positioned on the surface of a first side of the element layer and a dielectric layer positioned on one side of the first insulating layer, which is away from the element layer, wherein the first insulating layer is provided with at least one first through hole, a first plug connector electrically connected with the element layer is filled in the first through hole, the dielectric layer comprises an etching blocking layer and a first dielectric layer positioned on the surface of the first insulating layer, and the dielectric constant of the first dielectric layer is smaller than 4F/m; the manufacturing method comprises the following steps:
Step 1: in the process of forming the dielectric layer, detecting the semiconductor device at preset time to obtain a detection result of the semiconductor device;
step 2: if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer;
Step 3: regrowing the dielectric layer on the side of the surface of the first insulating layer, which is away from the element layer;
step 4: repeating the steps 1-3 until the detection result of the semiconductor device meets a first condition;
The dielectric layer is provided with a second through hole, the second through hole is filled with a second plug connector electrically connected with the first plug connector, and the preset time is after the etching barrier layer is formed and before the second through hole is formed in the dielectric layer;
the method further comprises, after step 2 and before step 3: and polishing the first insulating layer for a first time, and removing part of the first insulating layer and part of the first plug connector.
2. The method of claim 1, wherein the first time has a value ranging from 1s to 4s, inclusive.
3. The method according to any one of claims 1-2, wherein the preset time is before the first dielectric layer is formed after the etching stop layer is formed, and if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer includes:
If the detection result of the semiconductor device does not meet the first condition and the thickness of the etching barrier layer is smaller than a first preset value, forming a buffer layer on the surface of the etching barrier layer;
Polishing the buffer layer and the etching barrier layer until the etching barrier layer is removed;
Wherein the hardness of the buffer layer is less than the hardness of the etch stop layer and not greater than the hardness of the first dielectric layer, and the texture of the buffer layer is softer than the etch stop layer and not softer than the texture of the first dielectric layer.
4. The method of claim 3, wherein the buffer layer is an ethyl silicate layer.
5. The method according to any one of claims 1-2, wherein the removing the dielectric layer if the detection result of the semiconductor device does not satisfy the first condition after the forming of the first dielectric layer is performed for the preset time includes:
etching part of the first dielectric layer, and reserving the first dielectric layer with the first thickness;
polishing the first dielectric layer with the first thickness and the etching barrier layer until the etching barrier layer is removed;
wherein the first thickness is less than the thickness of the etch stop layer.
6. The method of claim 5, wherein the first thickness is no greater than 200 angstroms.
7. The method of claim 5, wherein the etching gas of the first dielectric layer is C 4F8、O2, ar, or N 2.
8. The method of claim 5, wherein etching a portion of the first dielectric layer to leave a first thickness of the first dielectric layer comprises:
etching the first dielectric layer with the second thickness;
Determining an etching rate of the first dielectric layer based on an etching process of the first dielectric layer of the second thickness;
continuing etching the rest part of the first dielectric layer for a second time by utilizing the etching rate of the first dielectric layer so as to keep the first dielectric layer with the first thickness;
Wherein the sum of the first thickness and the second thickness is less than the total thickness of the first dielectric layer.
9. The method of claim 8, wherein the second thickness is 1/2 of the total thickness of the first dielectric layer.
10. The method of any of claims 1-2, wherein the dielectric layer further comprises a photoresist pattern on a side of the first dielectric layer facing away from the etch stop layer; the preset time is located after the photoresist pattern is formed, and if the detection result of the semiconductor device does not meet the first condition, removing the dielectric layer includes:
Removing the photoresist pattern;
etching part of the first dielectric layer, and reserving the first dielectric layer with the first thickness;
polishing the first dielectric layer with the first thickness and the etching barrier layer until the etching barrier layer is removed;
wherein the first thickness is less than the thickness of the etch stop layer.
11. The method of claim 10, wherein the dielectric layer further comprises a first mask layer between the photoresist pattern and the first dielectric layer, the method further comprising, after removing the photoresist pattern, before etching a portion of the dielectric layer:
And removing the first mask layer.
12. The method of claim 11, wherein the first mask layer is a metal mask layer, and removing the first mask layer comprises:
And removing the first mask layer by utilizing H 2O2.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1589977A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Rotary coating manufacturing method capable of repeatedly proceeding |
| CN102543845A (en) * | 2010-12-29 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1589977A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Rotary coating manufacturing method capable of repeatedly proceeding |
| CN102543845A (en) * | 2010-12-29 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
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