CN112992661B - Micro LED and manufacturing method thereof - Google Patents

Micro LED and manufacturing method thereof Download PDF

Info

Publication number
CN112992661B
CN112992661B CN202011322165.2A CN202011322165A CN112992661B CN 112992661 B CN112992661 B CN 112992661B CN 202011322165 A CN202011322165 A CN 202011322165A CN 112992661 B CN112992661 B CN 112992661B
Authority
CN
China
Prior art keywords
layer
epitaxial wafer
light
region
current diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011322165.2A
Other languages
Chinese (zh)
Other versions
CN112992661A (en
Inventor
王涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Kangjia Photoelectric Technology Research Institute Co Ltd
Original Assignee
Chongqing Kangjia Photoelectric Technology Research Institute Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chongqing Kangjia Photoelectric Technology Research Institute Co Ltd filed Critical Chongqing Kangjia Photoelectric Technology Research Institute Co Ltd
Priority to CN202011322165.2A priority Critical patent/CN112992661B/en
Publication of CN112992661A publication Critical patent/CN112992661A/en
Application granted granted Critical
Publication of CN112992661B publication Critical patent/CN112992661B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)

Abstract

The application relates to a manufacturing method of a micro LED. The method includes the following operations. Growing an epitaxial wafer on the substrate, growing a current diffusion layer on the epitaxial wafer, and arranging a photoresist layer on the current diffusion layer. A first light is irradiated on the photoresist layer through a first mask, and the first light generates Poisson bright spots on the photoresist layer. And developing the photoresist layer, and etching the current diffusion layer and the epitaxial wafer. And removing the photoresist layer, and arranging metal electrodes on the etched current diffusion layer and the epitaxial wafer. According to the manufacturing method of the miniature LED, the cylindrical miniature LED is prepared by photoetching the Poisson bright spots, so that the yellow light frequency can be reduced, the production cost can be saved, and the precision and the yield of the miniature LED can be improved.

Description

Micro LED and manufacturing method thereof
Technical Field
The invention relates to the technical field of LED preparation, in particular to a miniature LED and a manufacturing method thereof.
Background
The light emitting diode has the advantages of energy conservation, environmental protection, long service life and the like, and the light emitting diode can gradually replace traditional lighting lamps such as incandescent lamps and fluorescent lamps and enter thousands of households in the future. At present, a micro light emitting diode is a novel display technology, has the advantages of high brightness, low delay, long service life, wide viewing angle, high contrast ratio and the like, and is the future development direction of the light emitting diode. The conventional Micro light emitting diode (Micro LED) needs four yellow lights, which results in the disadvantages of large alignment tolerance, high cost, etc., and how to manufacture a high-reliability Micro LED at low cost is a problem that needs to be solved at present.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present application is directed to a micro LED and a method for manufacturing the same. In the manufacturing method of the micro LED, the use times of yellow light can be reduced, the production time can be saved, the production cost can be saved, and the yield can be improved by using the Poisson bright spot to prepare the LED chip. In addition, through the process, the yellow light contraposition times can be reduced, and errors caused by contraposition are reduced, so that the distance between the N electrode and the P electrode is more uniform, and the current expansion is facilitated.
According to a first aspect, a method for fabricating a micro LED is provided. The manufacturing method comprises the following steps. Growing an epitaxial wafer on the substrate, growing a current diffusion layer on the epitaxial wafer, and arranging a photoresist layer on the current diffusion layer. The first light is irradiated on the photoresist layer through the first mask, wherein the first light generates Poisson bright spots on the photoresist layer. And developing the photoresist layer, and etching the current diffusion layer and the epitaxial wafer. And removing the photoresist layer, and arranging metal electrodes on the etched current diffusion layer and the epitaxial wafer.
According to one embodiment of the present application, wherein the removing the photoresist layer and the disposing the metal electrode on the etched current diffusion layer and the epitaxial wafer comprises the following steps. And removing the photoresist layer, arranging a passivation layer on the substrate, the current diffusion layer and the epitaxial wafer, and etching the passivation layer to expose part of the current diffusion layer and part of the epitaxial wafer. And respectively arranging metal electrodes on the exposed part of the current diffusion layer and the exposed part of the epitaxial wafer.
According to one embodiment of the present application, wherein developing the photoresist layer includes the following operations. Developing a first region of the photoresist layer corresponding to the poisson bright spot, and developing a second region of the photoresist layer outside the orthographic projection of the first photomask.
According to one embodiment of the present application, wherein developing the photoresist layer includes the following operations. Developing a portion of the photoresist layer in the first region and developing the entire photoresist layer in the second region.
According to one embodiment of the present application, wherein the first region of the photoresist layer is developed to form a circular hole, a diameter and a depth of the circular hole being determined according to an exposure gap and an exposure amount of the first light.
According to an embodiment of the present application, wherein etching the current spreading layer and the epitaxial wafer includes the following operations. The portions of the current diffusion layer corresponding to the first region are etched, and the portions of the epitaxial wafer corresponding to the first region and the second region are etched.
According to one embodiment of the present application, the exposure amount of the first light to which the first region is exposed is smaller than the exposure amount of the first light to which the second region is exposed. Wherein the first area is illuminated by the poisson optical spot and the second area is illuminated by the first light.
According to one embodiment of the present application, wherein a passivation layer is disposed on the substrate, the current spreading layer, and the epitaxial wafer, and etching the passivation layer such that portions of the current spreading layer are exposed and portions of the epitaxial wafer are exposed comprises the following operations. And depositing a passivation layer on the exposed surfaces of the substrate, the epitaxial wafer and the current diffusion layer, and arranging a positive adhesive layer on the passivation layer. And irradiating second light on the positive adhesive layer through a second photomask, developing a third area of the positive adhesive layer corresponding to the current diffusion layer, and developing a fourth area of the positive adhesive layer corresponding to the first area. And etching a part of the passivation layer corresponding to the third region and a part of the passivation layer corresponding to the fourth region, so that a part of the current diffusion layer corresponding to the third region is exposed and a part of the epitaxial wafer corresponding to the fourth region is exposed.
According to an embodiment of the application, wherein an orthographic projection of the third region falls within a range of the etched current spreading layer, and an orthographic projection of the fourth region falls within a range of the first region.
According to an embodiment of the present application, wherein the disposing of the metal electrodes on the exposed portion of the current diffusion layer and the exposed portion of the epitaxial wafer, respectively, comprises the following steps. And arranging a negative glue layer on the passivation layer, the exposed part of the current diffusion layer and the exposed part of the epitaxial wafer. And irradiating third light on the negative glue layer through a third photomask, and developing the negative glue layer to ensure that the exposed part of the current diffusion layer and the exposed part of the epitaxial wafer are exposed. And metal electrodes are respectively arranged on the exposed part of the current diffusion layer and the exposed part of the epitaxial wafer. And removing all negative glue layers.
According to an embodiment of the present application, wherein the first light, the second light, and the third light are ultraviolet light.
According to an embodiment of the present application, the epitaxial wafer is a GaN epitaxial wafer, and the current diffusion layer is an ITO layer
According to a second aspect, the present application also provides a micro LED. The micro-LED comprises the micro-LED manufactured according to the manufacturing method of the first aspect and/or any embodiment of the first aspect.
According to the manufacturing method of the miniature LED, the cylindrical miniature LED is prepared by photoetching the Poisson bright spots, so that the yellow light frequency can be reduced, the production cost can be saved, and the yield of the miniature LED can be improved. In addition, the manufacturing method of the micro LED can reduce the alignment frequency of yellow light, so that the tolerance caused by alignment of the yellow light is reduced, the distance between the N electrode and the P electrode is more uniform, and the current expansion is facilitated.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 shows a flow chart of a method of fabricating a micro LED according to the present application.
Fig. 2 shows a schematic cross-sectional view of a micro LED according to the present application.
Fig. 3 shows a process flow diagram for etching an epitaxial wafer and a current spreading layer.
Fig. 4 shows a process flow diagram for etching a passivation layer.
Fig. 5 shows a process flow diagram for providing a metal electrode.
Description of reference numerals:
10-a substrate; 20-an epitaxial wafer; a 202-N-GaN layer; 204-MQW layer; 206: a P-GaN layer; 30-a current spreading layer; 40-a photoresist layer; 400-a first area; 50-a passivation layer; 60-positive glue layer; 600-a third region; 610-a fourth area; 70-negative glue layer; 80-a metal electrode; 100-a first light ray; 110-a first mask; 200-a second light; 210-a second mask; 2100-a via; 300-a third ray; 310-a third mask; 3100-through hole.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure.
For the sake of understanding, the process flow and the terminology in the micro LED manufacturing process referred to in the present application are explained and explained below. It should be noted that the above explanation and description do not constitute any limitation to the present application.
The photolithography technique is used for photolithography, and the material used is a photosensitive material, i.e., a Photoresist (PR). Photoresists are also known as photoresists. PR has unique characteristics, and under the action of Ultraviolet (UV) light, PR undergoes a chemical reaction to become a new substance soluble in acid or alkali.
The photolithography technique is to transfer the pattern on the mask onto PR, and then to soak the irradiated part of PR in solvent to dissolve or retain the part of PR, so as to form the photoresist pattern which is identical to or complementary to the mask. Since the ambient illumination source of the photolithography process is yellow light, not red light of the conventional darkroom, the process is often referred to as "yellow light" process. The PR not masked by the mask becomes alkali-insoluble after exposure, forming a negative photoresist pattern. PR not blocked by mask is changed into substance dissolved in alkali after exposure to form positive photoresist pattern. UV light is irradiated onto the photoresist through the pattern on the mask to produce a photoresist pattern (PR is chemically changed after UV irradiation, but the physical form is not changed, so the produced photoresist pattern is invisible to naked eyes). In the alkaline solution, a resist pattern identical to or complementary to the mask pattern is formed on the resist film, and in the acidic solution, Indium Tin Oxide (ITO) not blocked by the resist pattern is dissolved to form an ITO pattern. The photoresist pattern is washed away in an acidic solution, and the ITO pattern is retained.
Generally, the LED manufacturing process includes "exposure", "development", "etching", "demolding", and the like. Specifically, "exposure" refers to the transfer of a pattern to a photoresist coating using UV light illumination. By "developing" is meant that the unexposed portions of the negative photoresist will dissolve and the exposed portions of the positive photoresist will dissolve under the influence of a developing solution. By "etching" is meant that portions not protected by the photoresist coating will be etched. "stripping" refers to removing the photoresist.
It should be noted that the structure shown in the drawings is only for schematically illustrating the cross-section of the micro LED and the components in the manufacturing process thereof, and is not intended to limit the actual structure thereof. Meanwhile, hatching in the drawings of the present application is intended to clearly distinguish the respective components, and is not intended to limit the properties of the materials and the like of the respective components.
In a first aspect, the present application provides a method for manufacturing a micro LED, as shown in fig. 1, the method for manufacturing a micro LED includes the following steps.
S100: an epitaxial wafer 20 is grown on a substrate 10, a current diffusion layer 30 is grown on the epitaxial wafer 20, and a photoresist layer 40 is provided on the current diffusion layer 30.
The process used by the manufacturing method of the micro LED comprises MESA (step etching) etching and ISO (gallium nitride deep etching) etching. Prior to performing the MESA etch, first, a substrate 10 is provided and an epitaxial wafer 20 is grown on the substrate 10. Optionally, the substrate 10 is a sapphire substrate. A current spreading layer 30 is sputtered on the surface of the epitaxial wafer 20 remote from the substrate 10. Then, a photoresist layer 40 is coated on the surface of the current diffusion layer 30 away from the substrate 10. In one embodiment, the photoresist layer 40 is a positive photoresist.
S200: the first light 100 is irradiated on the photoresist layer 40 through the first mask 110, wherein the first light 100 is diffracted by the first mask 110 and generates poisson's bright spots on the photoresist layer 40.
In this step, first, the first mask 110 is disposed. Alternatively, the first mask 110 is a disk, and the diameter of the disk is designed according to the size requirement for generating the poisson effect. Specifically, in order to diffract the first light beam 100 after passing through the first mask 110 and generate poisson's bright spots at the middle position of the photoresist layer 40, the first mask 110 is designed to have a specific size. The first light 100 passes through the first mask 110 to generate a poisson effect and generate a poisson bright spot on the photoresist layer 40.
In the present application, the first light 100 may be UV light.
In one embodiment, the poisson's patches fall into the first region 400 of the photoresist layer 40. The first region 400 may be a central region of the photoresist layer 40. The area of the photoresist layer 40 outside the orthographic projection of the first mask 110 on the photoresist layer 40 is a second area, and the second area is directly exposed by the first light 100. It should be understood that, in the present embodiment, the poisson optical spot generated on the photoresist layer 40 is used as a center of a circle, and a plurality of circles of diffraction fringes that are annular and concentric circles with each other appear around the center of the circle according to the poisson effect. However, since the exposure amount at these annular multi-turn diffraction fringes is small and the influence thereof on the resist layer 40 is small, the influence of these diffraction fringes is not considered in the present application for the time being.
Referring to fig. 3, the first light 100 passes through the first mask 110 to generate poisson bright spots on the first region 400 of the photoresist layer 40, and the second region of the photoresist layer 40, which is located outside the orthographic projection of the first mask 110 on the photoresist layer 40, is directly irradiated by the first light 100. It should be understood that the first region 400 is exposed to a lesser amount of light than the second region of the photoresist layer 40.
It should be understood that fig. 3 shows a cross-sectional view of the substrate 10, the epitaxial wafer 20, the current spreading layer 30, and the photoresist layer 40.
In fig. 3, a state 3-a shows a state after an epitaxial wafer 20, a current diffusion layer 30, and a photoresist layer 40 are sequentially provided on a substrate 10; state 3-B shows the state after developing the photoresist layer 40; state 3-C shows the state after etching the epitaxial wafer 20 and the current diffusion layer 30.
S300: the photoresist layer 40 is developed and the current spreading layer 30 and the epitaxial wafer 20 are etched.
After the exposure, the photoresist layer 40 is developed using a developer. When exposing, one part of the photoresist layer 40 is exposed to light and the other part is not exposed to light, the UV light affects the photoresist performance of the photoresist layer 40, the visible part of the positive photoresist is dissolved in the developing solution, and the invisible part is not dissolved, so that the light spot pattern generated by the Poisson effect can be copied and etched on the photoresist layer 40. Through the steps, the MESA photoetching process can be completed.
In one embodiment, developing the photoresist layer 40 includes the following operations. A first region 400 of the photoresist layer 40 corresponding to the poisson's bright spot is developed and a second region of the photoresist layer 40 outside the orthographic projection of the first mask 110 on the photoresist layer 40 is developed. The first region 400 and the second region are both light-receiving regions.
In one embodiment, developing the photoresist layer 40 includes the following operations. The photoresist of the photoresist layer 40 at a portion of the thickness of the first region 400 is developed (i.e., the photoresist layer 40 at a portion of the thickness of the first region 400 is dissolved), and the photoresist of the photoresist layer 40 at the entire thickness of the second region is developed (i.e., the photoresist layer 40 at the second region is dissolved). Specifically, as a result of the exposure of the first region 400 (e.g., the central region) of the photoresist layer 40 to the poisson's bright spot, the photoresist properties of the partial thickness of the first region 400 of the photoresist layer 40 change such that the partial thickness of the photoresist layer 40 of the first region 400 is developed (i.e., dissolved by the developing solution); the second region of the photoresist layer 40 (i.e., the region of the photoresist layer 40 outside the orthographic projection of the first mask 110 on the photoresist layer 40) is exposed to the direct light 100, i.e., the exposure amount is relatively large, so that the photoresist performance of the entire thickness of the second region of the photoresist layer 40 is changed, and the photoresist layer 40 of the entire thickness of the second region can be developed (i.e., dissolved by the developing solution).
In one embodiment, the first region 400 of the photoresist layer 40 is developed to obtain a circular hole (in the embodiment shown in FIG. 3, the circular hole is a blind hole) having a diameter and depth determined according to the exposure gap and exposure amount of the first light 100. It can be understood that the circular hole is obtained by irradiating the photoresist layer 40 with poisson bright spots, so that the diameter and depth of the circular hole can be controlled by adjusting the exposure gap and exposure amount of the first light 100 to meet different process requirements.
Next, after the MESA lithography is completed, the epitaxial wafer 20 is baked, and then the current diffusion layer 30 and the epitaxial wafer 20 are etched using an ICP (Inductively Coupled Plasma) apparatus.
In one embodiment, etching the current spreading layer 30 and the epitaxial wafer 20 includes the following operations.
The portion of the current diffusion layer 30 corresponding to the first region 400 is etched, and the portions of the epitaxial wafer 20 corresponding to the first region 400 and the second region are etched. Specifically, the portion of the epitaxial wafer 20 corresponding to the first region 400 is etched downward to a depth of 1um to 1.3um, and the portion of the epitaxial wafer 20 corresponding to the second region is etched downward to a depth of about 6 um.
It is understood that the ITO etching process is completed after etching the portion of the current diffusion layer 30 corresponding to the first region 400.
After etching the portions of the epitaxial wafer 20 corresponding to the first region 400 and the second region, an ISO (gallium nitride deep etch) etching process is completed.
In one embodiment, referring to fig. 3, the etched epitaxial wafer 20 has a substantially frustoconical structure. That is, the etched epitaxial wafer 20 has a substantially trapezoidal cross section. In another embodiment, the etched epitaxial wafer 20 has a substantially rectangular parallelepiped structure. That is, the etched epitaxial wafer 20 has a substantially rectangular cross-section.
In one embodiment, the first region 400 is exposed to a lesser amount of the first light 100 than the second region is exposed to the first light 100.
It should be understood that when the current diffusion layer 30 is etched, the side corrosion of the current diffusion layer 30 is also caused, i.e., the dissolution is performed from the side of the current diffusion layer 30 perpendicular to the epitaxial wafer 20 (see fig. 3).
Through the steps, the three yellow lights of MESA, ISO and ITO are combined into one yellow light.
S400: the photoresist layer 40 is removed and metal electrodes are provided on the etched current diffusion layer 30 and the epitaxial wafer 20. In one embodiment, step S400 includes the following steps S402 to S404.
S402: the photoresist layer 40 is removed, a passivation layer 50 is provided on the substrate 10, the current diffusion layer 30, and the epitaxial wafer 20, and the passivation layer 50 is etched to expose the current diffusion layer 30 partially and the epitaxial wafer 20 partially.
In one embodiment, step S402 specifically includes the following steps. Referring to FIG. 4, the photoresist layer 40 is removed. A passivation layer 50 is deposited on the exposed surfaces of the substrate 10, the epitaxial wafer 20, and the current spreading layer 30, and a positive adhesive layer 60 is disposed on the passivation layer 50. The second light 200 is irradiated on the positive glue layer 60 through the through hole 2100 of the second photo-mask 210, and the third region 600 of the positive glue layer 60 corresponding to the current spreading layer 30 is developed (dissolved), and the fourth region 610 of the positive glue layer 60 corresponding to the first region 400 is developed (dissolved). A partial region of the passivation layer 50 corresponding to the third region 600 is etched, and a partial region of the passivation layer corresponding to the fourth region 610 is etched, so that a portion of the current diffusion layer 30 corresponding to the third region 600 is exposed and a portion of the epitaxial wafer 20 corresponding to the fourth region 610 is exposed. At this time, all of the positive glue layer 60 is removed. It is understood that the second light 200 is irradiated to the third and fourth regions 600 and 610 of the positive adhesive layer 60 through the through hole 2100, respectively.
In fig. 4, state 4-a shows a state after a passivation layer 50 is provided on the substrate 10, the current diffusion layer 30, and the epitaxial wafer 20; the state 4-B shows a state after the positive adhesive layer 60 is developed; state 4-C shows the state after the passivation layer 50 has been etched.
In the present application, the second light 200 may be UV light.
It should be understood that fig. 4 shows a cross-sectional view of the substrate 10, the epitaxial wafer 20, the current spreading layer 30, the passivation layer 50, and the positive glue layer 60.
S404: metal electrodes 80 are provided on the exposed portions of the current diffusion layers 30 and the exposed portions of the epitaxial wafer 20, respectively.
In one embodiment, step S404 specifically includes the following steps. Referring to fig. 5, a negative adhesive layer 70 is disposed on the passivation layer 50, the exposed portion of the current spreading layer 30, and the exposed portion of the epitaxial wafer 20. The third light 300 is irradiated on the negative photoresist layer 70 through the through hole 3100 of the third mask 310, and the negative photoresist layer 70 is developed so that the exposed portion of the current diffusion layer 30 and the exposed portion of the epitaxial wafer 20 remain exposed. Metal electrodes 80 are provided on the exposed portions of the current diffusion layers 30 and the exposed portions of the epitaxial wafer 20, respectively. At this point, all of the negative glue layer 70 is removed.
In fig. 5, state 5-a shows a state after a negative paste layer 70 is provided on the passivation layer 50, the exposed portion of the current diffusion layer 30, and the exposed portion of the epitaxial wafer 20; the state 5-B shows a state after the negative adhesive layer 70 is developed; the state 5-C shows a state after the metal electrode 80 is provided.
In the present application, the third light 300 may be UV light.
It is to be understood that fig. 5 shows a cross-sectional view of the substrate 10, the epitaxial wafer 20, the current diffusion layer 30, the passivation layer 50, the negative glue layer 70, and the metal electrode 80.
In the present application, the current diffusion layer 30 may be an ITO layer 30, and the epitaxial wafer 20 may be a gallium nitride GaN epitaxial wafer 20. The epitaxial wafer 20 includes an N-GaN layer 202, an MQW layer 204, and a P-GaN layer 206 (see fig. 2) stacked in this order.
In one embodiment of the present application, an orthogonal projection of the third region 600 falls within a range of the etched current diffusion layer 30, and an orthogonal projection of the fourth region 610 falls within a range of the first region 400.
In the above steps, the metal electrode 80 is obtained by a metal evaporation process and a metal positive-resist evaporation (Lift-off) process.
The metal electrode 80 obtained through the above steps is convenient for realizing metal ohmic contact and bonding metal effects.
In a second aspect, the present application also provides a micro LED. Fig. 2 shows a schematic cross-sectional view of a micro LED provided in the present application, including a front view and a top view of the micro LED. The micro LED of the present application is manufactured by the method for manufacturing a micro LED according to the first aspect and any one of the embodiments. As can be seen from fig. 2, in one embodiment, the substrate 10 in the present application is cylindrical, and the epitaxial wafer 20 is also cylindrical before etching. Moreover, the micro-LED prepared by the method for manufacturing the micro-LED is also substantially cylindrical. The overall body of the micro LED and all parts thereof are designed into a cylindrical or roughly cylindrical structure, which is more beneficial to the expansion of current.
According to the manufacturing method of the miniature LED, the cylindrical miniature LED is prepared by photoetching the Poisson bright spots, so that the yellow light frequency can be reduced, the production cost can be saved, and the yield of the miniature LED can be improved. In addition, the manufacturing method of the miniature LED can reduce the alignment frequency of yellow light, so that the tolerance caused by alignment of the yellow light is reduced, the equal distance between NP electrodes is more uniform, and the current expansion is facilitated.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.

Claims (11)

1. A manufacturing method of a micro LED comprises the following steps:
growing an epitaxial wafer on a substrate, growing a current diffusion layer on the epitaxial wafer, and arranging a light resistance layer on the current diffusion layer;
irradiating a first light on the light resistance layer through a first light cover, wherein the first light is diffracted through the first light cover and generates a Poisson spot on the light resistance layer, the area of the Poisson spot falling into the light resistance layer is a first area, the area of the light resistance layer, which is positioned outside the orthographic projection of the first light cover on the light resistance layer, is a second area, and the exposure amount of the first light on the first area of the light resistance layer is smaller than that of the first light on the second area;
developing the photoresist layer to enable the photoresist layer with partial thickness of the first area to be dissolved by a developing solution, and the photoresist layer with the whole thickness of the second area to be dissolved by the developing solution;
etching the current diffusion layer and the epitaxial wafer, etching the part of the epitaxial wafer corresponding to the first region downwards to an N-GaN layer of the epitaxial wafer, and etching the part of the epitaxial wafer corresponding to the second region downwards to the substrate; and
and removing the photoresist layer, and arranging metal electrodes on the etched current diffusion layer and the epitaxial wafer.
2. The method of claim 1, wherein the removing the photoresist layer and the disposing metal electrodes on the etched current spreading layer and the epitaxial wafer comprises:
removing the photoresist layer, arranging a passivation layer on the substrate, the current diffusion layer and the epitaxial wafer, and etching the passivation layer to expose part of the current diffusion layer and expose part of the epitaxial wafer; and
and respectively arranging metal electrodes on the exposed part of the current diffusion layer and the exposed part of the epitaxial wafer.
3. The method of claim 1, wherein the first region of the photoresist layer is developed to form a circular hole, and the diameter and depth of the circular hole are determined according to the exposure gap and exposure amount of the first light.
4. The method of claim 1, wherein etching the current spreading layer and the epitaxial wafer comprises:
etching a portion of the current diffusion layer corresponding to the first region, and etching a portion of the epitaxial wafer corresponding to the first region and the second region.
5. The method of claim 2, wherein disposing the passivation layer on the substrate, the current spreading layer, and the epitaxial wafer and etching the passivation layer such that portions of the current spreading layer are exposed and portions of the epitaxial wafer are exposed comprises:
depositing a passivation layer on the exposed surfaces of the substrate, the epitaxial wafer and the current diffusion layer, and arranging a positive adhesive layer on the passivation layer;
irradiating second light on the positive adhesive layer through a second photomask, developing a third area of the positive adhesive layer corresponding to the current diffusion layer, and developing a fourth area of the positive adhesive layer corresponding to the first area;
etching a portion of the passivation layer corresponding to the third region and a portion of the passivation layer corresponding to the fourth region such that a portion of the current diffusion layer corresponding to the third region is exposed and a portion of the epitaxial wafer corresponding to the fourth region is exposed.
6. The method of claim 5, wherein the second light is ultraviolet light.
7. The method of claim 5, wherein an orthographic projection of the third region falls within a range of the etched current spreading layer, and an orthographic projection of the fourth region falls within a range of the first region.
8. The method of claim 2, wherein the disposing the metal electrode on the exposed portion of the current spreading layer and the exposed portion of the epitaxial wafer comprises:
arranging a negative glue layer on the passivation layer, the exposed part of the current diffusion layer and the exposed part of the epitaxial wafer;
irradiating third light on the negative adhesive layer through a third photomask, and developing the negative adhesive layer to enable the exposed part of the current diffusion layer and the exposed part of the epitaxial wafer to be exposed;
providing metal electrodes on the exposed portion of the current diffusion layer and the exposed portion of the epitaxial wafer, respectively; and
and removing all the negative glue layers.
9. The method of claim 8, wherein the first light and the third light are ultraviolet light.
10. The method for manufacturing a micro LED according to any one of claims 1 to 9, wherein the epitaxial wafer is a GaN epitaxial wafer and the current diffusion layer is an ITO (indium tin oxide) layer.
11. A micro LED comprising the micro LED manufactured by the method according to any one of claims 1 to 10.
CN202011322165.2A 2020-11-23 2020-11-23 Micro LED and manufacturing method thereof Active CN112992661B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011322165.2A CN112992661B (en) 2020-11-23 2020-11-23 Micro LED and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011322165.2A CN112992661B (en) 2020-11-23 2020-11-23 Micro LED and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN112992661A CN112992661A (en) 2021-06-18
CN112992661B true CN112992661B (en) 2021-11-23

Family

ID=76344816

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011322165.2A Active CN112992661B (en) 2020-11-23 2020-11-23 Micro LED and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN112992661B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097296A (en) * 2010-10-09 2011-06-15 北京大学 Preparation method of semiconductor nano circular ring
CN102495526A (en) * 2011-11-16 2012-06-13 中国科学院物理研究所 Optical exposing method, and method for applying optical exposure in preparation of silicon material vertical hollow structure
CN108511573A (en) * 2017-02-28 2018-09-07 山东浪潮华光光电子股份有限公司 A kind of preparation method of GaN base light emitting chip
CN111453693A (en) * 2020-04-21 2020-07-28 南方科技大学 Preparation method of nanoring

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170343893A1 (en) * 2016-05-25 2017-11-30 U.S.A. As Represented By The Administrator Of The National Aeronautics And Space Administration Design and fabrication of partially transparent petaled mask or occulter using grayscale lithography

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097296A (en) * 2010-10-09 2011-06-15 北京大学 Preparation method of semiconductor nano circular ring
CN102495526A (en) * 2011-11-16 2012-06-13 中国科学院物理研究所 Optical exposing method, and method for applying optical exposure in preparation of silicon material vertical hollow structure
CN108511573A (en) * 2017-02-28 2018-09-07 山东浪潮华光光电子股份有限公司 A kind of preparation method of GaN base light emitting chip
CN111453693A (en) * 2020-04-21 2020-07-28 南方科技大学 Preparation method of nanoring

Also Published As

Publication number Publication date
CN112992661A (en) 2021-06-18

Similar Documents

Publication Publication Date Title
CN101419906B (en) Method of forming micro pattern of semiconductor device
CN112992661B (en) Micro LED and manufacturing method thereof
CN105576498A (en) Manufacturing method for narrow ridge GaAs-based laser device and narrow ridge GaAs-based laser device
KR100907898B1 (en) Semiconductor device manufacturing method
CN114038737B (en) Mask plate using method, light-emitting device and manufacturing method thereof
KR20130041627A (en) Photolithography method including dual development process
CN108511574A (en) A kind of preparation method of GaN base light emitting chip
KR100674207B1 (en) Method for manufacturing stamper for the light guide plate use
CN107966876B (en) Photoetching plate, chip module and preparation method of photoetching plate
CN111453693A (en) Preparation method of nanoring
KR20090006703A (en) Method for manufacturing high-aspect-ratio micro structures
KR100946026B1 (en) Method of forming pattern for semiconductor
KR20090072462A (en) Method for fabricating nano-lens
KR20040046702A (en) Method for forming fine pattern of semiconductor device using double exposure
CN203882091U (en) Photosensitive layer structure with light absorption layer
KR100889334B1 (en) Method of forming overlay vernier for semiconductor device
CN109212887A (en) The manufacturing method of patterned substrate and the manufacturing method of semiconductor device
CN114038876B (en) Manufacturing method of light-emitting chip, light-emitting chip and light-emitting device
KR20100026732A (en) Method for fabricating the semiconductor device
JP5966808B2 (en) Manufacturing method of semiconductor device
CN106919015B (en) A kind of semiconductor devices making lithography alignment method
KR20150026186A (en) LED wafer and masking plate for PSS processes
KR100586531B1 (en) Method for settlement of etching time of pattern by pattern density
KR100235304B1 (en) Manufacturing method of spacer for fed
CN117712239A (en) Etching method of light-emitting diode epitaxial wafer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant