CN112986679A - Calibration compensation device and method for spectrum analyzer and spectrum analyzer - Google Patents
Calibration compensation device and method for spectrum analyzer and spectrum analyzer Download PDFInfo
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Abstract
A calibration compensation device for a spectrum analyzer is used for performing calibration compensation on at least one group of original scanning data collected by the spectrum analyzer and comprises a direct memory access module, a data caching module, a compensation logic module and a data uploading module. The direct memory access module is used for sequentially acquiring the compensation data in batches according to the acquisition sequence and sending the compensation data to the data cache module. The compensation logic module is used for acquiring the original scanning data and the acquisition configuration information corresponding to the original scanning data, and acquiring the compensation data corresponding to the acquisition configuration information from the data cache module according to the acquisition configuration information to calibrate and compensate the original scanning data. And the data uploading module is used for outputting the calibrated and compensated original scanning data. Because the compensation data are sequentially acquired according to the data input rate of the original scanning data and are compensated according to needs, the calibration compensation of the original scanning data has less requirements on hardware resources, and the research and development difficulty and the production cost of the spectrum analyzer are reduced.
Description
Technical Field
The invention relates to the technical field of spectrum analyzers, in particular to a calibration compensation device and method for a spectrum analyzer and a spectrum analyzer.
Background
The spectrum analyzer is a common device for researching the spectrum structure of a radio signal, is used for measuring signal parameters such as signal distortion degree, modulation degree, spectrum purity, frequency stability, intermodulation distortion and the like, has wide application, is commonly used in each link of research, development, production and inspection of electronic products, and is called as a radio frequency multimeter of a technician. With the continuous development of modern communication technology, the demand on the spectrum analyzer is higher and higher. Among them, calibration and compensation are the most important ring for ensuring the accuracy of the measurement result of the spectrum analyzer, and how to efficiently compensate the original scan data of the spectrum analyzer to ensure the accuracy of the measurement result is a problem that must be considered by a system designer, so the calibration scheme of the spectrum analyzer is more and more complex, and the generated calibration compensation data is more and more. At present, the calibration compensation of the original scanning data is completed by occupying resources of a CPU and an FPGA, so that the calibration compensation becomes a main bottleneck for restricting the spectrum analyzer from improving the measurement efficiency, and how to efficiently and quickly realize the calibration compensation of the original scanning data becomes a main research and development direction of the spectrum analyzer.
Disclosure of Invention
The invention mainly solves the technical problem of how to realize the calibration compensation of the original scanning data under the condition of reducing the occupation of CPU and FPGA resources.
According to a first aspect, the present invention provides a calibration compensation apparatus for a spectrum analyzer, including a memory direct access module, a data caching module, a compensation logic module, and a data uploading module;
the spectrum analyzer is configured with at least two groups of acquisition configuration information to acquire original scanning data, and each group of acquisition configuration information is sequenced to acquire the original scanning data corresponding to each group of acquisition configuration information according to the sequencing sequence of the acquisition configuration information;
the memory direct access module is connected with the data cache module; the direct memory access module is used for sequentially acquiring compensation data corresponding to the acquisition configuration information from the spectrum analyzer in batches according to the sorting sequence of the acquisition configuration information and sending the compensation data to the data cache module; the direct memory access module at least sends one piece of compensation data corresponding to the acquired configuration information to the data cache module in each batch; the memory direct access module is further used for acquiring the next batch of compensation data from the spectrum analyzer and sending the next batch of compensation data to the data cache module when the data stored in the data cache module is empty;
the data caching module is used for storing the compensation data;
the compensation logic module is connected with the data cache module; the compensation logic module is used for acquiring the original scanning data and the acquisition configuration information corresponding to the original scanning data from the spectrum analyzer, and acquiring the compensation data corresponding to the acquisition configuration information from the data cache module according to the acquisition configuration information so as to perform calibration compensation on the original scanning data;
the data uploading module is connected with the compensation logic module and is used for sending the calibrated and compensated original scanning data to the spectrum analyzer;
the data caching module is further configured to delete the compensation data after sending one compensation data to the compensation logic module.
In one embodiment, the spectrum analyzer stores each compensation data in a high speed memory DDR in an order of the collection configuration information corresponding to the compensation data;
the acquisition configuration information comprises scanning frequency, sweep frequency width, center frequency and/or attenuation value of a front-end attenuator;
and/or the data caching module is a first-in first-out memory.
In one embodiment, the memory direct access module is a DMA module;
the DMA module is in data communication with the high-speed memory DDR through an AXI4 interface;
the DMA module carries out data communication with the data cache module through an AXI4-Stream interface
In one embodiment, the data rate at which the compensation logic module obtains the raw scan data is not greater than the data rate at which the DMA module obtains the compensation data.
In one embodiment, the data uploading module sends the calibrated and compensated original scanning data to the spectrum analyzer through the DMA module;
and/or the data uploading module is in data communication with the DMA module through an AXI4-Stream interface.
In an embodiment, the spectrum analyzer further includes a counter, configured to count the compensation data deleted by the data caching module, where a value of the counter corresponds to the frequency point information of the original scan data acquired by the compensation logic module;
and the compensation logic module acquires corresponding information of the original scanning data and the compensation data according to the numerical value of the counter.
In an embodiment, when the compensation logic module performs calibration compensation on the acquired original scan data and the compensation data corresponding to the original scan data is not acquired from the data caching module, the compensation logic module performs calibration compensation on the original scan data according to the last received compensation data.
According to a second aspect, the present invention provides a spectrum analyser comprising the calibration compensation device of the first aspect.
According to a third aspect, the present invention provides a calibration compensation method for a spectrum analyzer, where the spectrum analyzer configures at least two sets of acquisition configuration information to acquire original scan data, sorts each set of acquisition configuration information, and acquires the original scan data corresponding to each set of acquisition configuration information according to a sorting order of the acquisition configuration information;
according to the sorting sequence of the acquisition configuration information, sequentially batching the compensation data corresponding to the acquisition configuration information, and sending the compensation data to a data cache module; each batch of compensation data corresponding to the acquisition configuration information is sent to the data cache module;
when the data stored in the data cache module is empty, acquiring the next batch of compensation data and sending the compensation data to the data cache module;
acquiring the original scanning data and the acquisition configuration information corresponding to the original scanning data, and acquiring the compensation data corresponding to the acquisition configuration information from the data cache module according to the acquisition configuration information so as to calibrate and compensate the original scanning data;
sending the calibrated and compensated original scanning data to the spectrum analyzer;
the data cache module deletes the compensation data after sending one compensation data to the compensation logic module
According to a fourth aspect, the invention provides a computer readable storage medium having a program stored thereon, the program being executable by a processor to implement the method according to the third aspect.
The invention has the beneficial effects that:
the calibration compensation device for the spectrum analyzer, which is provided in the above embodiment, performs calibration compensation on at least one group of raw scan data sorted by the spectrum analyzer according to the collection order, and includes a memory direct access module, a data caching module, a compensation logic module, and a data uploading module. The direct memory access module is used for sequentially acquiring the compensation data in batches according to the sequencing order and sending the compensation data to the data cache module. The compensation logic module is used for acquiring the original scanning data and the acquisition configuration information corresponding to the original scanning data, and acquiring the compensation data corresponding to the acquisition configuration information from the data cache module according to the acquisition configuration information to calibrate and compensate the original scanning data. And the data uploading module is used for outputting the calibrated and compensated original scanning data. Because the compensation data are sequentially acquired according to the data input rate of the original scanning data and are compensated according to needs, hardware resources required by the calibration compensation of the original scanning data are less, and the research and development difficulty and the production cost of the spectrum analyzer are reduced.
Drawings
FIG. 1 is a schematic diagram of a spectrum analyzer;
FIG. 2 is a schematic structural diagram of a radio frequency scanning channel;
FIG. 3 is a schematic diagram of an exemplary embodiment of a calibration compensation apparatus;
FIG. 4 is a schematic flow chart of a calibration compensation method for a spectrum analyzer in another embodiment;
fig. 5 is a schematic structural diagram of a spectrum analyzer according to another embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
For clear and accurate understanding of the technical solutions of the present application, some technical terms will be described herein.
Broadband (Broadband), which is a relative description, refers to a wide range of frequencies that a signal contains or that a processor can process simultaneously. The larger the frequency range, i.e., the higher the bandwidth (the frequency range occupied by various frequency components included in the signal), the larger the amount of data that can be transmitted.
Digital Down Converters (DDC) mixes an intermediate frequency signal with a local oscillator signal generated by a Numerically Controlled Oscillator (NCO), and obtains a baseband signal through a low-pass filter, thereby implementing a Down conversion function. The digital down-conversion is realized by adopting a digital signal processing technology, and the main components comprise: numerical control oscillation, digital mixing, digital filtering and extraction. At present, due to the limitation of ADC (analog-to-digital converter) and DSP (digital signal processor) development level, it is very difficult to directly perform AD conversion at a very high frequency radio frequency end and then perform digital signal processing, and the problems of ultrahigh sampling rate, huge sample point number, long processing time and the like exist.
An analog attenuator is an electronic component providing attenuation, is widely applied to electronic equipment, and belongs to the prior art. Analog attenuators have two main uses: on the one hand for adjusting the signal size in the circuit and on the other hand for improving the impedance matching in the circuit to obtain a stable load impedance. An existing analog attenuator generally has a carrier input end, a modulation control end, and a modulation output end, where the carrier input end is used to input a carrier signal to be attenuated, the modulation control end is used to input a modulation signal for amplitude modulation of the carrier signal, and the modulation output end is used to modulate an output signal (i.e., the carrier signal after amplitude modulation).
The process of amplitude modulating the carrier signal with the analog attenuator can be understood as:
by modulating signal UΩ(t) to control the carrier signal UC(t) amplitude of vibration, making carrier signal UC(t) amplitude of vibration in accordance with modulation signal UΩThe regularity of (t) is changed. The resulting modulated output signal can be expressed as:
UΩ′(t) =UC(Ec+UΩcos(Ωt))cos(ωct);
in the above formula, UCRepresenting the carrier amplitude, the expression of the carrier signal is UΩ′(t) =UC cos(ωct); UΩRepresenting the modulation amplitude, the expression of the modulated signal is UΩ(t) = Ec+UΩcos (Ω t). The modulation output signal is the product of the modulation signal and the carrier signal as seen by the mathematical equation in the equation.
A Direct Digital Synthesizer (DDS for short), which is a key Digital frequency generator for synthesizing Digital signals of any frequency, and belongs to the prior art. DDS generally includes a signal source and a waveform data generator, wherein the signal source may be a clock for generating a periodic signal with a specific frequency, and the function waveform generator generates a user-defined function waveform or a fixed waveform with an adjustable frequency (common fixed waveforms include sine wave, square wave, step wave, and sawtooth wave) by querying a data table (the data table is used for storing a function waveform of a complete period) under the action of an excitation signal of the signal. Compared with the traditional frequency synthesizer, the DDS has the advantages of low cost, low power consumption, high resolution, quick switching time and the like, and is widely used in the fields of telecommunications and electronic instruments. The DDS further includes a digital-to-analog conversion element, and can convert the synthesized digital signal into an analog signal having a corresponding frequency and amplitude.
A digital-to-analog converter (DAC, also called D/a converter) is a device for converting digital quantity into analog quantity, belongs to the prior art, and is not described in detail herein.
Referring to fig. 1, a schematic diagram of a spectrum analyzer is shown, the spectrum analyzer includes: a gain adjusting module 11, at least one radio frequency scanning channel (RF channel) 12, a radio frequency channel selection switch (RF channel selection switch) 13, a filtering module 14, an analog-to-digital sampling module (ADC sampling module) 15, a digital signal processing module 16 and a display module 17, wherein the gain adjusting module 11 is configured to adjust a gain of an input signal RFIN; the radio frequency scanning channels 12 are used for radio frequency scanning, and each radio frequency scanning channel corresponds to a different radio frequency scanning frequency band; the radio frequency scanning channel selection switch 13 is used for controlling the switching of the radio frequency scanning channel; the filtering module 14 is configured to filter a radio frequency signal output by the radio frequency scanning channel; the analog-to-digital sampling module 15 is configured to perform analog-to-digital conversion on the filtered radio frequency signal and output a digital radio frequency signal; the digital signal processing module 16 is configured to perform signal processing on the digital radio frequency signal and output a frequency domain waveform; the display module 17 is used for displaying the frequency domain waveform.
Referring to fig. 2, a schematic structural diagram of a radio frequency scanning channel is shown, where the radio frequency scanning channel includes N frequency mixing modules, each frequency mixing module includes a frequency mixer 1, a local oscillator signal generator, a gain adjuster, and a filter, and by switching the frequency of the local oscillator signal generator 1 IN the first frequency mixing module, and using the frequency conversion principle of the frequency domain, the frequency component of the input signal IN is gated to reach the frequency point of the first intermediate frequency, so as to implement a radio frequency scanning process on the input signal IN. However, in actual spectrum analyzer measurement, complicated conditions such as multi-stage frequency conversion, multiple radio frequency scanning channels, and multi-stage filtering are generally involved, and radio frequency scanning work is performed by combining and controlling a plurality of external devices such as phase-locked loops, radio frequency switches, filters, amplifiers, attenuators, and the like to present frequency domain waveforms to users.
Calibration compensation of a spectrum analyzer for raw scan data is generally achieved in three ways:
1) compensation is performed by the CPU of the digital signal processing module. Calibration compensation is performed when the CPU acquires raw scan data. When the data rate of the original scanning data is high, the method brings great computing pressure to the CPU, and occupies excessive computing resources of the CPU.
2) And the FPGA of the digital signal processing module is used for compensation. Most spectrum analyzer systems use an FPGA as a high-speed processor, and calibration data is stored in a high-speed processor layer (hereinafter, the high-speed processor is synonymous with the FPGA), and the raw scan data is compensated by the calibration data at the FPGA layer. The calibration data is stored in the FPGA, so that excessive precious and rare storage resources in the FPGA are temporarily used, design resources of other modules are necessarily compressed, and the flexibility and the expandability of FPGA system design are very unfavorable.
3) And (4) hanging a high-speed memory. A high-speed memory (a typical device is a DDR) is externally hung at the end of the FPGA, and calibration data is stored in the high-speed memory, so that the problem of insufficient internal storage resources of the FPGA can be solved, the cost of the whole system is increased, and the design difficulty of a hardware system is obviously increased.
The method I is adopted to calibrate and compensate the original scanning data, so that excessive computing resources of a CPU are occupied, the whole CPU system is blocked, and the user experience is very poor. And the second mode is adopted to calibrate and compensate the original scanning data, and when the bandwidth of the spectrum analyzer is larger and larger, and the calibration scheme is more and more complex, precious and rare storage resources inside the FPGA can be excessively occupied, so that the design resources of other modules are necessarily compressed, and the flexibility and the expandability of the FPGA system design are very unfavorable. And the calibration compensation of the original scanning data is performed in a third mode, so that the cost of the whole system is increased, and the design difficulty of a hardware system is obviously increased.
The calibration data compensation method does not need to occupy excessive computing resources of a CPU (Central processing Unit), does not greatly occupy internal storage resources of the FPGA, and does not need to plug a high-speed memory at the end of the FPGA externally.
The technical solution of the present application will be specifically described with reference to the following examples.
Example one
Referring to fig. 3, which is a schematic structural diagram of an embodiment of the calibration compensation apparatus, the calibration compensation apparatus 2 includes a direct memory access module 10, a data buffer module 20, a compensation logic module 30, and a data upload module 40. The spectrum analyzer 1 at least configures two sets of acquisition configuration information to acquire original scan data, and sorts each set of acquisition configuration information to acquire original scan data corresponding to each set of acquisition configuration information according to the sorting order of the acquisition configuration information. The memory direct access module 10 is connected to the data cache module 20, and the memory direct access module 10 is configured to sequentially acquire compensation data corresponding to the acquired configuration information from the spectrum analyzer 1 in batches according to the sorting order of the acquired configuration information, and send the compensation data to the data cache module 20. The direct memory access module 10 sends at least one compensation data corresponding to the collected configuration information to the data caching module 20 in batch. The direct memory access module 10 is further configured to obtain a next batch of compensation data from the spectrum analyzer 1 and send the next batch of compensation data to the data buffer module 20 when the data stored in the data buffer module 20 is empty. The data buffer module 20 is used for storing compensation data. The compensation logic module 30 is connected to the data cache module 20, and the compensation logic module 30 is configured to obtain the original scan data and the acquisition configuration information corresponding to the original scan data from the spectrum analyzer 1, and obtain the compensation data corresponding to the acquisition configuration information from the data cache module 20 according to the acquisition configuration information, so as to perform calibration compensation on the original scan data. The data uploading module 40 is connected to the compensation logic module 30, and the data uploading module 40 is configured to send the calibrated and compensated original scan data to the spectrum analyzer 1. The data buffer module 20 is further configured to delete each compensation data sent to the compensation logic module 30.
In one embodiment, the spectrum analyzer 1 stores each compensation data in the high speed memory DDR in the sorted order of the acquisition configuration information corresponding to the compensation data. In one embodiment, the acquisition configuration information includes a sweep frequency, a sweep width, a center frequency, and an attenuation value of the front end attenuator. In one embodiment, the data buffer module 20 is a first-in-first-out memory. In one embodiment, the DMA module 10 is a DMA module, and the DMA module performs data communication with the high speed memory DDR of the spectrum analyzer 1 through an AXI4 interface, and the DMA module performs data communication with the data cache module 20 through an AXI4-Stream interface. In one embodiment, the data rate at which the compensation logic 30 retrieves the raw scan data is not greater than the data rate at which the DMA module retrieves the compensation data. In one embodiment, the data upload module 40 sends the calibration-compensated raw scan data to the spectrum analyzer 1 through the DMA module. In one embodiment, the data upload module 40 communicates data with the DMA module via the AXI4-Stream interface.
In an embodiment, the calibration compensation apparatus further includes a counter, configured to count the compensation data deleted by the data caching module 20, where a value of the counter corresponds to the frequency point information of the original scanning data acquired by the compensation logic module 30, and the compensation logic module 30 acquires corresponding information of the original scanning data and the compensation data according to the value of the counter. In one embodiment, when the compensation logic module 30 performs calibration compensation on the acquired original scan data and does not acquire the compensation data corresponding to the original scan data from the data buffer module 20, the compensation logic module performs calibration compensation on the original scan data according to the last received compensation data.
The embodiment of the application also discloses a spectrum analyzer, which comprises the calibration compensation device for performing calibration compensation on the original scanning data.
In the embodiment of the application, the calibration compensation device for the spectrum analyzer is used for performing calibration compensation on at least one group of original scanning data collected by the spectrum analyzer, and comprises a direct memory access module, a data caching module, a compensation logic module and a data uploading module. The direct memory access module is used for sequentially acquiring the compensation data in batches according to the acquisition sequence and sending the compensation data to the data cache module. The compensation logic module is used for acquiring the original scanning data and the acquisition configuration information corresponding to the original scanning data, and acquiring the compensation data corresponding to the acquisition configuration information from the data cache module according to the acquisition configuration information to calibrate and compensate the original scanning data. And the data uploading module is used for outputting the calibrated and compensated original scanning data. Because the compensation data are sequentially acquired according to the data input rate of the original scanning data and are compensated according to needs, the calibration compensation of the original scanning data has less requirements on hardware resources, and the research and development difficulty and the production cost of the spectrum analyzer are reduced.
Example two
Referring to fig. 4, a schematic flowchart of a calibration compensation method for a spectrum analyzer in another embodiment is shown, the method is used for performing calibration compensation on original scan data, where the spectrum analyzer configures at least two sets of acquisition configuration information to acquire the original scan data, and sorts each set of acquisition configuration information to acquire the original scan data corresponding to each set of acquisition configuration information according to the sorting order of the acquisition configuration information. The calibration compensation method comprises the following steps:
and step 100, acquiring compensation data in batches in sequence.
And sequentially batching the compensation data corresponding to the acquired configuration information in batches according to the sorting sequence of the acquired configuration information, and sending the compensation data to a data cache module. And when the data stored in the data cache module is empty, the next batch of compensation data is acquired and sent to the data cache module.
And 200, acquiring original scanning data and performing calibration compensation.
The method comprises the steps of obtaining original scanning data and acquisition configuration information corresponding to the original scanning data, and obtaining compensation data corresponding to the acquisition configuration information from a data cache module according to the acquisition configuration information so as to calibrate and compensate the original scanning data. And the data cache module deletes the compensation data after sending one compensation data to the compensation logic module.
And step 300, sending out the compensated original scanning data.
And sending the calibrated and compensated original scanning data to a spectrum analyzer.
The following describes the implementation steps of the calibration compensation method by using an embodiment.
Referring to fig. 5, a schematic diagram of a spectrum analyzer according to another embodiment is shown, the spectrum analyzer has dual controllers, which are a CPU and an FPGA, respectively, and respectively constitute a CPU subsystem and an FPGA subsystem, the CPU subsystem has a high speed memory DDR, and the FPGA subsystem does not have an external high speed memory. Before the frequency scanning of the spectrum analyzer starts, the software service logic sequentially puts the compensation data of the machine in a corresponding section of DDR address space according to the current scanning condition, and the software user logic stores the compensation data corresponding to the current scanning parameter into the DDR every time the user changes the scanning parameter of the spectrum analyzer. The sweep parameters include, but are not limited to, sweep width, center frequency, front attenuator size, etc. The FPGA subsystem comprises a DMA (Direct Memory Access) module, an AXI4 interface and an AXI4-Stream interface are respectively arranged at two ends of the DMA module, the DMA module is used as a middle unit, the data exchange of DDR in the FPGA subsystem and the CPU subsystem can be directly realized without the participation of a CPU (central processing unit) of a spectrum analyzer, and the data exchange is full duplex, namely data can be written and read in the DDR at the same time. When the scanning starts to be initiated, the FPGA logic at the back end of the DMA module requests the DMA module to move the compensation data from the DDR to the FPGA logic through the AXI4-Stream interface. Because the AXI4-Stream interface requires the devices at both ends to have a handshake process when data exchange is performed by the interface, for the present invention, the handshake process is that the DMA module generates a tvalid signal, and the FPGA logic terminal generates a trace signal, and when both signals are valid, a request for shifting compensation data is generated. By the method, the compensation data can be requested as required without storing the compensation data in the internal storage resource of the FPGA in advance, so that the aim of saving the internal storage resource of the FPGA is fulfilled. However, in a specific implementation, when the compensation logic module of the FPGA receives the scanned original data sent by the digital down conversion unit of the spectrum analyzer and initiates a request for retrieving the compensation data, the DMA module does not immediately return a compensation data. Because there is a delay in the path from the DDR to the DMA output, the delay includes the fixed read delay of the DDR chip and the delay of the Memory interface. In view of the reason, the data cache module with the first-in first-out structure is designed in the FPGA subsystem, the size of the data cache unit is far smaller than the size of the resource occupied by storing all compensation data in the FPGA, and the more the compensation data, the more obvious the advantage of singly designing the data cache unit. Before the effective original scanning data enters the compensation logic module, the compensation data is buffered in the data buffer unit in advance, and the compensation data is not requested from the DMA until the unit is full. When the effective original scanning data is input into the compensation logic module, the compensation logic module reads the compensation data from the data cache module to compensate the original scanning data, once the data cache unit is read, the full mark of the unit will be invalid, and thus, a request for retrieving the compensation data is continuously initiated to the DMA module.
When the DMA module interacts with the DDR, the clock of the AXI4 interface is equal to the processing clock of the FPGA subsystem, and due to the fact that the digital down-conversion unit extracts the original data, the data rate of the data stream entering the compensation logic module is smaller than the processing clock of the FPGA subsystem, and the speed of the request for moving the compensation data generated by the FPGA logic end is smaller than or equal to the data rate of the data stream entering the compensation logic, so that the situation that the data cache unit is empty due to the fact that the DMA cannot move the compensation data in time can not occur.
In an embodiment, the present application further includes an error handling mechanism, when an unknown error occurs in the whole compensation data moving system, that is, the data cache module is empty, the valid original scan data after compensation is performed by the last compensation data (which is set to be replaced by 0 when no data exists in the data cache unit) in the data cache module. Because the spectrum analyzer takes some frequency points for calibration according to a fixed frequency interval (denoted as f _ cali _ step) during calibration, the frequency point information represented by the current compensation data can be determined only by designing a counter _ cali at the compensation logic unit, but the frequency point information f _ start _ cali of the first compensation data is configured in advance by the CPU _ Interface module (the CPU _ Interface module is mainly responsible for receiving some non-real-time information configured by the CPU subsystem). Specifically, each time one data is read from the data buffer unit, the counter is incremented by one, so that the frequency point information of the compensation data can be described simply by the following formula:
f_cali = f_start_cali + (counter_cali – 1) * f_cali_step，
wherein, counter _ cali > = 1; and the data flow entering the compensation logic module, wherein each data also corresponds to a frequency point, and the specific relationship is described by the following formula, similar to the calculation of the compensation data frequency point information:
f_raw_data=f_raw_data_start+(counter_raw_data–1)*f_raw_data_step，
wherein counter _ raw _ data > = 1.
When f _ raw _ data < = f _ cali, compensating the original scanning data by using the current compensation data; on the contrary, the compensation logic module generates a read enable signal, reads out new compensation data from the data buffer unit, and repeatedly compares the sizes of the f _ raw _ data and the f _ cali. After the original scanning data is compensated, the compensation logic module sends the original scanning data to the data uploading unit, and finally the original scanning data reaches the CPU subsystem through the DMA and is subjected to subsequent processing by the CPU subsystem.
The key point of the method is that the calibrated compensation data is stored in the DDR of the CPU subsystem, the DMA and the AXI4-Stream interface are utilized at the FPGA end, the compensation data in the DDR is required to compensate the original scanning data as required, the CPU is not required to be occupied by too much computing resources, the internal storage resources of the FPGA are not greatly occupied, the design difficulty of other modules of the FPGA is reduced, and the system expansion is facilitated. And a high-speed memory does not need to be externally hung at the FPGA end, so that the system cost and the hardware system design difficulty are not increased.
Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by computer programs. When all or part of the functions of the above embodiments are implemented by a computer program, the program may be stored in a computer-readable storage medium, and the storage medium may include: a read only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to realize the above functions. For example, the program may be stored in a memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above may be implemented. In addition, when all or part of the functions in the above embodiments are implemented by a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and may be downloaded or copied to a memory of a local device, or may be version-updated in a system of the local device, and when the program in the memory is executed by a processor, all or part of the functions in the above embodiments may be implemented.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A calibration compensation device for a spectrum analyzer is characterized by comprising a direct memory access module, a data cache module, a compensation logic module and a data uploading module;
the spectrum analyzer is configured with at least two groups of acquisition configuration information to acquire original scanning data, and each group of acquisition configuration information is sequenced to acquire the original scanning data corresponding to each group of acquisition configuration information according to the sequencing sequence of the acquisition configuration information;
the memory direct access module is connected with the data cache module; the direct memory access module is used for sequentially acquiring compensation data corresponding to the acquisition configuration information from the spectrum analyzer in batches according to the sorting sequence of the acquisition configuration information and sending the compensation data to the data cache module; the direct memory access module at least sends one piece of compensation data corresponding to the acquired configuration information to the data cache module in each batch; the memory direct access module is further used for acquiring the next batch of compensation data from the spectrum analyzer and sending the next batch of compensation data to the data cache module when the data stored in the data cache module is empty;
the data caching module is used for storing the compensation data;
the compensation logic module is connected with the data cache module; the compensation logic module is used for acquiring the original scanning data and the acquisition configuration information corresponding to the original scanning data from the spectrum analyzer, and acquiring the compensation data corresponding to the acquisition configuration information from the data cache module according to the acquisition configuration information so as to perform calibration compensation on the original scanning data;
the data uploading module is connected with the compensation logic module and is used for sending the calibrated and compensated original scanning data to the spectrum analyzer;
the data caching module is further configured to delete the compensation data after sending one compensation data to the compensation logic module.
2. The calibration compensation apparatus of claim 1, wherein the spectrum analyzer stores each of the compensation data in a high speed memory DDR in an order of sorting of the acquisition configuration information corresponding to the compensation data;
the acquisition configuration information comprises scanning frequency, sweep frequency width, center frequency and/or attenuation value of a front-end attenuator;
and/or the data caching module is a first-in first-out memory.
3. The calibration compensation apparatus of claim 2, wherein the memory direct access module is a DMA module;
the DMA module is in data communication with the high-speed memory DDR through an AXI4 interface;
the DMA module is in data communication with the data cache module through an AXI4-Stream interface.
4. The calibration compensation device of claim 3, wherein the data rate at which the compensation logic module retrieves the raw scan data is not greater than the data rate at which the DMA module retrieves the compensation data.
5. The calibration compensation apparatus of claim 3, wherein the data upload module sends the calibration compensated raw scan data to the spectrum analyzer via the DMA module;
and/or the data uploading module is in data communication with the DMA module through an AXI4-Stream interface.
6. The calibration compensation device of claim 1, further comprising a counter for counting the compensation data deleted by the data buffer module, wherein the value of the counter corresponds to the frequency point information of the original scan data obtained by the compensation logic module;
and the compensation logic module acquires corresponding information of the original scanning data and the compensation data according to the numerical value of the counter.
7. The calibration compensation device of claim 1, wherein when the compensation logic module performs calibration compensation on the acquired original scan data and the compensation data corresponding to the original scan data is not acquired from the data buffer module, the compensation logic module performs calibration compensation on the original scan data according to the last received compensation data.
8. A spectrum analyser comprising a calibration compensation device as claimed in any one of claims 1 to 7.
9. A calibration compensation method for a spectrum analyzer is characterized in that the spectrum analyzer is provided with at least two groups of acquisition configuration information to acquire original scanning data, each group of acquisition configuration information is sorted, and the original scanning data corresponding to each group of acquisition configuration information is acquired according to the sorting sequence of the acquisition configuration information;
according to the sorting sequence of the acquisition configuration information, sequentially batching the compensation data corresponding to the acquisition configuration information, and sending the compensation data to a data cache module; each batch of compensation data corresponding to the acquisition configuration information is sent to the data cache module;
when the data stored in the data cache module is empty, acquiring the next batch of compensation data and sending the compensation data to the data cache module;
acquiring the original scanning data and the acquisition configuration information corresponding to the original scanning data, and acquiring the compensation data corresponding to the acquisition configuration information from the data cache module according to the acquisition configuration information so as to calibrate and compensate the original scanning data;
sending the calibrated and compensated original scanning data to the spectrum analyzer;
and deleting the compensation data after the data cache module sends one compensation data to the compensation logic module.
10. A computer-readable storage medium, characterized in that the medium has stored thereon a program which is executable by a processor to implement the method of claim 9.
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