CN112967670A - Display driving method, device and chip, display device and storage medium - Google Patents
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
- G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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Abstract
The invention provides a display driving method, a display driving apparatus, a display device, and a computer-readable storage medium. The display driving method includes: generating a clock signal; calculating period data representing one frame time by a clock signal; calculating on-time data of the pulse width modulation signal according to the period data and the pixel value of the target pixel; the driving current of the display device is modulated according to the on-time data to drive the display device. According to the display driving technology provided by the invention, the pins of the driving chip can be saved, and the integration level of the driving circuit is improved.
Description
Technical Field
The present invention relates to the field of image display technologies, and in particular, to a display driving method, a display driving apparatus, a display driving chip, a display device, and a computer-readable storage medium.
Background
Techniques for dimming displays, in particular LED (light emitting diode) displays, to control the display grey scale, such as PWM (Pulse Width Modulation) techniques, are known. When dimming a display, it is necessary to ensure that the period of the dimming signal is synchronized with the image scanning period. Currently, Synchronization is ensured by determining a clock frequency inside the display driving chip from a signal related to image scanning, for example, a Vsync (Vertical Synchronization) signal, outside the chip, and thereby determining a dimming period from the clock frequency. This technique results in the need to add a Data Clock (DCLK) pin and/or a Gray Clock (GCLK) pin to the driver chip, reducing the integration of the chip.
Disclosure of Invention
In view of the above, the present invention is directed to a display driving method, a display driving apparatus, a display driving chip, a display device, and a computer readable storage medium, which can save pins of a chip and increase the integration level of the chip.
In one aspect, the present invention provides a display driving method, including: generating a clock signal; calculating period data representing one frame time by a clock signal; calculating on-time data of the pulse width modulation signal according to the period data and the pixel value of the target pixel; the driving current of the display device is modulated according to the on-time data to drive the display device.
According to a specific embodiment of the present invention, the calculating of the on-time data of the pwm signal based on the period data and the pixel value of the target pixel includes: the on-time data is calculated according to the following formula: dON_TIME＝(DDISP/DFULL_SCALE)×DTFX r, wherein DON_TIMERepresenting on-time data, DDISPRepresenting pixel value, DFULL_SCALERepresenting the highest luminance value, D, of the target pixelTFRepresenting period data, r represents a positive real number less than or equal to 1.
According to a particular embodiment of the invention, generating a clock signal comprises: a clock signal is generated by an internal clock source.
According to a particular embodiment of the invention, the internal clock source comprises a quartz crystal oscillator, a silicon crystal oscillator, a microelectromechanical system oscillator, or a complementary metal oxide semiconductor oscillator.
According to a particular embodiment of the present invention, calculating, by a clock signal, period data representing a frame time includes: calculating the period of the vertical synchronous signal through a clock signal; the period data indicating one frame time is determined according to the period of the vertical synchronization signal.
According to a specific embodiment of the present invention, determining period data indicating a frame time according to a period of a vertical synchronization signal includes: determining period data indicating a frame time according to a period of a vertical synchronization signal; or determines the period data indicating one frame time based on an average value of the periods of the plurality of vertical synchronization signals.
According to a particular embodiment of the invention, modulating a drive current of a display device according to on-time data to drive the display device comprises: calculating the period of the pulse width modulation signal according to the period data and the clock signal; modulating a driving current of the display device according to the on-time data and the period of the pulse width modulation signal to drive the display device; wherein, the calculation accuracy of the period of the vertical synchronization signal is lower than that of the pulse width modulation signal.
According to the display driving method, the display driving device, the display driving chip, the display device and the storage medium, the clock signal is generated inside the driving chip to measure the one-frame time, the internal clock frequency is not determined according to the external signal (such as the Vsync signal) representing the one-frame time, the external Data Clock (DCLK) and/or Gray Clock (GCLK) input pins can be omitted, the integration level of the driving circuit is increased, and the pin resources of the driving chip are saved.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in more detail embodiments of the present application with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings, like reference characters generally refer to the same or similar parts throughout the several views, and wherein:
fig. 1 shows a schematic diagram of a PWM signal generating circuit in the art;
fig. 2 shows a schematic diagram of a PWM signal generating circuit in the art;
FIG. 3 is a flow chart illustrating a display driving method according to an embodiment of the invention;
FIG. 4 is a flow chart illustrating a display driving method according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a display driving apparatus according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a display driver chip according to an embodiment of the invention;
fig. 7 illustrates a schematic configuration diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention is described in detail below with reference to specific embodiments in order to make the concept and idea of the present invention more clearly understood by those skilled in the art. It is to be understood that the embodiments presented herein are only a few of all embodiments that the present invention may have. Those skilled in the art who review this disclosure will readily appreciate that many modifications, variations, or alterations to the described embodiments, either in whole or in part, are possible and within the scope of the invention as claimed.
As used herein, the terms "a," "an," and the like are not intended to mean that there is only one of the described items, but rather that the description is directed to only one of the described items, which may have one or more. As used herein, the terms "comprises," "comprising," and other similar words are intended to refer to logical interrelationships, and are not to be construed as referring to spatial structural relationships. For example, "a includes B" is intended to mean that logically B belongs to a, and not that spatially B is located inside a. Furthermore, the terms "comprising," "including," and other similar words are to be construed as open-ended, rather than closed-ended. For example, "a includes B" is intended to mean that B belongs to a, but B does not necessarily constitute all of a, and a may also include C, D, E and other elements.
Herein, some operations are described in order. However, those skilled in the art will appreciate that these operations are not necessarily performed in the order of description, nor are they performed only once throughout the flow. In actual implementation, the execution order of these operations may be reversed, some operations may be executed at the same time or different times, and the execution times of the operations may be different from each other.
The terms "embodiment," "present embodiment," "an embodiment," "one embodiment," and "one embodiment" herein do not mean that the pertinent description applies to only one particular embodiment, but rather that the description may apply to yet another embodiment or embodiments. Those of skill in the art will understand that any of the descriptions given herein for one embodiment can be combined with, substituted for, or combined with the descriptions of one or more other embodiments to produce new embodiments, which are readily apparent to those of skill in the art and are intended to be within the scope of the present invention.
In the embodiments of the present invention, the display driving may refer to modulating the phase, peak value, frequency, etc. of a potential signal applied to the electrodes of the display device to establish a driving electric field to achieve the display effect of the display device. Common driving methods include constant current driving and constant voltage driving. For example, according to the current-voltage characteristics of the LED, it is known that the power of the LED is sensitive to the voltage across the PN junction and approximately linearly related to the current flowing through the PN junction, so that the power stability of the LED in the constant current driving mode is better. The constant current driving method includes: linear regulated drive, switch regulated drive, and current feedback regulated drive.
In the embodiments of the present invention, the display driving is usually implemented by a display driving chip or a display driving circuit. The display driving chip generally has a dimming function for a display device or a pixel point. Current dimming approaches include analog dimming, digital dimming, and pulsed dimming. Pulse dimming may include pulse frequency dimming (PFM), pulse width dimming (PWM), and pulse skip cycle dimming (PSM).
In some control circuits of dimmable displays in the art, it is common practice to use a row frequency control signal and an image frequency control signal of a display unit as synchronization signals to periodically generate PWM signals for driving the display in segments, thereby implementing the dimming function.
Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of a PWM signal generating circuit of a tunable optical display in the art; fig. 2 is a schematic diagram of a PWM signal generating circuit of another adjustable display in the art.
As shown in fig. 1, the PWM signal generating circuit has a phase-locked loop unit 11 and a PWM signal generating unit 12, the phase-locked loop unit 11 is configured to generate a line frequency control signal GCLK (also referred to as a gray scale clock) inside a chip according to an image frequency control signal DCLK (also referred to as a data clock) outside the chip, and the PWM signal generating unit 12 is configured to generate a pulse width modulation signal PWM according to the image frequency control signal DCLK and the line frequency control signal GCLK.
As shown in fig. 2, the PWM signal generating circuit has a PWM signal generating unit 20, and the PWM signal generating unit 20 generates the pulse width modulation signal PWM according to the image frequency control signal DCLK and the line frequency control signal GCLK outside the chip.
As can be seen from the above, the PWM signal generating circuits shown in fig. 1 and 2 need to provide the video frequency control signal DCLK and the line frequency control signal GCLK from the outside to synchronize the timing of the PWM signal PWM with the video scanning.
A display driving method 300 according to an embodiment of the present invention is described below with reference to fig. 3.
According to the present embodiment, the display driving method 300 includes:
s310, generating a clock signal;
s320, calculating period data indicating a frame time by using the clock signal;
s330, calculating the on-time data of the pulse width modulation signal according to the period data and the pixel value of the target pixel;
and S340, modulating the driving current of the display device according to the conduction time data so as to drive the display device.
According to the embodiment, the clock signal is generated inside the driving chip to measure the time of one frame, and the internal clock frequency is not determined according to the external signal (such as the Vsync signal) representing the time of one frame, so that the external Data Clock (DCLK) and/or gray scale clock (GCLK) input pins can be omitted, the integration level of the driving circuit is increased, and the pin resources of the driving chip are saved.
In one embodiment, the clock signal may refer to a pulse signal having periodicity generated by a circuit, and the clock signal is used to provide a reference for data transmission between a plurality of circuits in a system, which are synchronously executed, and between different systems. The clock signal has a fixed clock frequency, which is the inverse of the clock period.
In an embodiment, generating the clock signal may be accomplished by an internal or external clock generator. The clock generator may be a phase Locked Loop (LLP), an oscillating circuit or an oscillator. The phase-locked loop is a feedback control circuit that controls the frequency and phase of an oscillation signal inside the loop using an externally input reference signal. In the working process of the phase-locked loop, when the frequency of the output signal is equal to that of the input signal, the output voltage and the input voltage keep a fixed phase difference value, namely the phase of the output voltage and the phase of the input voltage are locked. A phase-locked loop is generally composed of three parts, namely a phase detector, a loop filter and a voltage-controlled oscillator. The oscillating circuit may refer to a circuit capable of generating a periodic oscillation frequency signal, for example, a circuit capable of generating an oscillating current, which is a current whose magnitude and direction periodically change. The oscillation circuit may include an RC (resistance capacitance) oscillation circuit and an LC (inductance capacitance) oscillation circuit. An oscillator may refer to an electronic component used to generate a repetitive electrical signal, typically a sine wave or a square wave. The oscillator may include a free-running oscillator, an independent oscillator, a crystal oscillator, a tuning fork oscillator, and the like.
In one embodiment, a frame time may refer to a display time of a frame of a picture. In one embodiment, a frame time may refer to a time when the display finishes scanning a frame of image. In one embodiment, a frame time may be a time determined by a refresh frequency of the display, and a time interval between two adjacent refreshes is a frame time. In one embodiment, a frame time may be a time determined by the Vsync signals, and a time interval between two adjacent Vsync signals is a frame time.
In one embodiment, the period data may refer to data indicating a frame time, which is generated according to a count of the clock signal. For example, if a frame time corresponds to exactly two counts of the clock signal, the period data may be 2.
In one embodiment, calculating the period data for indicating a frame time by using the clock signal may refer to measuring the time of a frame picture by using a count of the clock signal, and determining the data for indicating a frame time, i.e., the period data, by using the count of the clock signal. In one embodiment, calculating the period data indicating one frame time by using the clock signal may refer to measuring an external signal indicating one frame picture time by using the clock signal, thereby obtaining the period data indicating one frame time. Such an external signal may be a Vsync signal, a signal related to the Vsync signal (e.g., a signal of a transmission register for each frame, a display data input Signal (SDI), a display data output Signal (SDO), etc.), or another signal capable of indicating a time of one frame, such as an Hsync (horizontal synchronization) signal. One frame time is calculated from the Hsync signal, for example, by multiplying the time interval between two Hsync signals (i.e., the time to scan a line of pixels) by the number of lines of pixels of the display screen to obtain a frame time.
In one embodiment, PWM may refer to an analog control method that controls the on/off of the switching devices of the circuit so that the output end obtains a series of pulses with equal amplitude, and these pulses are used to replace a sine wave or a desired waveform. The PWM includes phase voltage control PWM, pulse width PWM method, random PWM, SPWM method, line voltage control PWM, and the like. In one embodiment, PWM can be used to adjust the output dc average voltage, which is equal to the peak voltage x duty cycle for a rectangular wave, where the duty cycle is the ratio of the high level time to the period in one pulse period, for example, the peak voltage is equal to 5V, and the duty cycle is equal to 50% of the average voltage of the square wave signal is equal to 2.5V. In one embodiment, the PWM signal is a series of levels, one high and one low, that are combined to convert the analog signal into the encoded signal required by the digital circuit. In one embodiment, the on-time of the PWM signal may refer to a time of high level. In one embodiment, the on-time of the PWM signal may refer to a high time in one PWM period, or may refer to a sum of high times in a plurality of PWM periods.
In one embodiment, the target pixel may refer to a pixel for which the current PWM signal on-time is calculated. The target pixel may be any one of the pixels in the display screen. After all target pixels in the display device are dimmed and driven, the scanning and displaying of the whole picture is completed.
In one embodiment, the on-time data of the PWM signal is calculated based on the period data and the pixel value of the target pixel, which may be a time for calculating a high level in the PWM signal for adjusting the display luminance (gray scale) of one pixel based on one frame time determined by the period data and the gray scale value of the target pixel.
In one embodiment, the driving current of the display device may refer to a current for causing a display device of the display device to emit light and controlling the brightness or gray scale of the display device.
In one embodiment, modulating the driving current of the display device according to the on-time data to drive the display device may be to control the on-time of the driving current of the display device according to the high level time in the PWM dimming signal determined by the on-time data, so that the on-time of the driving current is in accordance with the time specified by the on-time data, thereby controlling the brightness of the target pixel to be at a desired value. This operation is performed for all pixels, and the driving of the entire display device is completed.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 1 and may include one or more features of one or more of all of the embodiments described above.
According to the present embodiment, S130 includes:
the on-time data is calculated according to the following formula:
DON_TIME＝(DDISP/DFULL_SCALE)×DTF×r，
wherein D isON_TIMERepresenting on-time data, DDISPRepresenting pixel value, DFULL_SCALERepresenting the highest luminance value, D, of the target pixelTFRepresenting period data, r represents a positive real number less than or equal to 1.
According to the embodiment, the conduction time can be calculated according to the one-frame picture time counted by the internal clock through a simple calculation mode, so that the conduction time and the picture scanning time are unified, and the synchronization of PWM dimming and image scanning is realized.
In one embodiment, DON_TIMEMay refer to data indicating an on time (high time) in a PWM period, which is measured by an internal clock signal. For example, if the on-time of the PWM signal for one pixel corresponds to two counts of the clock signal, DON_TIMEThe data represented may be 2.
In one embodiment, DDISPMay be used to represent the pixel value or gray value of any one pixel in the display. After the above calculation is performed for all the pixels, the entire display screen is dimmed.
In one embodiment, DFULL_SCALEMay refer to the highest pixel value of the target pixel. For example, for a pixel value of 8bit representation, DFULL_SCALEMay refer to 255, DDISPMay refer to any value between 0 and 255.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 3 and may include one or more features of one or more of all of the embodiments described above.
According to the present embodiment, S310 includes:
a clock signal is generated by an internal clock source.
According to the embodiment, the clock signal is generated by the internal clock source, pins (including a DCLK pin and a GCLK pin) required by introducing the external clock signal into the chip can be omitted, and the integration level of the chip is further improved.
In one embodiment, the internal clock source may refer to a clock generator that is provided inside the chip and capable of providing a stable clock signal. The internal clock source may be constituted by an internal crystal oscillator or an internal oscillation circuit.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 3 and may include one or more features of one or more of all of the embodiments described above.
According to this embodiment, the internal clock source comprises a quartz crystal oscillator, a silicon crystal oscillator, a MEMS (Micro-Electro-Mechanical System) oscillator, or a CMOS (Complementary Metal Oxide Semiconductor) oscillator.
According to the present embodiment, the internal clock source is made by one of a quartz crystal oscillator, a silicon crystal oscillator, a MEMS oscillator and a CMOS oscillator, and a stable and reliable clock signal generator can be made by using the existing mature oscillator technology.
In one embodiment, the quartz crystal oscillator may refer to a device manufactured by using the principle that when the frequency of an electrical signal is equal to the natural frequency of a quartz crystal, the crystal generates a resonance phenomenon due to a piezoelectric effect. The quartz crystal oscillator may include a wafer type quartz crystal oscillator, a rod type quartz crystal oscillator, a tuning fork type quartz crystal oscillator.
In one embodiment, a silicon crystal oscillator may refer to a crystal oscillator made using a silicon crystal instead of a quartz crystal.
In one embodiment, the MEMS oscillator may refer to a programmable oscillator manufactured by a MEMS, and belongs to an active crystal oscillator.
In one embodiment, a CMOS oscillator may refer to a basic waveform generation circuit based on CMOS.
Another embodiment according to the present invention is described below with reference to fig. 4, which is a specific example of the embodiment of fig. 3 and may include one or more features of one or more of all of the embodiments described above.
According to the present embodiment, S320 includes:
s321, calculating the period of the vertical synchronous signal through the clock signal;
s322, determines the period data indicating one frame time according to the period of the vertical synchronization signal.
According to the present embodiment, calculating one frame time from the vertical synchronization Vsync signal can represent the scanning time of one frame in a simple and efficient manner, thereby accurately deriving the period data representing one frame time without causing a large calculation overhead.
In one embodiment, the Vsync signal may refer to a signal added between two frames. The Vsync signal is a pulse of relatively long duration, possibly lasting for one or several lines of the scanning time, but during this time no pixel signals are present.
In one embodiment, the Vsync signal operates on the principle that, at a certain point in time, one screen refresh cycle is completed, entering a short refresh blank period; at the moment, a Vsync signal is generated, the copying operation is completed firstly, and then the CPU/GPU is informed to draw the next frame of image; only when the Vsync signal is generated will the CPU/GPU begin drawing.
In one embodiment, the basic idea of Vsync is to synchronize the FPS (Frames Per Second) with the refresh rate of the display to avoid a phenomenon known as "tearing". Vsync solves the tearing problem by establishing a provision that does not allow the picture in the back buffer to be copied into the display buffer before the display is refreshed. After the update of the back-up buffer is completed, the system is in a waiting state. When the display is refreshed, the backup cache is copied into the display cache, and the display card can draw a new picture in the backup cache, so that the FPS is effectively limited within the range of the refresh rate of the display.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 3 and may include one or more features of one or more of all of the embodiments described above.
According to the present embodiment, S322 includes:
determining period data indicating a frame time according to a period of a vertical synchronization signal; or
The period data indicating one frame time is determined based on an average value of periods of a plurality of vertical synchronization signals.
According to the embodiment, the period data are calculated according to one or more periods of the Vsync signal, so that the calculation precision of the period data is improved, the scanning time of the current frame is judged more accurately, and the synchronization of image scanning and pulse width modulation is ensured.
In one embodiment, determining the period data indicating one frame time according to the period of one Vsync signal may refer to directly taking the time of one Vsync signal period (e.g., the time of the previous frame) as the time of the current frame; the time of one Vsync signal period may be calculated, and the calculated result may be the time of the current frame. In one embodiment, determining the period data indicating one frame time according to an average value of periods of the Vsync signals may refer to calculating an average value according to the periods of the Vsync signals (such as the periods of the previous frames), and using the calculated average value as the time of the current frame; further calculation may be performed based on an average value of the times of the plurality of Vsync signal periods, and the calculated result may be the time of the current frame.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 3 and may include one or more features of one or more of all of the embodiments described above.
According to the present embodiment, S340 includes:
calculating the period of the pulse width modulation signal according to the period data and the clock signal;
modulating a driving current of the display device according to the on-time data and the period of the pulse width modulation signal to drive the display device;
wherein, the calculation accuracy of the period of the vertical synchronization signal is lower than that of the pulse width modulation signal.
According to the embodiment, the period of the PWM signal is generally specified by parameters of the display, and the period of the Vsync signal is determined by the Vsync signal period calculation module in the driving chip, and the calculation module in the chip can be made smaller by calculating the Vsync signal period with lower calculation accuracy, so that the calculation resources of the chip are saved, and the manufacturing cost of the chip is reduced.
In one embodiment, calculating the period of the PWM signal according to the period data and the clock signal may refer to performing a frequency division operation on the clock signal according to the period data and the picture resolution (e.g., 1920 × 1080) to determine the frequency of the PWM signal, thereby determining the period of the PWM signal.
In an embodiment, modulating the driving current of the display device to drive the display device according to the on-time data and the period of the PWM signal may refer to using the on-time data as a high level time of a pixel in a frame time, and using the period of the PWM signal as a period for modulating the pixel (there may be a plurality of periods of the PWM signal in a frame time), and dispersing the average or uneven time of a frame in each period of the PWM signal, where the duty ratio of each PWM period is determined by the on-time data.
In an embodiment, the calculation accuracy of the period of the Vsync signal may refer to the accuracy of calculating the period of the Vsync signal by the frequency of the clock signal. In one embodiment, the module for counting periods of Vsync signals receives a clock signal or clock pulse from a clock source, counts the number of clock signals by a counter with a certain precision, and represents the periods of Vsync signals (i.e., one frame time) according to the number of clock signals counted by the counter in the time interval between two Vsync signals. For example, the clock signal is transmitted 1000 times per second (once every 1 microsecond), the precision of the counter is 4 microseconds (that is, the counter determines whether the clock signal is received once every 4 microseconds, and counts once if the clock signal is received), and the minimum unit for calculating the period of the Vsync signal through counting by the counter is 4 microseconds. If the count result of the counter is 10 in one period of the Vsync signal, it means that the period of the Vsync signal is 40 microseconds.
In one embodiment, the calculation accuracy of the period of the PWM signal may refer to the accuracy of calculating the period of the PWM signal by the frequency of the clock signal. In one embodiment, the module for calculating the period of the PWM signal receives a clock signal or clock pulse from a clock source, and counts the number of clock signals by a counter with a certain precision, and represents the period of the PWM signal according to the number of clock signals counted in one period of the PWM signal. For example, the clock source sends a clock signal 1000 times per second, the precision of the counter in the PWM period calculation module is 2 microseconds, and the minimum unit for calculating the PWM signal period through the counting of the counter is 2 microseconds (higher than the calculation precision of the Vsync signal period). If the counting result of the counter is 5 within one period of the PWM signal, it means that the period of the PWM signal is 10 microseconds.
In one embodiment, the PWM signal period is calculated to 14 bits and the Vsync signal period is calculated to 13, 12, 11, or less bits.
A display driving apparatus 500 according to an embodiment of the present invention is described below with reference to fig. 5.
According to the present embodiment, the display driving apparatus 500 includes:
a generating module 510 for generating a clock signal;
a first calculating module 520 for calculating period data representing one frame time by a clock signal;
a second calculating module 530, configured to calculate on-time data of the pwm signal according to the period data and the pixel value of the target pixel;
and a modulation module 540, configured to modulate a driving current of the display device according to the on-time data to drive the display device.
For details of the generating module 510, the first calculating module 520, the second calculating module 530, and the modulating module 540, reference may be made to the description above for the embodiment of fig. 3.
In an embodiment, the second calculation module 530 is configured to:
the on-time data is calculated according to the following formula:
DON_TIME＝(DDISP/DFULL_SCALE)×DTF×r，
wherein D isON_TIMERepresenting on-time data, DDISPRepresenting pixel value, DFULL_SCALERepresenting the highest luminance value, D, of the target pixelTFRepresenting period data, r represents a positive real number less than or equal to 1.
In an embodiment, the generation module 510 is configured to:
a clock signal is generated by an internal clock source.
In one embodiment, the internal clock source comprises a quartz crystal oscillator, a silicon crystal oscillator, a microelectromechanical system oscillator, or a complementary metal oxide semiconductor oscillator.
In an embodiment, the first calculation module 520 is configured to:
calculating the period of the vertical synchronous signal through a clock signal;
the period data indicating one frame time is determined according to the period of the vertical synchronization signal.
In an embodiment, the first calculation module 520 is further configured to:
determining period data indicating a frame time according to a period of a vertical synchronization signal; or
The period data indicating one frame time is determined based on an average value of periods of a plurality of vertical synchronization signals.
In an embodiment, the modulation module 540 is configured to:
calculating the period of the pulse width modulation signal according to the period data and the clock signal;
modulating a driving current of the display device according to the on-time data and the period of the pulse width modulation signal to drive the display device;
wherein, the calculation accuracy of the period of the vertical synchronization signal is lower than that of the pulse width modulation signal.
The following describes the display driving chip 600 according to an embodiment of the invention with reference to fig. 6.
According to the present embodiment, the display driving chip 600 includes:
a clock generation unit 610 for generating a clock signal;
a frame time calculation unit 620 for calculating period data representing one frame time by a clock signal;
an on-time calculation unit 630 for calculating on-time data of the pulse width modulation signal based on the period data and the pixel value of the target pixel;
and a pulse width modulation driving circuit 640 for modulating a driving current of the display device according to the on-time data to drive the display device.
Details regarding the clock generation unit 610, the frame time calculation unit 620, the on-time calculation unit 630, and the pwm drive circuit 640 are referred to the description above with respect to the embodiment of fig. 3.
In one embodiment, the on-time calculation unit 630 is configured to:
the on-time data is calculated according to the following formula:
DON_TIME＝(DDISP/DFULL_SCALE)×DTF×r，
wherein D isON_TIMERepresenting on-time data, DDISPRepresenting pixel value, DFULL_SCALERepresenting the highest luminance value, D, of the target pixelTFRepresenting period data, r represents a positive real number less than or equal to 1.
In an embodiment, the clock generation unit 610 is configured to:
a clock signal is generated by an internal clock source.
In an embodiment, the frame time calculation unit 620 is configured to:
calculating the period of the vertical synchronous signal through a clock signal;
the period data indicating one frame time is determined according to the period of the vertical synchronization signal.
In an embodiment, the frame time calculation unit 620 is further configured to:
determining period data indicating a frame time according to a period of a vertical synchronization signal; or
The period data indicating one frame time is determined based on an average value of periods of a plurality of vertical synchronization signals.
In one embodiment, the pwm driver circuit 640 is configured to:
calculating the period of the pulse width modulation signal according to the period data and the clock signal;
modulating a driving current of the display device according to the on-time data and the period of the pulse width modulation signal to drive the display device;
wherein, the calculation accuracy of the period of the vertical synchronization signal is lower than that of the pulse width modulation signal.
A display device 700 according to an embodiment of the present application is described below in conjunction with fig. 7.
According to the present embodiment, the display apparatus 700 includes:
a display screen 710;
the display driving chip 720 is used for driving the display screen 710.
In one embodiment, the display device 700 may be a device capable of converting an electrical signal into image information. The display device may include a two-dimensional display device and a three-dimensional display device. The two-dimensional display device may include a cathode ray tube display (CRT), a light emitting diode display (LED), an electroluminescent display (ELD), a Plasma Display Panel (PDP), a Liquid Crystal Display (LCD), a thin film transistor display (TFT), an organic light emitting semiconductor display (OLED), an interferometric modulator display (IMOD), and the like. The three-dimensional display device may include a corner mirror display, an emission wavelength display, a laser display, a holographic display, a light field display, and the like.
In one embodiment, the display device 700 may be an LED backlight display, which includes a display screen including an LED backlight module and a display component array (such as a liquid crystal display component array) and a display driving chip for driving the LED backlight module.
In one embodiment, the display device 700 may be an LED display, including a display screen including an array of LED display elements and a display driver chip for driving the array of LED display elements.
The following describes a computer-readable storage medium according to an embodiment of the present application.
The computer readable storage medium according to the present embodiment has stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the steps in the display driving method according to various embodiments of the present application described hereinabove in the present specification.
In an embodiment, a computer-readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The concepts, principles and concepts of the invention have been described above in detail in connection with specific embodiments (including examples and illustrations). It will be appreciated by persons skilled in the art that embodiments of the invention are not limited to the specific forms disclosed above, and that many modifications, alterations and equivalents of the steps, methods, apparatus and components described in the above embodiments may be made by those skilled in the art after reading this specification, and that such modifications, alterations and equivalents are to be considered as falling within the scope of the invention. The scope of the invention is only limited by the claims.
Claims (11)
1. A display driving method comprising:
generating a clock signal;
calculating period data representing one frame time by the clock signal;
calculating on-time data of the pulse width modulation signal according to the period data and the pixel value of the target pixel;
and modulating the driving current of the display device according to the on-time data so as to drive the display device.
2. The display driving method according to claim 1, wherein the calculating on-time data of the pulse width modulation signal based on the period data and the pixel value of the target pixel comprises:
calculating the on-time data according to:
DON_TIME＝(DDISP/DFULL_SCALE)×DTF×r，
wherein D isON_TIMERepresenting said on-time data, DDISPRepresenting said pixel value, DFULL_SCALERepresenting the highest luminance value, D, of said target pixelTFRepresents the period data, and r represents a positive real number less than or equal to 1.
3. The display driving method according to claim 1, wherein the generating a clock signal comprises:
a clock signal is generated by an internal clock source.
4. The display driving method according to claim 3, wherein the internal clock source comprises a quartz crystal oscillator, a silicon crystal oscillator, a microelectromechanical system oscillator, or a complementary metal oxide semiconductor oscillator.
5. The display driving method according to claim 1, wherein said calculating, by the clock signal, period data representing one frame time includes:
calculating the period of a vertical synchronization signal through the clock signal;
and determining period data for representing one frame time according to the period of the vertical synchronization signal.
6. The display driving method according to claim 5, wherein the determining of the period data representing one frame time according to the period of the vertical synchronization signal comprises:
determining period data indicating a frame time according to a period of one of the vertical synchronization signals; or
The period data indicating one frame time is determined based on an average value of a plurality of periods of the vertical synchronization signal.
7. The display driving method according to claim 5, wherein the modulating a driving current of a display device according to the on-time data to drive the display device comprises:
calculating the period of the pulse width modulation signal according to the period data and the clock signal;
modulating a driving current of a display device according to the on-time data and the period of the pulse width modulation signal to drive the display device;
wherein the calculation accuracy of the period of the vertical synchronization signal is lower than the calculation accuracy of the period of the pulse width modulation signal.
8. A display driving apparatus comprising:
a generating module for generating a clock signal;
a first calculation module for calculating period data representing one frame time by the clock signal;
the second calculation module is used for calculating the on-time data of the pulse width modulation signal according to the period data and the pixel value of the target pixel;
and the modulation module is used for modulating the driving current of the display equipment according to the conduction time data so as to drive the display equipment.
9. A display driver chip comprising:
a clock generation unit for generating a clock signal;
a frame time calculation unit for calculating period data indicating a frame time by the clock signal;
the on-time calculating unit is used for calculating on-time data of the pulse width modulation signal according to the period data and the pixel value of the target pixel;
and the pulse width modulation driving circuit is used for modulating the driving current of the display equipment according to the conduction time data so as to drive the display equipment.
10. A display device, comprising:
a display screen;
the display driver chip of claim 9, configured to drive the display screen.
11. A computer-readable storage medium storing a computer program for executing the display driving method according to any one of claims 1 to 7.
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